1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Unisoc IOMMU driver 4 * 5 * Copyright (C) 2020 Unisoc, Inc. 6 * Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/errno.h> 13 #include <linux/iommu.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of_platform.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 20 #define SPRD_IOMMU_PAGE_SHIFT 12 21 #define SPRD_IOMMU_PAGE_SIZE SZ_4K 22 23 #define SPRD_EX_CFG 0x0 24 #define SPRD_IOMMU_VAOR_BYPASS BIT(4) 25 #define SPRD_IOMMU_GATE_EN BIT(1) 26 #define SPRD_IOMMU_EN BIT(0) 27 #define SPRD_EX_UPDATE 0x4 28 #define SPRD_EX_FIRST_VPN 0x8 29 #define SPRD_EX_VPN_RANGE 0xc 30 #define SPRD_EX_FIRST_PPN 0x10 31 #define SPRD_EX_DEFAULT_PPN 0x14 32 33 #define SPRD_IOMMU_VERSION 0x0 34 #define SPRD_VERSION_MASK GENMASK(15, 8) 35 #define SPRD_VERSION_SHIFT 0x8 36 #define SPRD_VAU_CFG 0x4 37 #define SPRD_VAU_UPDATE 0x8 38 #define SPRD_VAU_AUTH_CFG 0xc 39 #define SPRD_VAU_FIRST_PPN 0x10 40 #define SPRD_VAU_DEFAULT_PPN_RD 0x14 41 #define SPRD_VAU_DEFAULT_PPN_WR 0x18 42 #define SPRD_VAU_FIRST_VPN 0x1c 43 #define SPRD_VAU_VPN_RANGE 0x20 44 45 enum sprd_iommu_version { 46 SPRD_IOMMU_EX, 47 SPRD_IOMMU_VAU, 48 }; 49 50 /* 51 * struct sprd_iommu_device - high-level sprd IOMMU device representation, 52 * including hardware information and configuration, also driver data, etc 53 * 54 * @ver: sprd IOMMU IP version 55 * @prot_page_va: protect page base virtual address 56 * @prot_page_pa: protect page base physical address, data would be 57 * written to here while translation fault 58 * @base: mapped base address for accessing registers 59 * @dev: pointer to basic device structure 60 * @iommu: IOMMU core representation 61 * @group: IOMMU group 62 * @eb: gate clock which controls IOMMU access 63 */ 64 struct sprd_iommu_device { 65 struct sprd_iommu_domain *dom; 66 enum sprd_iommu_version ver; 67 u32 *prot_page_va; 68 dma_addr_t prot_page_pa; 69 void __iomem *base; 70 struct device *dev; 71 struct iommu_device iommu; 72 struct iommu_group *group; 73 struct clk *eb; 74 }; 75 76 struct sprd_iommu_domain { 77 spinlock_t pgtlock; /* lock for page table */ 78 struct iommu_domain domain; 79 u32 *pgt_va; /* page table virtual address base */ 80 dma_addr_t pgt_pa; /* page table physical address base */ 81 struct sprd_iommu_device *sdev; 82 }; 83 84 static const struct iommu_ops sprd_iommu_ops; 85 86 static struct sprd_iommu_domain *to_sprd_domain(struct iommu_domain *dom) 87 { 88 return container_of(dom, struct sprd_iommu_domain, domain); 89 } 90 91 static inline void 92 sprd_iommu_write(struct sprd_iommu_device *sdev, unsigned int reg, u32 val) 93 { 94 writel_relaxed(val, sdev->base + reg); 95 } 96 97 static inline u32 98 sprd_iommu_read(struct sprd_iommu_device *sdev, unsigned int reg) 99 { 100 return readl_relaxed(sdev->base + reg); 101 } 102 103 static inline void 104 sprd_iommu_update_bits(struct sprd_iommu_device *sdev, unsigned int reg, 105 u32 mask, u32 shift, u32 val) 106 { 107 u32 t = sprd_iommu_read(sdev, reg); 108 109 t = (t & (~(mask << shift))) | ((val & mask) << shift); 110 sprd_iommu_write(sdev, reg, t); 111 } 112 113 static inline int 114 sprd_iommu_get_version(struct sprd_iommu_device *sdev) 115 { 116 int ver = (sprd_iommu_read(sdev, SPRD_IOMMU_VERSION) & 117 SPRD_VERSION_MASK) >> SPRD_VERSION_SHIFT; 118 119 switch (ver) { 120 case SPRD_IOMMU_EX: 121 case SPRD_IOMMU_VAU: 122 return ver; 123 default: 124 return -EINVAL; 125 } 126 } 127 128 static size_t 129 sprd_iommu_pgt_size(struct iommu_domain *domain) 130 { 131 return ((domain->geometry.aperture_end - 132 domain->geometry.aperture_start + 1) >> 133 SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32); 134 } 135 136 static struct iommu_domain *sprd_iommu_domain_alloc(unsigned int domain_type) 137 { 138 struct sprd_iommu_domain *dom; 139 140 if (domain_type != IOMMU_DOMAIN_DMA && domain_type != IOMMU_DOMAIN_UNMANAGED) 141 return NULL; 142 143 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 144 if (!dom) 145 return NULL; 146 147 spin_lock_init(&dom->pgtlock); 148 149 dom->domain.geometry.aperture_start = 0; 150 dom->domain.geometry.aperture_end = SZ_256M - 1; 151 152 return &dom->domain; 153 } 154 155 static void sprd_iommu_first_vpn(struct sprd_iommu_domain *dom) 156 { 157 struct sprd_iommu_device *sdev = dom->sdev; 158 u32 val; 159 unsigned int reg; 160 161 if (sdev->ver == SPRD_IOMMU_EX) 162 reg = SPRD_EX_FIRST_VPN; 163 else 164 reg = SPRD_VAU_FIRST_VPN; 165 166 val = dom->domain.geometry.aperture_start >> SPRD_IOMMU_PAGE_SHIFT; 167 sprd_iommu_write(sdev, reg, val); 168 } 169 170 static void sprd_iommu_vpn_range(struct sprd_iommu_domain *dom) 171 { 172 struct sprd_iommu_device *sdev = dom->sdev; 173 u32 val; 174 unsigned int reg; 175 176 if (sdev->ver == SPRD_IOMMU_EX) 177 reg = SPRD_EX_VPN_RANGE; 178 else 179 reg = SPRD_VAU_VPN_RANGE; 180 181 val = (dom->domain.geometry.aperture_end - 182 dom->domain.geometry.aperture_start) >> SPRD_IOMMU_PAGE_SHIFT; 183 sprd_iommu_write(sdev, reg, val); 184 } 185 186 static void sprd_iommu_first_ppn(struct sprd_iommu_domain *dom) 187 { 188 u32 val = dom->pgt_pa >> SPRD_IOMMU_PAGE_SHIFT; 189 struct sprd_iommu_device *sdev = dom->sdev; 190 unsigned int reg; 191 192 if (sdev->ver == SPRD_IOMMU_EX) 193 reg = SPRD_EX_FIRST_PPN; 194 else 195 reg = SPRD_VAU_FIRST_PPN; 196 197 sprd_iommu_write(sdev, reg, val); 198 } 199 200 static void sprd_iommu_default_ppn(struct sprd_iommu_device *sdev) 201 { 202 u32 val = sdev->prot_page_pa >> SPRD_IOMMU_PAGE_SHIFT; 203 204 if (sdev->ver == SPRD_IOMMU_EX) { 205 sprd_iommu_write(sdev, SPRD_EX_DEFAULT_PPN, val); 206 } else if (sdev->ver == SPRD_IOMMU_VAU) { 207 sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_RD, val); 208 sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_WR, val); 209 } 210 } 211 212 static void sprd_iommu_hw_en(struct sprd_iommu_device *sdev, bool en) 213 { 214 unsigned int reg_cfg; 215 u32 mask, val; 216 217 if (sdev->ver == SPRD_IOMMU_EX) 218 reg_cfg = SPRD_EX_CFG; 219 else 220 reg_cfg = SPRD_VAU_CFG; 221 222 mask = SPRD_IOMMU_EN | SPRD_IOMMU_GATE_EN; 223 val = en ? mask : 0; 224 sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val); 225 } 226 227 static void sprd_iommu_cleanup(struct sprd_iommu_domain *dom) 228 { 229 size_t pgt_size; 230 231 /* Nothing need to do if the domain hasn't been attached */ 232 if (!dom->sdev) 233 return; 234 235 pgt_size = sprd_iommu_pgt_size(&dom->domain); 236 dma_free_coherent(dom->sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa); 237 dom->sdev = NULL; 238 sprd_iommu_hw_en(dom->sdev, false); 239 } 240 241 static void sprd_iommu_domain_free(struct iommu_domain *domain) 242 { 243 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 244 245 sprd_iommu_cleanup(dom); 246 kfree(dom); 247 } 248 249 static int sprd_iommu_attach_device(struct iommu_domain *domain, 250 struct device *dev) 251 { 252 struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev); 253 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 254 size_t pgt_size = sprd_iommu_pgt_size(domain); 255 256 /* The device is attached to this domain */ 257 if (sdev->dom == dom) 258 return 0; 259 260 /* The first time that domain is attaching to a device */ 261 if (!dom->pgt_va) { 262 dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL); 263 if (!dom->pgt_va) 264 return -ENOMEM; 265 266 dom->sdev = sdev; 267 } 268 269 sdev->dom = dom; 270 271 /* 272 * One sprd IOMMU serves one client device only, disabled it before 273 * configure mapping table to avoid access conflict in case other 274 * mapping table is stored in. 275 */ 276 sprd_iommu_hw_en(sdev, false); 277 sprd_iommu_first_ppn(dom); 278 sprd_iommu_first_vpn(dom); 279 sprd_iommu_vpn_range(dom); 280 sprd_iommu_default_ppn(sdev); 281 sprd_iommu_hw_en(sdev, true); 282 283 return 0; 284 } 285 286 static int sprd_iommu_map(struct iommu_domain *domain, unsigned long iova, 287 phys_addr_t paddr, size_t pgsize, size_t pgcount, 288 int prot, gfp_t gfp, size_t *mapped) 289 { 290 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 291 size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE; 292 unsigned long flags; 293 unsigned int i; 294 u32 *pgt_base_iova; 295 u32 pabase = (u32)paddr; 296 unsigned long start = domain->geometry.aperture_start; 297 unsigned long end = domain->geometry.aperture_end; 298 299 if (!dom->sdev) { 300 pr_err("No sprd_iommu_device attached to the domain\n"); 301 return -EINVAL; 302 } 303 304 if (iova < start || (iova + size) > (end + 1)) { 305 dev_err(dom->sdev->dev, "(iova(0x%lx) + size(%zx)) are not in the range!\n", 306 iova, size); 307 return -EINVAL; 308 } 309 310 pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT); 311 312 spin_lock_irqsave(&dom->pgtlock, flags); 313 for (i = 0; i < pgcount; i++) { 314 pgt_base_iova[i] = pabase >> SPRD_IOMMU_PAGE_SHIFT; 315 pabase += SPRD_IOMMU_PAGE_SIZE; 316 } 317 spin_unlock_irqrestore(&dom->pgtlock, flags); 318 319 *mapped = size; 320 return 0; 321 } 322 323 static size_t sprd_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 324 size_t pgsize, size_t pgcount, 325 struct iommu_iotlb_gather *iotlb_gather) 326 { 327 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 328 unsigned long flags; 329 u32 *pgt_base_iova; 330 size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE; 331 unsigned long start = domain->geometry.aperture_start; 332 unsigned long end = domain->geometry.aperture_end; 333 334 if (iova < start || (iova + size) > (end + 1)) 335 return 0; 336 337 pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT); 338 339 spin_lock_irqsave(&dom->pgtlock, flags); 340 memset(pgt_base_iova, 0, pgcount * sizeof(u32)); 341 spin_unlock_irqrestore(&dom->pgtlock, flags); 342 343 return size; 344 } 345 346 static void sprd_iommu_sync_map(struct iommu_domain *domain, 347 unsigned long iova, size_t size) 348 { 349 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 350 unsigned int reg; 351 352 if (dom->sdev->ver == SPRD_IOMMU_EX) 353 reg = SPRD_EX_UPDATE; 354 else 355 reg = SPRD_VAU_UPDATE; 356 357 /* clear IOMMU TLB buffer after page table updated */ 358 sprd_iommu_write(dom->sdev, reg, 0xffffffff); 359 } 360 361 static void sprd_iommu_sync(struct iommu_domain *domain, 362 struct iommu_iotlb_gather *iotlb_gather) 363 { 364 sprd_iommu_sync_map(domain, 0, 0); 365 } 366 367 static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain, 368 dma_addr_t iova) 369 { 370 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 371 unsigned long flags; 372 phys_addr_t pa; 373 unsigned long start = domain->geometry.aperture_start; 374 unsigned long end = domain->geometry.aperture_end; 375 376 if (WARN_ON(iova < start || iova > end)) 377 return 0; 378 379 spin_lock_irqsave(&dom->pgtlock, flags); 380 pa = *(dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT)); 381 pa = (pa << SPRD_IOMMU_PAGE_SHIFT) + ((iova - start) & (SPRD_IOMMU_PAGE_SIZE - 1)); 382 spin_unlock_irqrestore(&dom->pgtlock, flags); 383 384 return pa; 385 } 386 387 static struct iommu_device *sprd_iommu_probe_device(struct device *dev) 388 { 389 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 390 struct sprd_iommu_device *sdev; 391 392 if (!fwspec || fwspec->ops != &sprd_iommu_ops) 393 return ERR_PTR(-ENODEV); 394 395 sdev = dev_iommu_priv_get(dev); 396 397 return &sdev->iommu; 398 } 399 400 static struct iommu_group *sprd_iommu_device_group(struct device *dev) 401 { 402 struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev); 403 404 return iommu_group_ref_get(sdev->group); 405 } 406 407 static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 408 { 409 struct platform_device *pdev; 410 411 if (!dev_iommu_priv_get(dev)) { 412 pdev = of_find_device_by_node(args->np); 413 dev_iommu_priv_set(dev, platform_get_drvdata(pdev)); 414 platform_device_put(pdev); 415 } 416 417 return 0; 418 } 419 420 421 static const struct iommu_ops sprd_iommu_ops = { 422 .domain_alloc = sprd_iommu_domain_alloc, 423 .probe_device = sprd_iommu_probe_device, 424 .device_group = sprd_iommu_device_group, 425 .of_xlate = sprd_iommu_of_xlate, 426 .pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE, 427 .owner = THIS_MODULE, 428 .default_domain_ops = &(const struct iommu_domain_ops) { 429 .attach_dev = sprd_iommu_attach_device, 430 .map_pages = sprd_iommu_map, 431 .unmap_pages = sprd_iommu_unmap, 432 .iotlb_sync_map = sprd_iommu_sync_map, 433 .iotlb_sync = sprd_iommu_sync, 434 .iova_to_phys = sprd_iommu_iova_to_phys, 435 .free = sprd_iommu_domain_free, 436 } 437 }; 438 439 static const struct of_device_id sprd_iommu_of_match[] = { 440 { .compatible = "sprd,iommu-v1" }, 441 { }, 442 }; 443 MODULE_DEVICE_TABLE(of, sprd_iommu_of_match); 444 445 /* 446 * Clock is not required, access to some of IOMMUs is controlled by gate 447 * clk, enabled clocks for that kind of IOMMUs before accessing. 448 * Return 0 for success or no clocks found. 449 */ 450 static int sprd_iommu_clk_enable(struct sprd_iommu_device *sdev) 451 { 452 struct clk *eb; 453 454 eb = devm_clk_get_optional(sdev->dev, NULL); 455 if (!eb) 456 return 0; 457 458 if (IS_ERR(eb)) 459 return PTR_ERR(eb); 460 461 sdev->eb = eb; 462 return clk_prepare_enable(eb); 463 } 464 465 static void sprd_iommu_clk_disable(struct sprd_iommu_device *sdev) 466 { 467 if (sdev->eb) 468 clk_disable_unprepare(sdev->eb); 469 } 470 471 static int sprd_iommu_probe(struct platform_device *pdev) 472 { 473 struct sprd_iommu_device *sdev; 474 struct device *dev = &pdev->dev; 475 void __iomem *base; 476 int ret; 477 478 sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL); 479 if (!sdev) 480 return -ENOMEM; 481 482 base = devm_platform_ioremap_resource(pdev, 0); 483 if (IS_ERR(base)) { 484 dev_err(dev, "Failed to get ioremap resource.\n"); 485 return PTR_ERR(base); 486 } 487 sdev->base = base; 488 489 sdev->prot_page_va = dma_alloc_coherent(dev, SPRD_IOMMU_PAGE_SIZE, 490 &sdev->prot_page_pa, GFP_KERNEL); 491 if (!sdev->prot_page_va) 492 return -ENOMEM; 493 494 platform_set_drvdata(pdev, sdev); 495 sdev->dev = dev; 496 497 /* All the client devices are in the same iommu-group */ 498 sdev->group = iommu_group_alloc(); 499 if (IS_ERR(sdev->group)) { 500 ret = PTR_ERR(sdev->group); 501 goto free_page; 502 } 503 504 ret = iommu_device_sysfs_add(&sdev->iommu, dev, NULL, dev_name(dev)); 505 if (ret) 506 goto put_group; 507 508 ret = iommu_device_register(&sdev->iommu, &sprd_iommu_ops, dev); 509 if (ret) 510 goto remove_sysfs; 511 512 ret = sprd_iommu_clk_enable(sdev); 513 if (ret) 514 goto unregister_iommu; 515 516 ret = sprd_iommu_get_version(sdev); 517 if (ret < 0) { 518 dev_err(dev, "IOMMU version(%d) is invalid.\n", ret); 519 goto disable_clk; 520 } 521 sdev->ver = ret; 522 523 return 0; 524 525 disable_clk: 526 sprd_iommu_clk_disable(sdev); 527 unregister_iommu: 528 iommu_device_unregister(&sdev->iommu); 529 remove_sysfs: 530 iommu_device_sysfs_remove(&sdev->iommu); 531 put_group: 532 iommu_group_put(sdev->group); 533 free_page: 534 dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa); 535 return ret; 536 } 537 538 static void sprd_iommu_remove(struct platform_device *pdev) 539 { 540 struct sprd_iommu_device *sdev = platform_get_drvdata(pdev); 541 542 dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa); 543 544 iommu_group_put(sdev->group); 545 sdev->group = NULL; 546 547 platform_set_drvdata(pdev, NULL); 548 iommu_device_sysfs_remove(&sdev->iommu); 549 iommu_device_unregister(&sdev->iommu); 550 } 551 552 static struct platform_driver sprd_iommu_driver = { 553 .driver = { 554 .name = "sprd-iommu", 555 .of_match_table = sprd_iommu_of_match, 556 .suppress_bind_attrs = true, 557 }, 558 .probe = sprd_iommu_probe, 559 .remove_new = sprd_iommu_remove, 560 }; 561 module_platform_driver(sprd_iommu_driver); 562 563 MODULE_DESCRIPTION("IOMMU driver for Unisoc SoCs"); 564 MODULE_ALIAS("platform:sprd-iommu"); 565 MODULE_LICENSE("GPL"); 566