1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Unisoc IOMMU driver 4 * 5 * Copyright (C) 2020 Unisoc, Inc. 6 * Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/errno.h> 13 #include <linux/iommu.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of_platform.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 21 #define SPRD_IOMMU_PAGE_SHIFT 12 22 #define SPRD_IOMMU_PAGE_SIZE SZ_4K 23 24 #define SPRD_EX_CFG 0x0 25 #define SPRD_IOMMU_VAOR_BYPASS BIT(4) 26 #define SPRD_IOMMU_GATE_EN BIT(1) 27 #define SPRD_IOMMU_EN BIT(0) 28 #define SPRD_EX_UPDATE 0x4 29 #define SPRD_EX_FIRST_VPN 0x8 30 #define SPRD_EX_VPN_RANGE 0xc 31 #define SPRD_EX_FIRST_PPN 0x10 32 #define SPRD_EX_DEFAULT_PPN 0x14 33 34 #define SPRD_IOMMU_VERSION 0x0 35 #define SPRD_VERSION_MASK GENMASK(15, 8) 36 #define SPRD_VERSION_SHIFT 0x8 37 #define SPRD_VAU_CFG 0x4 38 #define SPRD_VAU_UPDATE 0x8 39 #define SPRD_VAU_AUTH_CFG 0xc 40 #define SPRD_VAU_FIRST_PPN 0x10 41 #define SPRD_VAU_DEFAULT_PPN_RD 0x14 42 #define SPRD_VAU_DEFAULT_PPN_WR 0x18 43 #define SPRD_VAU_FIRST_VPN 0x1c 44 #define SPRD_VAU_VPN_RANGE 0x20 45 46 enum sprd_iommu_version { 47 SPRD_IOMMU_EX, 48 SPRD_IOMMU_VAU, 49 }; 50 51 /* 52 * struct sprd_iommu_device - high-level sprd IOMMU device representation, 53 * including hardware information and configuration, also driver data, etc 54 * 55 * @ver: sprd IOMMU IP version 56 * @prot_page_va: protect page base virtual address 57 * @prot_page_pa: protect page base physical address, data would be 58 * written to here while translation fault 59 * @base: mapped base address for accessing registers 60 * @dev: pointer to basic device structure 61 * @iommu: IOMMU core representation 62 * @group: IOMMU group 63 * @eb: gate clock which controls IOMMU access 64 */ 65 struct sprd_iommu_device { 66 struct sprd_iommu_domain *dom; 67 enum sprd_iommu_version ver; 68 u32 *prot_page_va; 69 dma_addr_t prot_page_pa; 70 void __iomem *base; 71 struct device *dev; 72 struct iommu_device iommu; 73 struct iommu_group *group; 74 struct clk *eb; 75 }; 76 77 struct sprd_iommu_domain { 78 spinlock_t pgtlock; /* lock for page table */ 79 struct iommu_domain domain; 80 u32 *pgt_va; /* page table virtual address base */ 81 dma_addr_t pgt_pa; /* page table physical address base */ 82 struct sprd_iommu_device *sdev; 83 }; 84 85 static const struct iommu_ops sprd_iommu_ops; 86 87 static struct sprd_iommu_domain *to_sprd_domain(struct iommu_domain *dom) 88 { 89 return container_of(dom, struct sprd_iommu_domain, domain); 90 } 91 92 static inline void 93 sprd_iommu_write(struct sprd_iommu_device *sdev, unsigned int reg, u32 val) 94 { 95 writel_relaxed(val, sdev->base + reg); 96 } 97 98 static inline u32 99 sprd_iommu_read(struct sprd_iommu_device *sdev, unsigned int reg) 100 { 101 return readl_relaxed(sdev->base + reg); 102 } 103 104 static inline void 105 sprd_iommu_update_bits(struct sprd_iommu_device *sdev, unsigned int reg, 106 u32 mask, u32 shift, u32 val) 107 { 108 u32 t = sprd_iommu_read(sdev, reg); 109 110 t = (t & (~(mask << shift))) | ((val & mask) << shift); 111 sprd_iommu_write(sdev, reg, t); 112 } 113 114 static inline int 115 sprd_iommu_get_version(struct sprd_iommu_device *sdev) 116 { 117 int ver = (sprd_iommu_read(sdev, SPRD_IOMMU_VERSION) & 118 SPRD_VERSION_MASK) >> SPRD_VERSION_SHIFT; 119 120 switch (ver) { 121 case SPRD_IOMMU_EX: 122 case SPRD_IOMMU_VAU: 123 return ver; 124 default: 125 return -EINVAL; 126 } 127 } 128 129 static size_t 130 sprd_iommu_pgt_size(struct iommu_domain *domain) 131 { 132 return ((domain->geometry.aperture_end - 133 domain->geometry.aperture_start + 1) >> 134 SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32); 135 } 136 137 static struct iommu_domain *sprd_iommu_domain_alloc(unsigned int domain_type) 138 { 139 struct sprd_iommu_domain *dom; 140 141 if (domain_type != IOMMU_DOMAIN_DMA && domain_type != IOMMU_DOMAIN_UNMANAGED) 142 return NULL; 143 144 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 145 if (!dom) 146 return NULL; 147 148 spin_lock_init(&dom->pgtlock); 149 150 dom->domain.geometry.aperture_start = 0; 151 dom->domain.geometry.aperture_end = SZ_256M - 1; 152 153 return &dom->domain; 154 } 155 156 static void sprd_iommu_first_vpn(struct sprd_iommu_domain *dom) 157 { 158 struct sprd_iommu_device *sdev = dom->sdev; 159 u32 val; 160 unsigned int reg; 161 162 if (sdev->ver == SPRD_IOMMU_EX) 163 reg = SPRD_EX_FIRST_VPN; 164 else 165 reg = SPRD_VAU_FIRST_VPN; 166 167 val = dom->domain.geometry.aperture_start >> SPRD_IOMMU_PAGE_SHIFT; 168 sprd_iommu_write(sdev, reg, val); 169 } 170 171 static void sprd_iommu_vpn_range(struct sprd_iommu_domain *dom) 172 { 173 struct sprd_iommu_device *sdev = dom->sdev; 174 u32 val; 175 unsigned int reg; 176 177 if (sdev->ver == SPRD_IOMMU_EX) 178 reg = SPRD_EX_VPN_RANGE; 179 else 180 reg = SPRD_VAU_VPN_RANGE; 181 182 val = (dom->domain.geometry.aperture_end - 183 dom->domain.geometry.aperture_start) >> SPRD_IOMMU_PAGE_SHIFT; 184 sprd_iommu_write(sdev, reg, val); 185 } 186 187 static void sprd_iommu_first_ppn(struct sprd_iommu_domain *dom) 188 { 189 u32 val = dom->pgt_pa >> SPRD_IOMMU_PAGE_SHIFT; 190 struct sprd_iommu_device *sdev = dom->sdev; 191 unsigned int reg; 192 193 if (sdev->ver == SPRD_IOMMU_EX) 194 reg = SPRD_EX_FIRST_PPN; 195 else 196 reg = SPRD_VAU_FIRST_PPN; 197 198 sprd_iommu_write(sdev, reg, val); 199 } 200 201 static void sprd_iommu_default_ppn(struct sprd_iommu_device *sdev) 202 { 203 u32 val = sdev->prot_page_pa >> SPRD_IOMMU_PAGE_SHIFT; 204 205 if (sdev->ver == SPRD_IOMMU_EX) { 206 sprd_iommu_write(sdev, SPRD_EX_DEFAULT_PPN, val); 207 } else if (sdev->ver == SPRD_IOMMU_VAU) { 208 sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_RD, val); 209 sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_WR, val); 210 } 211 } 212 213 static void sprd_iommu_hw_en(struct sprd_iommu_device *sdev, bool en) 214 { 215 unsigned int reg_cfg; 216 u32 mask, val; 217 218 if (sdev->ver == SPRD_IOMMU_EX) 219 reg_cfg = SPRD_EX_CFG; 220 else 221 reg_cfg = SPRD_VAU_CFG; 222 223 mask = SPRD_IOMMU_EN | SPRD_IOMMU_GATE_EN; 224 val = en ? mask : 0; 225 sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val); 226 } 227 228 static void sprd_iommu_cleanup(struct sprd_iommu_domain *dom) 229 { 230 size_t pgt_size; 231 232 /* Nothing need to do if the domain hasn't been attached */ 233 if (!dom->sdev) 234 return; 235 236 pgt_size = sprd_iommu_pgt_size(&dom->domain); 237 dma_free_coherent(dom->sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa); 238 dom->sdev = NULL; 239 sprd_iommu_hw_en(dom->sdev, false); 240 } 241 242 static void sprd_iommu_domain_free(struct iommu_domain *domain) 243 { 244 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 245 246 sprd_iommu_cleanup(dom); 247 kfree(dom); 248 } 249 250 static int sprd_iommu_attach_device(struct iommu_domain *domain, 251 struct device *dev) 252 { 253 struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev); 254 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 255 size_t pgt_size = sprd_iommu_pgt_size(domain); 256 257 /* The device is attached to this domain */ 258 if (sdev->dom == dom) 259 return 0; 260 261 /* The first time that domain is attaching to a device */ 262 if (!dom->pgt_va) { 263 dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL); 264 if (!dom->pgt_va) 265 return -ENOMEM; 266 267 dom->sdev = sdev; 268 } 269 270 sdev->dom = dom; 271 272 /* 273 * One sprd IOMMU serves one client device only, disabled it before 274 * configure mapping table to avoid access conflict in case other 275 * mapping table is stored in. 276 */ 277 sprd_iommu_hw_en(sdev, false); 278 sprd_iommu_first_ppn(dom); 279 sprd_iommu_first_vpn(dom); 280 sprd_iommu_vpn_range(dom); 281 sprd_iommu_default_ppn(sdev); 282 sprd_iommu_hw_en(sdev, true); 283 284 return 0; 285 } 286 287 static int sprd_iommu_map(struct iommu_domain *domain, unsigned long iova, 288 phys_addr_t paddr, size_t pgsize, size_t pgcount, 289 int prot, gfp_t gfp, size_t *mapped) 290 { 291 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 292 size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE; 293 unsigned long flags; 294 unsigned int i; 295 u32 *pgt_base_iova; 296 u32 pabase = (u32)paddr; 297 unsigned long start = domain->geometry.aperture_start; 298 unsigned long end = domain->geometry.aperture_end; 299 300 if (!dom->sdev) { 301 pr_err("No sprd_iommu_device attached to the domain\n"); 302 return -EINVAL; 303 } 304 305 if (iova < start || (iova + size) > (end + 1)) { 306 dev_err(dom->sdev->dev, "(iova(0x%lx) + size(%zx)) are not in the range!\n", 307 iova, size); 308 return -EINVAL; 309 } 310 311 pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT); 312 313 spin_lock_irqsave(&dom->pgtlock, flags); 314 for (i = 0; i < pgcount; i++) { 315 pgt_base_iova[i] = pabase >> SPRD_IOMMU_PAGE_SHIFT; 316 pabase += SPRD_IOMMU_PAGE_SIZE; 317 } 318 spin_unlock_irqrestore(&dom->pgtlock, flags); 319 320 *mapped = size; 321 return 0; 322 } 323 324 static size_t sprd_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 325 size_t pgsize, size_t pgcount, 326 struct iommu_iotlb_gather *iotlb_gather) 327 { 328 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 329 unsigned long flags; 330 u32 *pgt_base_iova; 331 size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE; 332 unsigned long start = domain->geometry.aperture_start; 333 unsigned long end = domain->geometry.aperture_end; 334 335 if (iova < start || (iova + size) > (end + 1)) 336 return 0; 337 338 pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT); 339 340 spin_lock_irqsave(&dom->pgtlock, flags); 341 memset(pgt_base_iova, 0, pgcount * sizeof(u32)); 342 spin_unlock_irqrestore(&dom->pgtlock, flags); 343 344 return size; 345 } 346 347 static void sprd_iommu_sync_map(struct iommu_domain *domain, 348 unsigned long iova, size_t size) 349 { 350 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 351 unsigned int reg; 352 353 if (dom->sdev->ver == SPRD_IOMMU_EX) 354 reg = SPRD_EX_UPDATE; 355 else 356 reg = SPRD_VAU_UPDATE; 357 358 /* clear IOMMU TLB buffer after page table updated */ 359 sprd_iommu_write(dom->sdev, reg, 0xffffffff); 360 } 361 362 static void sprd_iommu_sync(struct iommu_domain *domain, 363 struct iommu_iotlb_gather *iotlb_gather) 364 { 365 sprd_iommu_sync_map(domain, 0, 0); 366 } 367 368 static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain, 369 dma_addr_t iova) 370 { 371 struct sprd_iommu_domain *dom = to_sprd_domain(domain); 372 unsigned long flags; 373 phys_addr_t pa; 374 unsigned long start = domain->geometry.aperture_start; 375 unsigned long end = domain->geometry.aperture_end; 376 377 if (WARN_ON(iova < start || iova > end)) 378 return 0; 379 380 spin_lock_irqsave(&dom->pgtlock, flags); 381 pa = *(dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT)); 382 pa = (pa << SPRD_IOMMU_PAGE_SHIFT) + ((iova - start) & (SPRD_IOMMU_PAGE_SIZE - 1)); 383 spin_unlock_irqrestore(&dom->pgtlock, flags); 384 385 return pa; 386 } 387 388 static struct iommu_device *sprd_iommu_probe_device(struct device *dev) 389 { 390 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 391 struct sprd_iommu_device *sdev; 392 393 if (!fwspec || fwspec->ops != &sprd_iommu_ops) 394 return ERR_PTR(-ENODEV); 395 396 sdev = dev_iommu_priv_get(dev); 397 398 return &sdev->iommu; 399 } 400 401 static struct iommu_group *sprd_iommu_device_group(struct device *dev) 402 { 403 struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev); 404 405 return iommu_group_ref_get(sdev->group); 406 } 407 408 static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 409 { 410 struct platform_device *pdev; 411 412 if (!dev_iommu_priv_get(dev)) { 413 pdev = of_find_device_by_node(args->np); 414 dev_iommu_priv_set(dev, platform_get_drvdata(pdev)); 415 platform_device_put(pdev); 416 } 417 418 return 0; 419 } 420 421 422 static const struct iommu_ops sprd_iommu_ops = { 423 .domain_alloc = sprd_iommu_domain_alloc, 424 .probe_device = sprd_iommu_probe_device, 425 .device_group = sprd_iommu_device_group, 426 .of_xlate = sprd_iommu_of_xlate, 427 .pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE, 428 .owner = THIS_MODULE, 429 .default_domain_ops = &(const struct iommu_domain_ops) { 430 .attach_dev = sprd_iommu_attach_device, 431 .map_pages = sprd_iommu_map, 432 .unmap_pages = sprd_iommu_unmap, 433 .iotlb_sync_map = sprd_iommu_sync_map, 434 .iotlb_sync = sprd_iommu_sync, 435 .iova_to_phys = sprd_iommu_iova_to_phys, 436 .free = sprd_iommu_domain_free, 437 } 438 }; 439 440 static const struct of_device_id sprd_iommu_of_match[] = { 441 { .compatible = "sprd,iommu-v1" }, 442 { }, 443 }; 444 MODULE_DEVICE_TABLE(of, sprd_iommu_of_match); 445 446 /* 447 * Clock is not required, access to some of IOMMUs is controlled by gate 448 * clk, enabled clocks for that kind of IOMMUs before accessing. 449 * Return 0 for success or no clocks found. 450 */ 451 static int sprd_iommu_clk_enable(struct sprd_iommu_device *sdev) 452 { 453 struct clk *eb; 454 455 eb = devm_clk_get_optional(sdev->dev, NULL); 456 if (!eb) 457 return 0; 458 459 if (IS_ERR(eb)) 460 return PTR_ERR(eb); 461 462 sdev->eb = eb; 463 return clk_prepare_enable(eb); 464 } 465 466 static void sprd_iommu_clk_disable(struct sprd_iommu_device *sdev) 467 { 468 if (sdev->eb) 469 clk_disable_unprepare(sdev->eb); 470 } 471 472 static int sprd_iommu_probe(struct platform_device *pdev) 473 { 474 struct sprd_iommu_device *sdev; 475 struct device *dev = &pdev->dev; 476 void __iomem *base; 477 int ret; 478 479 sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL); 480 if (!sdev) 481 return -ENOMEM; 482 483 base = devm_platform_ioremap_resource(pdev, 0); 484 if (IS_ERR(base)) { 485 dev_err(dev, "Failed to get ioremap resource.\n"); 486 return PTR_ERR(base); 487 } 488 sdev->base = base; 489 490 sdev->prot_page_va = dma_alloc_coherent(dev, SPRD_IOMMU_PAGE_SIZE, 491 &sdev->prot_page_pa, GFP_KERNEL); 492 if (!sdev->prot_page_va) 493 return -ENOMEM; 494 495 platform_set_drvdata(pdev, sdev); 496 sdev->dev = dev; 497 498 /* All the client devices are in the same iommu-group */ 499 sdev->group = iommu_group_alloc(); 500 if (IS_ERR(sdev->group)) { 501 ret = PTR_ERR(sdev->group); 502 goto free_page; 503 } 504 505 ret = iommu_device_sysfs_add(&sdev->iommu, dev, NULL, dev_name(dev)); 506 if (ret) 507 goto put_group; 508 509 ret = iommu_device_register(&sdev->iommu, &sprd_iommu_ops, dev); 510 if (ret) 511 goto remove_sysfs; 512 513 ret = sprd_iommu_clk_enable(sdev); 514 if (ret) 515 goto unregister_iommu; 516 517 ret = sprd_iommu_get_version(sdev); 518 if (ret < 0) { 519 dev_err(dev, "IOMMU version(%d) is invalid.\n", ret); 520 goto disable_clk; 521 } 522 sdev->ver = ret; 523 524 return 0; 525 526 disable_clk: 527 sprd_iommu_clk_disable(sdev); 528 unregister_iommu: 529 iommu_device_unregister(&sdev->iommu); 530 remove_sysfs: 531 iommu_device_sysfs_remove(&sdev->iommu); 532 put_group: 533 iommu_group_put(sdev->group); 534 free_page: 535 dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa); 536 return ret; 537 } 538 539 static void sprd_iommu_remove(struct platform_device *pdev) 540 { 541 struct sprd_iommu_device *sdev = platform_get_drvdata(pdev); 542 543 dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa); 544 545 iommu_group_put(sdev->group); 546 sdev->group = NULL; 547 548 platform_set_drvdata(pdev, NULL); 549 iommu_device_sysfs_remove(&sdev->iommu); 550 iommu_device_unregister(&sdev->iommu); 551 } 552 553 static struct platform_driver sprd_iommu_driver = { 554 .driver = { 555 .name = "sprd-iommu", 556 .of_match_table = sprd_iommu_of_match, 557 .suppress_bind_attrs = true, 558 }, 559 .probe = sprd_iommu_probe, 560 .remove_new = sprd_iommu_remove, 561 }; 562 module_platform_driver(sprd_iommu_driver); 563 564 MODULE_DESCRIPTION("IOMMU driver for Unisoc SoCs"); 565 MODULE_ALIAS("platform:sprd-iommu"); 566 MODULE_LICENSE("GPL"); 567