1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * IOMMU API for Rockchip
4  *
5  * Module Authors:	Simon Xue <xxm@rock-chips.com>
6  *			Daniel Kurtz <djkurtz@chromium.org>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/compiler.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/dma-iommu.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iommu.h>
19 #include <linux/iopoll.h>
20 #include <linux/list.h>
21 #include <linux/mm.h>
22 #include <linux/init.h>
23 #include <linux/of.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/slab.h>
28 #include <linux/spinlock.h>
29 
30 /** MMU register offsets */
31 #define RK_MMU_DTE_ADDR		0x00	/* Directory table address */
32 #define RK_MMU_STATUS		0x04
33 #define RK_MMU_COMMAND		0x08
34 #define RK_MMU_PAGE_FAULT_ADDR	0x0C	/* IOVA of last page fault */
35 #define RK_MMU_ZAP_ONE_LINE	0x10	/* Shootdown one IOTLB entry */
36 #define RK_MMU_INT_RAWSTAT	0x14	/* IRQ status ignoring mask */
37 #define RK_MMU_INT_CLEAR	0x18	/* Acknowledge and re-arm irq */
38 #define RK_MMU_INT_MASK		0x1C	/* IRQ enable */
39 #define RK_MMU_INT_STATUS	0x20	/* IRQ status after masking */
40 #define RK_MMU_AUTO_GATING	0x24
41 
42 #define DTE_ADDR_DUMMY		0xCAFEBABE
43 
44 #define RK_MMU_POLL_PERIOD_US		100
45 #define RK_MMU_FORCE_RESET_TIMEOUT_US	100000
46 #define RK_MMU_POLL_TIMEOUT_US		1000
47 
48 /* RK_MMU_STATUS fields */
49 #define RK_MMU_STATUS_PAGING_ENABLED       BIT(0)
50 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE    BIT(1)
51 #define RK_MMU_STATUS_STALL_ACTIVE         BIT(2)
52 #define RK_MMU_STATUS_IDLE                 BIT(3)
53 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY  BIT(4)
54 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE  BIT(5)
55 #define RK_MMU_STATUS_STALL_NOT_ACTIVE     BIT(31)
56 
57 /* RK_MMU_COMMAND command values */
58 #define RK_MMU_CMD_ENABLE_PAGING    0  /* Enable memory translation */
59 #define RK_MMU_CMD_DISABLE_PAGING   1  /* Disable memory translation */
60 #define RK_MMU_CMD_ENABLE_STALL     2  /* Stall paging to allow other cmds */
61 #define RK_MMU_CMD_DISABLE_STALL    3  /* Stop stall re-enables paging */
62 #define RK_MMU_CMD_ZAP_CACHE        4  /* Shoot down entire IOTLB */
63 #define RK_MMU_CMD_PAGE_FAULT_DONE  5  /* Clear page fault */
64 #define RK_MMU_CMD_FORCE_RESET      6  /* Reset all registers */
65 
66 /* RK_MMU_INT_* register fields */
67 #define RK_MMU_IRQ_PAGE_FAULT    0x01  /* page fault */
68 #define RK_MMU_IRQ_BUS_ERROR     0x02  /* bus read error */
69 #define RK_MMU_IRQ_MASK          (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
70 
71 #define NUM_DT_ENTRIES 1024
72 #define NUM_PT_ENTRIES 1024
73 
74 #define SPAGE_ORDER 12
75 #define SPAGE_SIZE (1 << SPAGE_ORDER)
76 
77  /*
78   * Support mapping any size that fits in one page table:
79   *   4 KiB to 4 MiB
80   */
81 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
82 
83 struct rk_iommu_domain {
84 	struct list_head iommus;
85 	u32 *dt; /* page directory table */
86 	dma_addr_t dt_dma;
87 	spinlock_t iommus_lock; /* lock for iommus list */
88 	spinlock_t dt_lock; /* lock for modifying page directory table */
89 
90 	struct iommu_domain domain;
91 };
92 
93 /* list of clocks required by IOMMU */
94 static const char * const rk_iommu_clocks[] = {
95 	"aclk", "iface",
96 };
97 
98 struct rk_iommu_ops {
99 	phys_addr_t (*pt_address)(u32 dte);
100 	u32 (*mk_dtentries)(dma_addr_t pt_dma);
101 	u32 (*mk_ptentries)(phys_addr_t page, int prot);
102 	phys_addr_t (*dte_addr_phys)(u32 addr);
103 	u32 (*dma_addr_dte)(dma_addr_t dt_dma);
104 	u64 dma_bit_mask;
105 };
106 
107 struct rk_iommu {
108 	struct device *dev;
109 	void __iomem **bases;
110 	int num_mmu;
111 	int num_irq;
112 	struct clk_bulk_data *clocks;
113 	int num_clocks;
114 	bool reset_disabled;
115 	struct iommu_device iommu;
116 	struct list_head node; /* entry in rk_iommu_domain.iommus */
117 	struct iommu_domain *domain; /* domain to which iommu is attached */
118 	struct iommu_group *group;
119 };
120 
121 struct rk_iommudata {
122 	struct device_link *link; /* runtime PM link from IOMMU to master */
123 	struct rk_iommu *iommu;
124 };
125 
126 static struct device *dma_dev;
127 static const struct rk_iommu_ops *rk_ops;
128 
129 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
130 				  unsigned int count)
131 {
132 	size_t size = count * sizeof(u32); /* count of u32 entry */
133 
134 	dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
135 }
136 
137 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
138 {
139 	return container_of(dom, struct rk_iommu_domain, domain);
140 }
141 
142 /*
143  * The Rockchip rk3288 iommu uses a 2-level page table.
144  * The first level is the "Directory Table" (DT).
145  * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
146  * to a "Page Table".
147  * The second level is the 1024 Page Tables (PT).
148  * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
149  * a 4 KB page of physical memory.
150  *
151  * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
152  * Each iommu device has a MMU_DTE_ADDR register that contains the physical
153  * address of the start of the DT page.
154  *
155  * The structure of the page table is as follows:
156  *
157  *                   DT
158  * MMU_DTE_ADDR -> +-----+
159  *                 |     |
160  *                 +-----+     PT
161  *                 | DTE | -> +-----+
162  *                 +-----+    |     |     Memory
163  *                 |     |    +-----+     Page
164  *                 |     |    | PTE | -> +-----+
165  *                 +-----+    +-----+    |     |
166  *                            |     |    |     |
167  *                            |     |    |     |
168  *                            +-----+    |     |
169  *                                       |     |
170  *                                       |     |
171  *                                       +-----+
172  */
173 
174 /*
175  * Each DTE has a PT address and a valid bit:
176  * +---------------------+-----------+-+
177  * | PT address          | Reserved  |V|
178  * +---------------------+-----------+-+
179  *  31:12 - PT address (PTs always starts on a 4 KB boundary)
180  *  11: 1 - Reserved
181  *      0 - 1 if PT @ PT address is valid
182  */
183 #define RK_DTE_PT_ADDRESS_MASK    0xfffff000
184 #define RK_DTE_PT_VALID           BIT(0)
185 
186 static inline phys_addr_t rk_dte_pt_address(u32 dte)
187 {
188 	return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
189 }
190 
191 /*
192  * In v2:
193  * 31:12 - PT address bit 31:0
194  * 11: 8 - PT address bit 35:32
195  *  7: 4 - PT address bit 39:36
196  *  3: 1 - Reserved
197  *     0 - 1 if PT @ PT address is valid
198  */
199 #define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
200 #define DTE_HI_MASK1	GENMASK(11, 8)
201 #define DTE_HI_MASK2	GENMASK(7, 4)
202 #define DTE_HI_SHIFT1	24 /* shift bit 8 to bit 32 */
203 #define DTE_HI_SHIFT2	32 /* shift bit 4 to bit 36 */
204 #define PAGE_DESC_HI_MASK1	GENMASK_ULL(39, 36)
205 #define PAGE_DESC_HI_MASK2	GENMASK_ULL(35, 32)
206 
207 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
208 {
209 	u64 dte_v2 = dte;
210 
211 	dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
212 		 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
213 		 (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
214 
215 	return (phys_addr_t)dte_v2;
216 }
217 
218 static inline bool rk_dte_is_pt_valid(u32 dte)
219 {
220 	return dte & RK_DTE_PT_VALID;
221 }
222 
223 static inline u32 rk_mk_dte(dma_addr_t pt_dma)
224 {
225 	return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
226 }
227 
228 static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
229 {
230 	pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
231 		 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
232 		 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
233 
234 	return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
235 }
236 
237 /*
238  * Each PTE has a Page address, some flags and a valid bit:
239  * +---------------------+---+-------+-+
240  * | Page address        |Rsv| Flags |V|
241  * +---------------------+---+-------+-+
242  *  31:12 - Page address (Pages always start on a 4 KB boundary)
243  *  11: 9 - Reserved
244  *   8: 1 - Flags
245  *      8 - Read allocate - allocate cache space on read misses
246  *      7 - Read cache - enable cache & prefetch of data
247  *      6 - Write buffer - enable delaying writes on their way to memory
248  *      5 - Write allocate - allocate cache space on write misses
249  *      4 - Write cache - different writes can be merged together
250  *      3 - Override cache attributes
251  *          if 1, bits 4-8 control cache attributes
252  *          if 0, the system bus defaults are used
253  *      2 - Writable
254  *      1 - Readable
255  *      0 - 1 if Page @ Page address is valid
256  */
257 #define RK_PTE_PAGE_ADDRESS_MASK  0xfffff000
258 #define RK_PTE_PAGE_FLAGS_MASK    0x000001fe
259 #define RK_PTE_PAGE_WRITABLE      BIT(2)
260 #define RK_PTE_PAGE_READABLE      BIT(1)
261 #define RK_PTE_PAGE_VALID         BIT(0)
262 
263 static inline bool rk_pte_is_page_valid(u32 pte)
264 {
265 	return pte & RK_PTE_PAGE_VALID;
266 }
267 
268 /* TODO: set cache flags per prot IOMMU_CACHE */
269 static u32 rk_mk_pte(phys_addr_t page, int prot)
270 {
271 	u32 flags = 0;
272 	flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
273 	flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
274 	page &= RK_PTE_PAGE_ADDRESS_MASK;
275 	return page | flags | RK_PTE_PAGE_VALID;
276 }
277 
278 /*
279  * In v2:
280  * 31:12 - Page address bit 31:0
281  *  11:9 - Page address bit 34:32
282  *   8:4 - Page address bit 39:35
283  *     3 - Security
284  *     2 - Readable
285  *     1 - Writable
286  *     0 - 1 if Page @ Page address is valid
287  */
288 #define RK_PTE_PAGE_READABLE_V2      BIT(2)
289 #define RK_PTE_PAGE_WRITABLE_V2      BIT(1)
290 
291 static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
292 {
293 	u32 flags = 0;
294 
295 	flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
296 	flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
297 
298 	return rk_mk_dte_v2(page) | flags;
299 }
300 
301 static u32 rk_mk_pte_invalid(u32 pte)
302 {
303 	return pte & ~RK_PTE_PAGE_VALID;
304 }
305 
306 /*
307  * rk3288 iova (IOMMU Virtual Address) format
308  *  31       22.21       12.11          0
309  * +-----------+-----------+-------------+
310  * | DTE index | PTE index | Page offset |
311  * +-----------+-----------+-------------+
312  *  31:22 - DTE index   - index of DTE in DT
313  *  21:12 - PTE index   - index of PTE in PT @ DTE.pt_address
314  *  11: 0 - Page offset - offset into page @ PTE.page_address
315  */
316 #define RK_IOVA_DTE_MASK    0xffc00000
317 #define RK_IOVA_DTE_SHIFT   22
318 #define RK_IOVA_PTE_MASK    0x003ff000
319 #define RK_IOVA_PTE_SHIFT   12
320 #define RK_IOVA_PAGE_MASK   0x00000fff
321 #define RK_IOVA_PAGE_SHIFT  0
322 
323 static u32 rk_iova_dte_index(dma_addr_t iova)
324 {
325 	return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
326 }
327 
328 static u32 rk_iova_pte_index(dma_addr_t iova)
329 {
330 	return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
331 }
332 
333 static u32 rk_iova_page_offset(dma_addr_t iova)
334 {
335 	return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
336 }
337 
338 static u32 rk_iommu_read(void __iomem *base, u32 offset)
339 {
340 	return readl(base + offset);
341 }
342 
343 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
344 {
345 	writel(value, base + offset);
346 }
347 
348 static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
349 {
350 	int i;
351 
352 	for (i = 0; i < iommu->num_mmu; i++)
353 		writel(command, iommu->bases[i] + RK_MMU_COMMAND);
354 }
355 
356 static void rk_iommu_base_command(void __iomem *base, u32 command)
357 {
358 	writel(command, base + RK_MMU_COMMAND);
359 }
360 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
361 			       size_t size)
362 {
363 	int i;
364 	dma_addr_t iova_end = iova_start + size;
365 	/*
366 	 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
367 	 * entire iotlb rather than iterate over individual iovas.
368 	 */
369 	for (i = 0; i < iommu->num_mmu; i++) {
370 		dma_addr_t iova;
371 
372 		for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
373 			rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
374 	}
375 }
376 
377 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
378 {
379 	bool active = true;
380 	int i;
381 
382 	for (i = 0; i < iommu->num_mmu; i++)
383 		active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
384 					   RK_MMU_STATUS_STALL_ACTIVE);
385 
386 	return active;
387 }
388 
389 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
390 {
391 	bool enable = true;
392 	int i;
393 
394 	for (i = 0; i < iommu->num_mmu; i++)
395 		enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
396 					   RK_MMU_STATUS_PAGING_ENABLED);
397 
398 	return enable;
399 }
400 
401 static bool rk_iommu_is_reset_done(struct rk_iommu *iommu)
402 {
403 	bool done = true;
404 	int i;
405 
406 	for (i = 0; i < iommu->num_mmu; i++)
407 		done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
408 
409 	return done;
410 }
411 
412 static int rk_iommu_enable_stall(struct rk_iommu *iommu)
413 {
414 	int ret, i;
415 	bool val;
416 
417 	if (rk_iommu_is_stall_active(iommu))
418 		return 0;
419 
420 	/* Stall can only be enabled if paging is enabled */
421 	if (!rk_iommu_is_paging_enabled(iommu))
422 		return 0;
423 
424 	rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
425 
426 	ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
427 				 val, RK_MMU_POLL_PERIOD_US,
428 				 RK_MMU_POLL_TIMEOUT_US);
429 	if (ret)
430 		for (i = 0; i < iommu->num_mmu; i++)
431 			dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
432 				rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
433 
434 	return ret;
435 }
436 
437 static int rk_iommu_disable_stall(struct rk_iommu *iommu)
438 {
439 	int ret, i;
440 	bool val;
441 
442 	if (!rk_iommu_is_stall_active(iommu))
443 		return 0;
444 
445 	rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
446 
447 	ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
448 				 !val, RK_MMU_POLL_PERIOD_US,
449 				 RK_MMU_POLL_TIMEOUT_US);
450 	if (ret)
451 		for (i = 0; i < iommu->num_mmu; i++)
452 			dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
453 				rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
454 
455 	return ret;
456 }
457 
458 static int rk_iommu_enable_paging(struct rk_iommu *iommu)
459 {
460 	int ret, i;
461 	bool val;
462 
463 	if (rk_iommu_is_paging_enabled(iommu))
464 		return 0;
465 
466 	rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
467 
468 	ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
469 				 val, RK_MMU_POLL_PERIOD_US,
470 				 RK_MMU_POLL_TIMEOUT_US);
471 	if (ret)
472 		for (i = 0; i < iommu->num_mmu; i++)
473 			dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
474 				rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
475 
476 	return ret;
477 }
478 
479 static int rk_iommu_disable_paging(struct rk_iommu *iommu)
480 {
481 	int ret, i;
482 	bool val;
483 
484 	if (!rk_iommu_is_paging_enabled(iommu))
485 		return 0;
486 
487 	rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
488 
489 	ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
490 				 !val, RK_MMU_POLL_PERIOD_US,
491 				 RK_MMU_POLL_TIMEOUT_US);
492 	if (ret)
493 		for (i = 0; i < iommu->num_mmu; i++)
494 			dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
495 				rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
496 
497 	return ret;
498 }
499 
500 static int rk_iommu_force_reset(struct rk_iommu *iommu)
501 {
502 	int ret, i;
503 	u32 dte_addr;
504 	bool val;
505 
506 	if (iommu->reset_disabled)
507 		return 0;
508 
509 	/*
510 	 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
511 	 * and verifying that upper 5 nybbles are read back.
512 	 */
513 	for (i = 0; i < iommu->num_mmu; i++) {
514 		dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY);
515 		rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr);
516 
517 		if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) {
518 			dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
519 			return -EFAULT;
520 		}
521 	}
522 
523 	rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
524 
525 	ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val,
526 				 val, RK_MMU_FORCE_RESET_TIMEOUT_US,
527 				 RK_MMU_POLL_TIMEOUT_US);
528 	if (ret) {
529 		dev_err(iommu->dev, "FORCE_RESET command timed out\n");
530 		return ret;
531 	}
532 
533 	return 0;
534 }
535 
536 static inline phys_addr_t rk_dte_addr_phys(u32 addr)
537 {
538 	return (phys_addr_t)addr;
539 }
540 
541 static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
542 {
543 	return dt_dma;
544 }
545 
546 #define DT_HI_MASK GENMASK_ULL(39, 32)
547 #define DT_SHIFT   28
548 
549 static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
550 {
551 	return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
552 	       ((addr & DT_HI_MASK) << DT_SHIFT);
553 }
554 
555 static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
556 {
557 	return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
558 	       ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
559 }
560 
561 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
562 {
563 	void __iomem *base = iommu->bases[index];
564 	u32 dte_index, pte_index, page_offset;
565 	u32 mmu_dte_addr;
566 	phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
567 	u32 *dte_addr;
568 	u32 dte;
569 	phys_addr_t pte_addr_phys = 0;
570 	u32 *pte_addr = NULL;
571 	u32 pte = 0;
572 	phys_addr_t page_addr_phys = 0;
573 	u32 page_flags = 0;
574 
575 	dte_index = rk_iova_dte_index(iova);
576 	pte_index = rk_iova_pte_index(iova);
577 	page_offset = rk_iova_page_offset(iova);
578 
579 	mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
580 	mmu_dte_addr_phys = rk_ops->dte_addr_phys(mmu_dte_addr);
581 
582 	dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
583 	dte_addr = phys_to_virt(dte_addr_phys);
584 	dte = *dte_addr;
585 
586 	if (!rk_dte_is_pt_valid(dte))
587 		goto print_it;
588 
589 	pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4);
590 	pte_addr = phys_to_virt(pte_addr_phys);
591 	pte = *pte_addr;
592 
593 	if (!rk_pte_is_page_valid(pte))
594 		goto print_it;
595 
596 	page_addr_phys = rk_ops->pt_address(pte) + page_offset;
597 	page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
598 
599 print_it:
600 	dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
601 		&iova, dte_index, pte_index, page_offset);
602 	dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
603 		&mmu_dte_addr_phys, &dte_addr_phys, dte,
604 		rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
605 		rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
606 }
607 
608 static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
609 {
610 	struct rk_iommu *iommu = dev_id;
611 	u32 status;
612 	u32 int_status;
613 	dma_addr_t iova;
614 	irqreturn_t ret = IRQ_NONE;
615 	int i, err;
616 
617 	err = pm_runtime_get_if_in_use(iommu->dev);
618 	if (!err || WARN_ON_ONCE(err < 0))
619 		return ret;
620 
621 	if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)))
622 		goto out;
623 
624 	for (i = 0; i < iommu->num_mmu; i++) {
625 		int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
626 		if (int_status == 0)
627 			continue;
628 
629 		ret = IRQ_HANDLED;
630 		iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
631 
632 		if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
633 			int flags;
634 
635 			status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
636 			flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
637 					IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
638 
639 			dev_err(iommu->dev, "Page fault at %pad of type %s\n",
640 				&iova,
641 				(flags == IOMMU_FAULT_WRITE) ? "write" : "read");
642 
643 			log_iova(iommu, i, iova);
644 
645 			/*
646 			 * Report page fault to any installed handlers.
647 			 * Ignore the return code, though, since we always zap cache
648 			 * and clear the page fault anyway.
649 			 */
650 			if (iommu->domain)
651 				report_iommu_fault(iommu->domain, iommu->dev, iova,
652 						   flags);
653 			else
654 				dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
655 
656 			rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
657 			rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
658 		}
659 
660 		if (int_status & RK_MMU_IRQ_BUS_ERROR)
661 			dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
662 
663 		if (int_status & ~RK_MMU_IRQ_MASK)
664 			dev_err(iommu->dev, "unexpected int_status: %#08x\n",
665 				int_status);
666 
667 		rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
668 	}
669 
670 	clk_bulk_disable(iommu->num_clocks, iommu->clocks);
671 
672 out:
673 	pm_runtime_put(iommu->dev);
674 	return ret;
675 }
676 
677 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
678 					 dma_addr_t iova)
679 {
680 	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
681 	unsigned long flags;
682 	phys_addr_t pt_phys, phys = 0;
683 	u32 dte, pte;
684 	u32 *page_table;
685 
686 	spin_lock_irqsave(&rk_domain->dt_lock, flags);
687 
688 	dte = rk_domain->dt[rk_iova_dte_index(iova)];
689 	if (!rk_dte_is_pt_valid(dte))
690 		goto out;
691 
692 	pt_phys = rk_ops->pt_address(dte);
693 	page_table = (u32 *)phys_to_virt(pt_phys);
694 	pte = page_table[rk_iova_pte_index(iova)];
695 	if (!rk_pte_is_page_valid(pte))
696 		goto out;
697 
698 	phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova);
699 out:
700 	spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
701 
702 	return phys;
703 }
704 
705 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
706 			      dma_addr_t iova, size_t size)
707 {
708 	struct list_head *pos;
709 	unsigned long flags;
710 
711 	/* shootdown these iova from all iommus using this domain */
712 	spin_lock_irqsave(&rk_domain->iommus_lock, flags);
713 	list_for_each(pos, &rk_domain->iommus) {
714 		struct rk_iommu *iommu;
715 		int ret;
716 
717 		iommu = list_entry(pos, struct rk_iommu, node);
718 
719 		/* Only zap TLBs of IOMMUs that are powered on. */
720 		ret = pm_runtime_get_if_in_use(iommu->dev);
721 		if (WARN_ON_ONCE(ret < 0))
722 			continue;
723 		if (ret) {
724 			WARN_ON(clk_bulk_enable(iommu->num_clocks,
725 						iommu->clocks));
726 			rk_iommu_zap_lines(iommu, iova, size);
727 			clk_bulk_disable(iommu->num_clocks, iommu->clocks);
728 			pm_runtime_put(iommu->dev);
729 		}
730 	}
731 	spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
732 }
733 
734 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
735 					 dma_addr_t iova, size_t size)
736 {
737 	rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
738 	if (size > SPAGE_SIZE)
739 		rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
740 					SPAGE_SIZE);
741 }
742 
743 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
744 				  dma_addr_t iova)
745 {
746 	u32 *page_table, *dte_addr;
747 	u32 dte_index, dte;
748 	phys_addr_t pt_phys;
749 	dma_addr_t pt_dma;
750 
751 	assert_spin_locked(&rk_domain->dt_lock);
752 
753 	dte_index = rk_iova_dte_index(iova);
754 	dte_addr = &rk_domain->dt[dte_index];
755 	dte = *dte_addr;
756 	if (rk_dte_is_pt_valid(dte))
757 		goto done;
758 
759 	page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
760 	if (!page_table)
761 		return ERR_PTR(-ENOMEM);
762 
763 	pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
764 	if (dma_mapping_error(dma_dev, pt_dma)) {
765 		dev_err(dma_dev, "DMA mapping error while allocating page table\n");
766 		free_page((unsigned long)page_table);
767 		return ERR_PTR(-ENOMEM);
768 	}
769 
770 	dte = rk_ops->mk_dtentries(pt_dma);
771 	*dte_addr = dte;
772 
773 	rk_table_flush(rk_domain,
774 		       rk_domain->dt_dma + dte_index * sizeof(u32), 1);
775 done:
776 	pt_phys = rk_ops->pt_address(dte);
777 	return (u32 *)phys_to_virt(pt_phys);
778 }
779 
780 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
781 				  u32 *pte_addr, dma_addr_t pte_dma,
782 				  size_t size)
783 {
784 	unsigned int pte_count;
785 	unsigned int pte_total = size / SPAGE_SIZE;
786 
787 	assert_spin_locked(&rk_domain->dt_lock);
788 
789 	for (pte_count = 0; pte_count < pte_total; pte_count++) {
790 		u32 pte = pte_addr[pte_count];
791 		if (!rk_pte_is_page_valid(pte))
792 			break;
793 
794 		pte_addr[pte_count] = rk_mk_pte_invalid(pte);
795 	}
796 
797 	rk_table_flush(rk_domain, pte_dma, pte_count);
798 
799 	return pte_count * SPAGE_SIZE;
800 }
801 
802 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
803 			     dma_addr_t pte_dma, dma_addr_t iova,
804 			     phys_addr_t paddr, size_t size, int prot)
805 {
806 	unsigned int pte_count;
807 	unsigned int pte_total = size / SPAGE_SIZE;
808 	phys_addr_t page_phys;
809 
810 	assert_spin_locked(&rk_domain->dt_lock);
811 
812 	for (pte_count = 0; pte_count < pte_total; pte_count++) {
813 		u32 pte = pte_addr[pte_count];
814 
815 		if (rk_pte_is_page_valid(pte))
816 			goto unwind;
817 
818 		pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot);
819 
820 		paddr += SPAGE_SIZE;
821 	}
822 
823 	rk_table_flush(rk_domain, pte_dma, pte_total);
824 
825 	/*
826 	 * Zap the first and last iova to evict from iotlb any previously
827 	 * mapped cachelines holding stale values for its dte and pte.
828 	 * We only zap the first and last iova, since only they could have
829 	 * dte or pte shared with an existing mapping.
830 	 */
831 	rk_iommu_zap_iova_first_last(rk_domain, iova, size);
832 
833 	return 0;
834 unwind:
835 	/* Unmap the range of iovas that we just mapped */
836 	rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
837 			    pte_count * SPAGE_SIZE);
838 
839 	iova += pte_count * SPAGE_SIZE;
840 	page_phys = rk_ops->pt_address(pte_addr[pte_count]);
841 	pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
842 	       &iova, &page_phys, &paddr, prot);
843 
844 	return -EADDRINUSE;
845 }
846 
847 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
848 			phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
849 {
850 	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
851 	unsigned long flags;
852 	dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
853 	u32 *page_table, *pte_addr;
854 	u32 dte_index, pte_index;
855 	int ret;
856 
857 	spin_lock_irqsave(&rk_domain->dt_lock, flags);
858 
859 	/*
860 	 * pgsize_bitmap specifies iova sizes that fit in one page table
861 	 * (1024 4-KiB pages = 4 MiB).
862 	 * So, size will always be 4096 <= size <= 4194304.
863 	 * Since iommu_map() guarantees that both iova and size will be
864 	 * aligned, we will always only be mapping from a single dte here.
865 	 */
866 	page_table = rk_dte_get_page_table(rk_domain, iova);
867 	if (IS_ERR(page_table)) {
868 		spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
869 		return PTR_ERR(page_table);
870 	}
871 
872 	dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
873 	pte_index = rk_iova_pte_index(iova);
874 	pte_addr = &page_table[pte_index];
875 
876 	pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32);
877 	ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
878 				paddr, size, prot);
879 
880 	spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
881 
882 	return ret;
883 }
884 
885 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
886 			     size_t size, struct iommu_iotlb_gather *gather)
887 {
888 	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
889 	unsigned long flags;
890 	dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
891 	phys_addr_t pt_phys;
892 	u32 dte;
893 	u32 *pte_addr;
894 	size_t unmap_size;
895 
896 	spin_lock_irqsave(&rk_domain->dt_lock, flags);
897 
898 	/*
899 	 * pgsize_bitmap specifies iova sizes that fit in one page table
900 	 * (1024 4-KiB pages = 4 MiB).
901 	 * So, size will always be 4096 <= size <= 4194304.
902 	 * Since iommu_unmap() guarantees that both iova and size will be
903 	 * aligned, we will always only be unmapping from a single dte here.
904 	 */
905 	dte = rk_domain->dt[rk_iova_dte_index(iova)];
906 	/* Just return 0 if iova is unmapped */
907 	if (!rk_dte_is_pt_valid(dte)) {
908 		spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
909 		return 0;
910 	}
911 
912 	pt_phys = rk_ops->pt_address(dte);
913 	pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
914 	pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
915 	unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
916 
917 	spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
918 
919 	/* Shootdown iotlb entries for iova range that was just unmapped */
920 	rk_iommu_zap_iova(rk_domain, iova, unmap_size);
921 
922 	return unmap_size;
923 }
924 
925 static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
926 {
927 	struct rk_iommudata *data = dev_iommu_priv_get(dev);
928 
929 	return data ? data->iommu : NULL;
930 }
931 
932 /* Must be called with iommu powered on and attached */
933 static void rk_iommu_disable(struct rk_iommu *iommu)
934 {
935 	int i;
936 
937 	/* Ignore error while disabling, just keep going */
938 	WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
939 	rk_iommu_enable_stall(iommu);
940 	rk_iommu_disable_paging(iommu);
941 	for (i = 0; i < iommu->num_mmu; i++) {
942 		rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
943 		rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
944 	}
945 	rk_iommu_disable_stall(iommu);
946 	clk_bulk_disable(iommu->num_clocks, iommu->clocks);
947 }
948 
949 /* Must be called with iommu powered on and attached */
950 static int rk_iommu_enable(struct rk_iommu *iommu)
951 {
952 	struct iommu_domain *domain = iommu->domain;
953 	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
954 	int ret, i;
955 
956 	ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
957 	if (ret)
958 		return ret;
959 
960 	ret = rk_iommu_enable_stall(iommu);
961 	if (ret)
962 		goto out_disable_clocks;
963 
964 	ret = rk_iommu_force_reset(iommu);
965 	if (ret)
966 		goto out_disable_stall;
967 
968 	for (i = 0; i < iommu->num_mmu; i++) {
969 		rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
970 			       rk_ops->dma_addr_dte(rk_domain->dt_dma));
971 		rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
972 		rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
973 	}
974 
975 	ret = rk_iommu_enable_paging(iommu);
976 
977 out_disable_stall:
978 	rk_iommu_disable_stall(iommu);
979 out_disable_clocks:
980 	clk_bulk_disable(iommu->num_clocks, iommu->clocks);
981 	return ret;
982 }
983 
984 static void rk_iommu_detach_device(struct iommu_domain *domain,
985 				   struct device *dev)
986 {
987 	struct rk_iommu *iommu;
988 	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
989 	unsigned long flags;
990 	int ret;
991 
992 	/* Allow 'virtual devices' (eg drm) to detach from domain */
993 	iommu = rk_iommu_from_dev(dev);
994 	if (!iommu)
995 		return;
996 
997 	dev_dbg(dev, "Detaching from iommu domain\n");
998 
999 	/* iommu already detached */
1000 	if (iommu->domain != domain)
1001 		return;
1002 
1003 	iommu->domain = NULL;
1004 
1005 	spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1006 	list_del_init(&iommu->node);
1007 	spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1008 
1009 	ret = pm_runtime_get_if_in_use(iommu->dev);
1010 	WARN_ON_ONCE(ret < 0);
1011 	if (ret > 0) {
1012 		rk_iommu_disable(iommu);
1013 		pm_runtime_put(iommu->dev);
1014 	}
1015 }
1016 
1017 static int rk_iommu_attach_device(struct iommu_domain *domain,
1018 		struct device *dev)
1019 {
1020 	struct rk_iommu *iommu;
1021 	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1022 	unsigned long flags;
1023 	int ret;
1024 
1025 	/*
1026 	 * Allow 'virtual devices' (e.g., drm) to attach to domain.
1027 	 * Such a device does not belong to an iommu group.
1028 	 */
1029 	iommu = rk_iommu_from_dev(dev);
1030 	if (!iommu)
1031 		return 0;
1032 
1033 	dev_dbg(dev, "Attaching to iommu domain\n");
1034 
1035 	/* iommu already attached */
1036 	if (iommu->domain == domain)
1037 		return 0;
1038 
1039 	if (iommu->domain)
1040 		rk_iommu_detach_device(iommu->domain, dev);
1041 
1042 	iommu->domain = domain;
1043 
1044 	spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1045 	list_add_tail(&iommu->node, &rk_domain->iommus);
1046 	spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1047 
1048 	ret = pm_runtime_get_if_in_use(iommu->dev);
1049 	if (!ret || WARN_ON_ONCE(ret < 0))
1050 		return 0;
1051 
1052 	ret = rk_iommu_enable(iommu);
1053 	if (ret)
1054 		rk_iommu_detach_device(iommu->domain, dev);
1055 
1056 	pm_runtime_put(iommu->dev);
1057 
1058 	return ret;
1059 }
1060 
1061 static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
1062 {
1063 	struct rk_iommu_domain *rk_domain;
1064 
1065 	if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
1066 		return NULL;
1067 
1068 	if (!dma_dev)
1069 		return NULL;
1070 
1071 	rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL);
1072 	if (!rk_domain)
1073 		return NULL;
1074 
1075 	if (type == IOMMU_DOMAIN_DMA &&
1076 	    iommu_get_dma_cookie(&rk_domain->domain))
1077 		goto err_free_domain;
1078 
1079 	/*
1080 	 * rk32xx iommus use a 2 level pagetable.
1081 	 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
1082 	 * Allocate one 4 KiB page for each table.
1083 	 */
1084 	rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
1085 	if (!rk_domain->dt)
1086 		goto err_put_cookie;
1087 
1088 	rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt,
1089 					   SPAGE_SIZE, DMA_TO_DEVICE);
1090 	if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) {
1091 		dev_err(dma_dev, "DMA map error for DT\n");
1092 		goto err_free_dt;
1093 	}
1094 
1095 	spin_lock_init(&rk_domain->iommus_lock);
1096 	spin_lock_init(&rk_domain->dt_lock);
1097 	INIT_LIST_HEAD(&rk_domain->iommus);
1098 
1099 	rk_domain->domain.geometry.aperture_start = 0;
1100 	rk_domain->domain.geometry.aperture_end   = DMA_BIT_MASK(32);
1101 	rk_domain->domain.geometry.force_aperture = true;
1102 
1103 	return &rk_domain->domain;
1104 
1105 err_free_dt:
1106 	free_page((unsigned long)rk_domain->dt);
1107 err_put_cookie:
1108 	if (type == IOMMU_DOMAIN_DMA)
1109 		iommu_put_dma_cookie(&rk_domain->domain);
1110 err_free_domain:
1111 	kfree(rk_domain);
1112 
1113 	return NULL;
1114 }
1115 
1116 static void rk_iommu_domain_free(struct iommu_domain *domain)
1117 {
1118 	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1119 	int i;
1120 
1121 	WARN_ON(!list_empty(&rk_domain->iommus));
1122 
1123 	for (i = 0; i < NUM_DT_ENTRIES; i++) {
1124 		u32 dte = rk_domain->dt[i];
1125 		if (rk_dte_is_pt_valid(dte)) {
1126 			phys_addr_t pt_phys = rk_ops->pt_address(dte);
1127 			u32 *page_table = phys_to_virt(pt_phys);
1128 			dma_unmap_single(dma_dev, pt_phys,
1129 					 SPAGE_SIZE, DMA_TO_DEVICE);
1130 			free_page((unsigned long)page_table);
1131 		}
1132 	}
1133 
1134 	dma_unmap_single(dma_dev, rk_domain->dt_dma,
1135 			 SPAGE_SIZE, DMA_TO_DEVICE);
1136 	free_page((unsigned long)rk_domain->dt);
1137 
1138 	if (domain->type == IOMMU_DOMAIN_DMA)
1139 		iommu_put_dma_cookie(&rk_domain->domain);
1140 	kfree(rk_domain);
1141 }
1142 
1143 static struct iommu_device *rk_iommu_probe_device(struct device *dev)
1144 {
1145 	struct rk_iommudata *data;
1146 	struct rk_iommu *iommu;
1147 
1148 	data = dev_iommu_priv_get(dev);
1149 	if (!data)
1150 		return ERR_PTR(-ENODEV);
1151 
1152 	iommu = rk_iommu_from_dev(dev);
1153 
1154 	data->link = device_link_add(dev, iommu->dev,
1155 				     DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1156 
1157 	return &iommu->iommu;
1158 }
1159 
1160 static void rk_iommu_release_device(struct device *dev)
1161 {
1162 	struct rk_iommudata *data = dev_iommu_priv_get(dev);
1163 
1164 	device_link_del(data->link);
1165 }
1166 
1167 static struct iommu_group *rk_iommu_device_group(struct device *dev)
1168 {
1169 	struct rk_iommu *iommu;
1170 
1171 	iommu = rk_iommu_from_dev(dev);
1172 
1173 	return iommu_group_ref_get(iommu->group);
1174 }
1175 
1176 static int rk_iommu_of_xlate(struct device *dev,
1177 			     struct of_phandle_args *args)
1178 {
1179 	struct platform_device *iommu_dev;
1180 	struct rk_iommudata *data;
1181 
1182 	data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL);
1183 	if (!data)
1184 		return -ENOMEM;
1185 
1186 	iommu_dev = of_find_device_by_node(args->np);
1187 
1188 	data->iommu = platform_get_drvdata(iommu_dev);
1189 	dev_iommu_priv_set(dev, data);
1190 
1191 	platform_device_put(iommu_dev);
1192 
1193 	return 0;
1194 }
1195 
1196 static const struct iommu_ops rk_iommu_ops = {
1197 	.domain_alloc = rk_iommu_domain_alloc,
1198 	.domain_free = rk_iommu_domain_free,
1199 	.attach_dev = rk_iommu_attach_device,
1200 	.detach_dev = rk_iommu_detach_device,
1201 	.map = rk_iommu_map,
1202 	.unmap = rk_iommu_unmap,
1203 	.probe_device = rk_iommu_probe_device,
1204 	.release_device = rk_iommu_release_device,
1205 	.iova_to_phys = rk_iommu_iova_to_phys,
1206 	.device_group = rk_iommu_device_group,
1207 	.pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1208 	.of_xlate = rk_iommu_of_xlate,
1209 };
1210 
1211 static int rk_iommu_probe(struct platform_device *pdev)
1212 {
1213 	struct device *dev = &pdev->dev;
1214 	struct rk_iommu *iommu;
1215 	struct resource *res;
1216 	const struct rk_iommu_ops *ops;
1217 	int num_res = pdev->num_resources;
1218 	int err, i;
1219 
1220 	iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1221 	if (!iommu)
1222 		return -ENOMEM;
1223 
1224 	platform_set_drvdata(pdev, iommu);
1225 	iommu->dev = dev;
1226 	iommu->num_mmu = 0;
1227 
1228 	ops = of_device_get_match_data(dev);
1229 	if (!rk_ops)
1230 		rk_ops = ops;
1231 
1232 	/*
1233 	 * That should not happen unless different versions of the
1234 	 * hardware block are embedded the same SoC
1235 	 */
1236 	if (WARN_ON(rk_ops != ops))
1237 		return -EINVAL;
1238 
1239 	iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases),
1240 				    GFP_KERNEL);
1241 	if (!iommu->bases)
1242 		return -ENOMEM;
1243 
1244 	for (i = 0; i < num_res; i++) {
1245 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1246 		if (!res)
1247 			continue;
1248 		iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1249 		if (IS_ERR(iommu->bases[i]))
1250 			continue;
1251 		iommu->num_mmu++;
1252 	}
1253 	if (iommu->num_mmu == 0)
1254 		return PTR_ERR(iommu->bases[0]);
1255 
1256 	iommu->num_irq = platform_irq_count(pdev);
1257 	if (iommu->num_irq < 0)
1258 		return iommu->num_irq;
1259 
1260 	iommu->reset_disabled = device_property_read_bool(dev,
1261 					"rockchip,disable-mmu-reset");
1262 
1263 	iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks);
1264 	iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks,
1265 				     sizeof(*iommu->clocks), GFP_KERNEL);
1266 	if (!iommu->clocks)
1267 		return -ENOMEM;
1268 
1269 	for (i = 0; i < iommu->num_clocks; ++i)
1270 		iommu->clocks[i].id = rk_iommu_clocks[i];
1271 
1272 	/*
1273 	 * iommu clocks should be present for all new devices and devicetrees
1274 	 * but there are older devicetrees without clocks out in the wild.
1275 	 * So clocks as optional for the time being.
1276 	 */
1277 	err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks);
1278 	if (err == -ENOENT)
1279 		iommu->num_clocks = 0;
1280 	else if (err)
1281 		return err;
1282 
1283 	err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
1284 	if (err)
1285 		return err;
1286 
1287 	iommu->group = iommu_group_alloc();
1288 	if (IS_ERR(iommu->group)) {
1289 		err = PTR_ERR(iommu->group);
1290 		goto err_unprepare_clocks;
1291 	}
1292 
1293 	err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
1294 	if (err)
1295 		goto err_put_group;
1296 
1297 	err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev);
1298 	if (err)
1299 		goto err_remove_sysfs;
1300 
1301 	/*
1302 	 * Use the first registered IOMMU device for domain to use with DMA
1303 	 * API, since a domain might not physically correspond to a single
1304 	 * IOMMU device..
1305 	 */
1306 	if (!dma_dev)
1307 		dma_dev = &pdev->dev;
1308 
1309 	bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1310 
1311 	pm_runtime_enable(dev);
1312 
1313 	for (i = 0; i < iommu->num_irq; i++) {
1314 		int irq = platform_get_irq(pdev, i);
1315 
1316 		if (irq < 0)
1317 			return irq;
1318 
1319 		err = devm_request_irq(iommu->dev, irq, rk_iommu_irq,
1320 				       IRQF_SHARED, dev_name(dev), iommu);
1321 		if (err) {
1322 			pm_runtime_disable(dev);
1323 			goto err_remove_sysfs;
1324 		}
1325 	}
1326 
1327 	dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask);
1328 
1329 	return 0;
1330 err_remove_sysfs:
1331 	iommu_device_sysfs_remove(&iommu->iommu);
1332 err_put_group:
1333 	iommu_group_put(iommu->group);
1334 err_unprepare_clocks:
1335 	clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
1336 	return err;
1337 }
1338 
1339 static void rk_iommu_shutdown(struct platform_device *pdev)
1340 {
1341 	struct rk_iommu *iommu = platform_get_drvdata(pdev);
1342 	int i;
1343 
1344 	for (i = 0; i < iommu->num_irq; i++) {
1345 		int irq = platform_get_irq(pdev, i);
1346 
1347 		devm_free_irq(iommu->dev, irq, iommu);
1348 	}
1349 
1350 	pm_runtime_force_suspend(&pdev->dev);
1351 }
1352 
1353 static int __maybe_unused rk_iommu_suspend(struct device *dev)
1354 {
1355 	struct rk_iommu *iommu = dev_get_drvdata(dev);
1356 
1357 	if (!iommu->domain)
1358 		return 0;
1359 
1360 	rk_iommu_disable(iommu);
1361 	return 0;
1362 }
1363 
1364 static int __maybe_unused rk_iommu_resume(struct device *dev)
1365 {
1366 	struct rk_iommu *iommu = dev_get_drvdata(dev);
1367 
1368 	if (!iommu->domain)
1369 		return 0;
1370 
1371 	return rk_iommu_enable(iommu);
1372 }
1373 
1374 static const struct dev_pm_ops rk_iommu_pm_ops = {
1375 	SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL)
1376 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1377 				pm_runtime_force_resume)
1378 };
1379 
1380 static struct rk_iommu_ops iommu_data_ops_v1 = {
1381 	.pt_address = &rk_dte_pt_address,
1382 	.mk_dtentries = &rk_mk_dte,
1383 	.mk_ptentries = &rk_mk_pte,
1384 	.dte_addr_phys = &rk_dte_addr_phys,
1385 	.dma_addr_dte = &rk_dma_addr_dte,
1386 	.dma_bit_mask = DMA_BIT_MASK(32),
1387 };
1388 
1389 static struct rk_iommu_ops iommu_data_ops_v2 = {
1390 	.pt_address = &rk_dte_pt_address_v2,
1391 	.mk_dtentries = &rk_mk_dte_v2,
1392 	.mk_ptentries = &rk_mk_pte_v2,
1393 	.dte_addr_phys = &rk_dte_addr_phys_v2,
1394 	.dma_addr_dte = &rk_dma_addr_dte_v2,
1395 	.dma_bit_mask = DMA_BIT_MASK(40),
1396 };
1397 
1398 static const struct of_device_id rk_iommu_dt_ids[] = {
1399 	{	.compatible = "rockchip,iommu",
1400 		.data = &iommu_data_ops_v1,
1401 	},
1402 	{	.compatible = "rockchip,rk3568-iommu",
1403 		.data = &iommu_data_ops_v2,
1404 	},
1405 	{ /* sentinel */ }
1406 };
1407 
1408 static struct platform_driver rk_iommu_driver = {
1409 	.probe = rk_iommu_probe,
1410 	.shutdown = rk_iommu_shutdown,
1411 	.driver = {
1412 		   .name = "rk_iommu",
1413 		   .of_match_table = rk_iommu_dt_ids,
1414 		   .pm = &rk_iommu_pm_ops,
1415 		   .suppress_bind_attrs = true,
1416 	},
1417 };
1418 
1419 static int __init rk_iommu_init(void)
1420 {
1421 	return platform_driver_register(&rk_iommu_driver);
1422 }
1423 subsys_initcall(rk_iommu_init);
1424