1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IOMMU API for Rockchip 4 * 5 * Module Authors: Simon Xue <xxm@rock-chips.com> 6 * Daniel Kurtz <djkurtz@chromium.org> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/errno.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iommu.h> 18 #include <linux/iopoll.h> 19 #include <linux/list.h> 20 #include <linux/mm.h> 21 #include <linux/init.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 29 /** MMU register offsets */ 30 #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */ 31 #define RK_MMU_STATUS 0x04 32 #define RK_MMU_COMMAND 0x08 33 #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */ 34 #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */ 35 #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */ 36 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */ 37 #define RK_MMU_INT_MASK 0x1C /* IRQ enable */ 38 #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */ 39 #define RK_MMU_AUTO_GATING 0x24 40 41 #define DTE_ADDR_DUMMY 0xCAFEBABE 42 43 #define RK_MMU_POLL_PERIOD_US 100 44 #define RK_MMU_FORCE_RESET_TIMEOUT_US 100000 45 #define RK_MMU_POLL_TIMEOUT_US 1000 46 47 /* RK_MMU_STATUS fields */ 48 #define RK_MMU_STATUS_PAGING_ENABLED BIT(0) 49 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) 50 #define RK_MMU_STATUS_STALL_ACTIVE BIT(2) 51 #define RK_MMU_STATUS_IDLE BIT(3) 52 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) 53 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) 54 #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) 55 56 /* RK_MMU_COMMAND command values */ 57 #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */ 58 #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */ 59 #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */ 60 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */ 61 #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */ 62 #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */ 63 #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */ 64 65 /* RK_MMU_INT_* register fields */ 66 #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */ 67 #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */ 68 #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR) 69 70 #define NUM_DT_ENTRIES 1024 71 #define NUM_PT_ENTRIES 1024 72 73 #define SPAGE_ORDER 12 74 #define SPAGE_SIZE (1 << SPAGE_ORDER) 75 76 /* 77 * Support mapping any size that fits in one page table: 78 * 4 KiB to 4 MiB 79 */ 80 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000 81 82 struct rk_iommu_domain { 83 struct list_head iommus; 84 u32 *dt; /* page directory table */ 85 dma_addr_t dt_dma; 86 spinlock_t iommus_lock; /* lock for iommus list */ 87 spinlock_t dt_lock; /* lock for modifying page directory table */ 88 89 struct iommu_domain domain; 90 }; 91 92 /* list of clocks required by IOMMU */ 93 static const char * const rk_iommu_clocks[] = { 94 "aclk", "iface", 95 }; 96 97 struct rk_iommu_ops { 98 phys_addr_t (*pt_address)(u32 dte); 99 u32 (*mk_dtentries)(dma_addr_t pt_dma); 100 u32 (*mk_ptentries)(phys_addr_t page, int prot); 101 phys_addr_t (*dte_addr_phys)(u32 addr); 102 u32 (*dma_addr_dte)(dma_addr_t dt_dma); 103 u64 dma_bit_mask; 104 }; 105 106 struct rk_iommu { 107 struct device *dev; 108 void __iomem **bases; 109 int num_mmu; 110 int num_irq; 111 struct clk_bulk_data *clocks; 112 int num_clocks; 113 bool reset_disabled; 114 struct iommu_device iommu; 115 struct list_head node; /* entry in rk_iommu_domain.iommus */ 116 struct iommu_domain *domain; /* domain to which iommu is attached */ 117 struct iommu_group *group; 118 }; 119 120 struct rk_iommudata { 121 struct device_link *link; /* runtime PM link from IOMMU to master */ 122 struct rk_iommu *iommu; 123 }; 124 125 static struct device *dma_dev; 126 static const struct rk_iommu_ops *rk_ops; 127 static struct iommu_domain rk_identity_domain; 128 129 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, 130 unsigned int count) 131 { 132 size_t size = count * sizeof(u32); /* count of u32 entry */ 133 134 dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE); 135 } 136 137 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom) 138 { 139 return container_of(dom, struct rk_iommu_domain, domain); 140 } 141 142 /* 143 * The Rockchip rk3288 iommu uses a 2-level page table. 144 * The first level is the "Directory Table" (DT). 145 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing 146 * to a "Page Table". 147 * The second level is the 1024 Page Tables (PT). 148 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to 149 * a 4 KB page of physical memory. 150 * 151 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries). 152 * Each iommu device has a MMU_DTE_ADDR register that contains the physical 153 * address of the start of the DT page. 154 * 155 * The structure of the page table is as follows: 156 * 157 * DT 158 * MMU_DTE_ADDR -> +-----+ 159 * | | 160 * +-----+ PT 161 * | DTE | -> +-----+ 162 * +-----+ | | Memory 163 * | | +-----+ Page 164 * | | | PTE | -> +-----+ 165 * +-----+ +-----+ | | 166 * | | | | 167 * | | | | 168 * +-----+ | | 169 * | | 170 * | | 171 * +-----+ 172 */ 173 174 /* 175 * Each DTE has a PT address and a valid bit: 176 * +---------------------+-----------+-+ 177 * | PT address | Reserved |V| 178 * +---------------------+-----------+-+ 179 * 31:12 - PT address (PTs always starts on a 4 KB boundary) 180 * 11: 1 - Reserved 181 * 0 - 1 if PT @ PT address is valid 182 */ 183 #define RK_DTE_PT_ADDRESS_MASK 0xfffff000 184 #define RK_DTE_PT_VALID BIT(0) 185 186 static inline phys_addr_t rk_dte_pt_address(u32 dte) 187 { 188 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; 189 } 190 191 /* 192 * In v2: 193 * 31:12 - PT address bit 31:0 194 * 11: 8 - PT address bit 35:32 195 * 7: 4 - PT address bit 39:36 196 * 3: 1 - Reserved 197 * 0 - 1 if PT @ PT address is valid 198 */ 199 #define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4) 200 #define DTE_HI_MASK1 GENMASK(11, 8) 201 #define DTE_HI_MASK2 GENMASK(7, 4) 202 #define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */ 203 #define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */ 204 #define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32) 205 #define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36) 206 207 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) 208 { 209 u64 dte_v2 = dte; 210 211 dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) | 212 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) | 213 (dte_v2 & RK_DTE_PT_ADDRESS_MASK); 214 215 return (phys_addr_t)dte_v2; 216 } 217 218 static inline bool rk_dte_is_pt_valid(u32 dte) 219 { 220 return dte & RK_DTE_PT_VALID; 221 } 222 223 static inline u32 rk_mk_dte(dma_addr_t pt_dma) 224 { 225 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID; 226 } 227 228 static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma) 229 { 230 pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) | 231 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) | 232 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2; 233 234 return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID; 235 } 236 237 /* 238 * Each PTE has a Page address, some flags and a valid bit: 239 * +---------------------+---+-------+-+ 240 * | Page address |Rsv| Flags |V| 241 * +---------------------+---+-------+-+ 242 * 31:12 - Page address (Pages always start on a 4 KB boundary) 243 * 11: 9 - Reserved 244 * 8: 1 - Flags 245 * 8 - Read allocate - allocate cache space on read misses 246 * 7 - Read cache - enable cache & prefetch of data 247 * 6 - Write buffer - enable delaying writes on their way to memory 248 * 5 - Write allocate - allocate cache space on write misses 249 * 4 - Write cache - different writes can be merged together 250 * 3 - Override cache attributes 251 * if 1, bits 4-8 control cache attributes 252 * if 0, the system bus defaults are used 253 * 2 - Writable 254 * 1 - Readable 255 * 0 - 1 if Page @ Page address is valid 256 */ 257 #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000 258 #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe 259 #define RK_PTE_PAGE_WRITABLE BIT(2) 260 #define RK_PTE_PAGE_READABLE BIT(1) 261 #define RK_PTE_PAGE_VALID BIT(0) 262 263 static inline bool rk_pte_is_page_valid(u32 pte) 264 { 265 return pte & RK_PTE_PAGE_VALID; 266 } 267 268 /* TODO: set cache flags per prot IOMMU_CACHE */ 269 static u32 rk_mk_pte(phys_addr_t page, int prot) 270 { 271 u32 flags = 0; 272 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 273 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 274 page &= RK_PTE_PAGE_ADDRESS_MASK; 275 return page | flags | RK_PTE_PAGE_VALID; 276 } 277 278 /* 279 * In v2: 280 * 31:12 - Page address bit 31:0 281 * 11:9 - Page address bit 34:32 282 * 8:4 - Page address bit 39:35 283 * 3 - Security 284 * 2 - Writable 285 * 1 - Readable 286 * 0 - 1 if Page @ Page address is valid 287 */ 288 289 static u32 rk_mk_pte_v2(phys_addr_t page, int prot) 290 { 291 u32 flags = 0; 292 293 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 294 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 295 296 return rk_mk_dte_v2(page) | flags; 297 } 298 299 static u32 rk_mk_pte_invalid(u32 pte) 300 { 301 return pte & ~RK_PTE_PAGE_VALID; 302 } 303 304 /* 305 * rk3288 iova (IOMMU Virtual Address) format 306 * 31 22.21 12.11 0 307 * +-----------+-----------+-------------+ 308 * | DTE index | PTE index | Page offset | 309 * +-----------+-----------+-------------+ 310 * 31:22 - DTE index - index of DTE in DT 311 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address 312 * 11: 0 - Page offset - offset into page @ PTE.page_address 313 */ 314 #define RK_IOVA_DTE_MASK 0xffc00000 315 #define RK_IOVA_DTE_SHIFT 22 316 #define RK_IOVA_PTE_MASK 0x003ff000 317 #define RK_IOVA_PTE_SHIFT 12 318 #define RK_IOVA_PAGE_MASK 0x00000fff 319 #define RK_IOVA_PAGE_SHIFT 0 320 321 static u32 rk_iova_dte_index(dma_addr_t iova) 322 { 323 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT; 324 } 325 326 static u32 rk_iova_pte_index(dma_addr_t iova) 327 { 328 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT; 329 } 330 331 static u32 rk_iova_page_offset(dma_addr_t iova) 332 { 333 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT; 334 } 335 336 static u32 rk_iommu_read(void __iomem *base, u32 offset) 337 { 338 return readl(base + offset); 339 } 340 341 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value) 342 { 343 writel(value, base + offset); 344 } 345 346 static void rk_iommu_command(struct rk_iommu *iommu, u32 command) 347 { 348 int i; 349 350 for (i = 0; i < iommu->num_mmu; i++) 351 writel(command, iommu->bases[i] + RK_MMU_COMMAND); 352 } 353 354 static void rk_iommu_base_command(void __iomem *base, u32 command) 355 { 356 writel(command, base + RK_MMU_COMMAND); 357 } 358 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start, 359 size_t size) 360 { 361 int i; 362 dma_addr_t iova_end = iova_start + size; 363 /* 364 * TODO(djkurtz): Figure out when it is more efficient to shootdown the 365 * entire iotlb rather than iterate over individual iovas. 366 */ 367 for (i = 0; i < iommu->num_mmu; i++) { 368 dma_addr_t iova; 369 370 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE) 371 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); 372 } 373 } 374 375 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu) 376 { 377 bool active = true; 378 int i; 379 380 for (i = 0; i < iommu->num_mmu; i++) 381 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 382 RK_MMU_STATUS_STALL_ACTIVE); 383 384 return active; 385 } 386 387 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu) 388 { 389 bool enable = true; 390 int i; 391 392 for (i = 0; i < iommu->num_mmu; i++) 393 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 394 RK_MMU_STATUS_PAGING_ENABLED); 395 396 return enable; 397 } 398 399 static bool rk_iommu_is_reset_done(struct rk_iommu *iommu) 400 { 401 bool done = true; 402 int i; 403 404 for (i = 0; i < iommu->num_mmu; i++) 405 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; 406 407 return done; 408 } 409 410 static int rk_iommu_enable_stall(struct rk_iommu *iommu) 411 { 412 int ret, i; 413 bool val; 414 415 if (rk_iommu_is_stall_active(iommu)) 416 return 0; 417 418 /* Stall can only be enabled if paging is enabled */ 419 if (!rk_iommu_is_paging_enabled(iommu)) 420 return 0; 421 422 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL); 423 424 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 425 val, RK_MMU_POLL_PERIOD_US, 426 RK_MMU_POLL_TIMEOUT_US); 427 if (ret) 428 for (i = 0; i < iommu->num_mmu; i++) 429 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n", 430 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 431 432 return ret; 433 } 434 435 static int rk_iommu_disable_stall(struct rk_iommu *iommu) 436 { 437 int ret, i; 438 bool val; 439 440 if (!rk_iommu_is_stall_active(iommu)) 441 return 0; 442 443 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL); 444 445 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 446 !val, RK_MMU_POLL_PERIOD_US, 447 RK_MMU_POLL_TIMEOUT_US); 448 if (ret) 449 for (i = 0; i < iommu->num_mmu; i++) 450 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n", 451 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 452 453 return ret; 454 } 455 456 static int rk_iommu_enable_paging(struct rk_iommu *iommu) 457 { 458 int ret, i; 459 bool val; 460 461 if (rk_iommu_is_paging_enabled(iommu)) 462 return 0; 463 464 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING); 465 466 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 467 val, RK_MMU_POLL_PERIOD_US, 468 RK_MMU_POLL_TIMEOUT_US); 469 if (ret) 470 for (i = 0; i < iommu->num_mmu; i++) 471 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n", 472 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 473 474 return ret; 475 } 476 477 static int rk_iommu_disable_paging(struct rk_iommu *iommu) 478 { 479 int ret, i; 480 bool val; 481 482 if (!rk_iommu_is_paging_enabled(iommu)) 483 return 0; 484 485 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING); 486 487 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 488 !val, RK_MMU_POLL_PERIOD_US, 489 RK_MMU_POLL_TIMEOUT_US); 490 if (ret) 491 for (i = 0; i < iommu->num_mmu; i++) 492 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n", 493 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 494 495 return ret; 496 } 497 498 static int rk_iommu_force_reset(struct rk_iommu *iommu) 499 { 500 int ret, i; 501 u32 dte_addr; 502 bool val; 503 504 if (iommu->reset_disabled) 505 return 0; 506 507 /* 508 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY 509 * and verifying that upper 5 nybbles are read back. 510 */ 511 for (i = 0; i < iommu->num_mmu; i++) { 512 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY); 513 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr); 514 515 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) { 516 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n"); 517 return -EFAULT; 518 } 519 } 520 521 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET); 522 523 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val, 524 val, RK_MMU_FORCE_RESET_TIMEOUT_US, 525 RK_MMU_POLL_TIMEOUT_US); 526 if (ret) { 527 dev_err(iommu->dev, "FORCE_RESET command timed out\n"); 528 return ret; 529 } 530 531 return 0; 532 } 533 534 static inline phys_addr_t rk_dte_addr_phys(u32 addr) 535 { 536 return (phys_addr_t)addr; 537 } 538 539 static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma) 540 { 541 return dt_dma; 542 } 543 544 #define DT_HI_MASK GENMASK_ULL(39, 32) 545 #define DTE_BASE_HI_MASK GENMASK(11, 4) 546 #define DT_SHIFT 28 547 548 static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr) 549 { 550 u64 addr64 = addr; 551 return (phys_addr_t)(addr64 & RK_DTE_PT_ADDRESS_MASK) | 552 ((addr64 & DTE_BASE_HI_MASK) << DT_SHIFT); 553 } 554 555 static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma) 556 { 557 return (dt_dma & RK_DTE_PT_ADDRESS_MASK) | 558 ((dt_dma & DT_HI_MASK) >> DT_SHIFT); 559 } 560 561 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova) 562 { 563 void __iomem *base = iommu->bases[index]; 564 u32 dte_index, pte_index, page_offset; 565 u32 mmu_dte_addr; 566 phys_addr_t mmu_dte_addr_phys, dte_addr_phys; 567 u32 *dte_addr; 568 u32 dte; 569 phys_addr_t pte_addr_phys = 0; 570 u32 *pte_addr = NULL; 571 u32 pte = 0; 572 phys_addr_t page_addr_phys = 0; 573 u32 page_flags = 0; 574 575 dte_index = rk_iova_dte_index(iova); 576 pte_index = rk_iova_pte_index(iova); 577 page_offset = rk_iova_page_offset(iova); 578 579 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR); 580 mmu_dte_addr_phys = rk_ops->dte_addr_phys(mmu_dte_addr); 581 582 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index); 583 dte_addr = phys_to_virt(dte_addr_phys); 584 dte = *dte_addr; 585 586 if (!rk_dte_is_pt_valid(dte)) 587 goto print_it; 588 589 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4); 590 pte_addr = phys_to_virt(pte_addr_phys); 591 pte = *pte_addr; 592 593 if (!rk_pte_is_page_valid(pte)) 594 goto print_it; 595 596 page_addr_phys = rk_ops->pt_address(pte) + page_offset; 597 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK; 598 599 print_it: 600 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n", 601 &iova, dte_index, pte_index, page_offset); 602 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n", 603 &mmu_dte_addr_phys, &dte_addr_phys, dte, 604 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte, 605 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags); 606 } 607 608 static irqreturn_t rk_iommu_irq(int irq, void *dev_id) 609 { 610 struct rk_iommu *iommu = dev_id; 611 u32 status; 612 u32 int_status; 613 dma_addr_t iova; 614 irqreturn_t ret = IRQ_NONE; 615 int i, err; 616 617 err = pm_runtime_get_if_in_use(iommu->dev); 618 if (!err || WARN_ON_ONCE(err < 0)) 619 return ret; 620 621 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) 622 goto out; 623 624 for (i = 0; i < iommu->num_mmu; i++) { 625 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); 626 if (int_status == 0) 627 continue; 628 629 ret = IRQ_HANDLED; 630 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); 631 632 if (int_status & RK_MMU_IRQ_PAGE_FAULT) { 633 int flags; 634 635 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); 636 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ? 637 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; 638 639 dev_err(iommu->dev, "Page fault at %pad of type %s\n", 640 &iova, 641 (flags == IOMMU_FAULT_WRITE) ? "write" : "read"); 642 643 log_iova(iommu, i, iova); 644 645 /* 646 * Report page fault to any installed handlers. 647 * Ignore the return code, though, since we always zap cache 648 * and clear the page fault anyway. 649 */ 650 if (iommu->domain != &rk_identity_domain) 651 report_iommu_fault(iommu->domain, iommu->dev, iova, 652 flags); 653 else 654 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n"); 655 656 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 657 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); 658 } 659 660 if (int_status & RK_MMU_IRQ_BUS_ERROR) 661 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova); 662 663 if (int_status & ~RK_MMU_IRQ_MASK) 664 dev_err(iommu->dev, "unexpected int_status: %#08x\n", 665 int_status); 666 667 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status); 668 } 669 670 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 671 672 out: 673 pm_runtime_put(iommu->dev); 674 return ret; 675 } 676 677 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain, 678 dma_addr_t iova) 679 { 680 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 681 unsigned long flags; 682 phys_addr_t pt_phys, phys = 0; 683 u32 dte, pte; 684 u32 *page_table; 685 686 spin_lock_irqsave(&rk_domain->dt_lock, flags); 687 688 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 689 if (!rk_dte_is_pt_valid(dte)) 690 goto out; 691 692 pt_phys = rk_ops->pt_address(dte); 693 page_table = (u32 *)phys_to_virt(pt_phys); 694 pte = page_table[rk_iova_pte_index(iova)]; 695 if (!rk_pte_is_page_valid(pte)) 696 goto out; 697 698 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova); 699 out: 700 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 701 702 return phys; 703 } 704 705 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain, 706 dma_addr_t iova, size_t size) 707 { 708 struct list_head *pos; 709 unsigned long flags; 710 711 /* shootdown these iova from all iommus using this domain */ 712 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 713 list_for_each(pos, &rk_domain->iommus) { 714 struct rk_iommu *iommu; 715 int ret; 716 717 iommu = list_entry(pos, struct rk_iommu, node); 718 719 /* Only zap TLBs of IOMMUs that are powered on. */ 720 ret = pm_runtime_get_if_in_use(iommu->dev); 721 if (WARN_ON_ONCE(ret < 0)) 722 continue; 723 if (ret) { 724 WARN_ON(clk_bulk_enable(iommu->num_clocks, 725 iommu->clocks)); 726 rk_iommu_zap_lines(iommu, iova, size); 727 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 728 pm_runtime_put(iommu->dev); 729 } 730 } 731 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 732 } 733 734 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain, 735 dma_addr_t iova, size_t size) 736 { 737 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE); 738 if (size > SPAGE_SIZE) 739 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE, 740 SPAGE_SIZE); 741 } 742 743 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain, 744 dma_addr_t iova) 745 { 746 u32 *page_table, *dte_addr; 747 u32 dte_index, dte; 748 phys_addr_t pt_phys; 749 dma_addr_t pt_dma; 750 751 assert_spin_locked(&rk_domain->dt_lock); 752 753 dte_index = rk_iova_dte_index(iova); 754 dte_addr = &rk_domain->dt[dte_index]; 755 dte = *dte_addr; 756 if (rk_dte_is_pt_valid(dte)) 757 goto done; 758 759 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32); 760 if (!page_table) 761 return ERR_PTR(-ENOMEM); 762 763 pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE); 764 if (dma_mapping_error(dma_dev, pt_dma)) { 765 dev_err(dma_dev, "DMA mapping error while allocating page table\n"); 766 free_page((unsigned long)page_table); 767 return ERR_PTR(-ENOMEM); 768 } 769 770 dte = rk_ops->mk_dtentries(pt_dma); 771 *dte_addr = dte; 772 773 rk_table_flush(rk_domain, 774 rk_domain->dt_dma + dte_index * sizeof(u32), 1); 775 done: 776 pt_phys = rk_ops->pt_address(dte); 777 return (u32 *)phys_to_virt(pt_phys); 778 } 779 780 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain, 781 u32 *pte_addr, dma_addr_t pte_dma, 782 size_t size) 783 { 784 unsigned int pte_count; 785 unsigned int pte_total = size / SPAGE_SIZE; 786 787 assert_spin_locked(&rk_domain->dt_lock); 788 789 for (pte_count = 0; pte_count < pte_total; pte_count++) { 790 u32 pte = pte_addr[pte_count]; 791 if (!rk_pte_is_page_valid(pte)) 792 break; 793 794 pte_addr[pte_count] = rk_mk_pte_invalid(pte); 795 } 796 797 rk_table_flush(rk_domain, pte_dma, pte_count); 798 799 return pte_count * SPAGE_SIZE; 800 } 801 802 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr, 803 dma_addr_t pte_dma, dma_addr_t iova, 804 phys_addr_t paddr, size_t size, int prot) 805 { 806 unsigned int pte_count; 807 unsigned int pte_total = size / SPAGE_SIZE; 808 phys_addr_t page_phys; 809 810 assert_spin_locked(&rk_domain->dt_lock); 811 812 for (pte_count = 0; pte_count < pte_total; pte_count++) { 813 u32 pte = pte_addr[pte_count]; 814 815 if (rk_pte_is_page_valid(pte)) 816 goto unwind; 817 818 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot); 819 820 paddr += SPAGE_SIZE; 821 } 822 823 rk_table_flush(rk_domain, pte_dma, pte_total); 824 825 /* 826 * Zap the first and last iova to evict from iotlb any previously 827 * mapped cachelines holding stale values for its dte and pte. 828 * We only zap the first and last iova, since only they could have 829 * dte or pte shared with an existing mapping. 830 */ 831 rk_iommu_zap_iova_first_last(rk_domain, iova, size); 832 833 return 0; 834 unwind: 835 /* Unmap the range of iovas that we just mapped */ 836 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, 837 pte_count * SPAGE_SIZE); 838 839 iova += pte_count * SPAGE_SIZE; 840 page_phys = rk_ops->pt_address(pte_addr[pte_count]); 841 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n", 842 &iova, &page_phys, &paddr, prot); 843 844 return -EADDRINUSE; 845 } 846 847 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova, 848 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 849 { 850 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 851 unsigned long flags; 852 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 853 u32 *page_table, *pte_addr; 854 u32 dte_index, pte_index; 855 int ret; 856 857 spin_lock_irqsave(&rk_domain->dt_lock, flags); 858 859 /* 860 * pgsize_bitmap specifies iova sizes that fit in one page table 861 * (1024 4-KiB pages = 4 MiB). 862 * So, size will always be 4096 <= size <= 4194304. 863 * Since iommu_map() guarantees that both iova and size will be 864 * aligned, we will always only be mapping from a single dte here. 865 */ 866 page_table = rk_dte_get_page_table(rk_domain, iova); 867 if (IS_ERR(page_table)) { 868 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 869 return PTR_ERR(page_table); 870 } 871 872 dte_index = rk_domain->dt[rk_iova_dte_index(iova)]; 873 pte_index = rk_iova_pte_index(iova); 874 pte_addr = &page_table[pte_index]; 875 876 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32); 877 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova, 878 paddr, size, prot); 879 880 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 881 882 return ret; 883 } 884 885 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, 886 size_t size, struct iommu_iotlb_gather *gather) 887 { 888 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 889 unsigned long flags; 890 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 891 phys_addr_t pt_phys; 892 u32 dte; 893 u32 *pte_addr; 894 size_t unmap_size; 895 896 spin_lock_irqsave(&rk_domain->dt_lock, flags); 897 898 /* 899 * pgsize_bitmap specifies iova sizes that fit in one page table 900 * (1024 4-KiB pages = 4 MiB). 901 * So, size will always be 4096 <= size <= 4194304. 902 * Since iommu_unmap() guarantees that both iova and size will be 903 * aligned, we will always only be unmapping from a single dte here. 904 */ 905 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 906 /* Just return 0 if iova is unmapped */ 907 if (!rk_dte_is_pt_valid(dte)) { 908 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 909 return 0; 910 } 911 912 pt_phys = rk_ops->pt_address(dte); 913 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova); 914 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32); 915 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size); 916 917 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 918 919 /* Shootdown iotlb entries for iova range that was just unmapped */ 920 rk_iommu_zap_iova(rk_domain, iova, unmap_size); 921 922 return unmap_size; 923 } 924 925 static struct rk_iommu *rk_iommu_from_dev(struct device *dev) 926 { 927 struct rk_iommudata *data = dev_iommu_priv_get(dev); 928 929 return data ? data->iommu : NULL; 930 } 931 932 /* Must be called with iommu powered on and attached */ 933 static void rk_iommu_disable(struct rk_iommu *iommu) 934 { 935 int i; 936 937 /* Ignore error while disabling, just keep going */ 938 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)); 939 rk_iommu_enable_stall(iommu); 940 rk_iommu_disable_paging(iommu); 941 for (i = 0; i < iommu->num_mmu; i++) { 942 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0); 943 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0); 944 } 945 rk_iommu_disable_stall(iommu); 946 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 947 } 948 949 /* Must be called with iommu powered on and attached */ 950 static int rk_iommu_enable(struct rk_iommu *iommu) 951 { 952 struct iommu_domain *domain = iommu->domain; 953 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 954 int ret, i; 955 956 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); 957 if (ret) 958 return ret; 959 960 ret = rk_iommu_enable_stall(iommu); 961 if (ret) 962 goto out_disable_clocks; 963 964 ret = rk_iommu_force_reset(iommu); 965 if (ret) 966 goto out_disable_stall; 967 968 for (i = 0; i < iommu->num_mmu; i++) { 969 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 970 rk_ops->dma_addr_dte(rk_domain->dt_dma)); 971 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 972 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); 973 } 974 975 ret = rk_iommu_enable_paging(iommu); 976 977 out_disable_stall: 978 rk_iommu_disable_stall(iommu); 979 out_disable_clocks: 980 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 981 return ret; 982 } 983 984 static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, 985 struct device *dev) 986 { 987 struct rk_iommu *iommu; 988 struct rk_iommu_domain *rk_domain; 989 unsigned long flags; 990 int ret; 991 992 /* Allow 'virtual devices' (eg drm) to detach from domain */ 993 iommu = rk_iommu_from_dev(dev); 994 if (!iommu) 995 return -ENODEV; 996 997 rk_domain = to_rk_domain(iommu->domain); 998 999 dev_dbg(dev, "Detaching from iommu domain\n"); 1000 1001 if (iommu->domain == identity_domain) 1002 return 0; 1003 1004 iommu->domain = identity_domain; 1005 1006 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 1007 list_del_init(&iommu->node); 1008 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 1009 1010 ret = pm_runtime_get_if_in_use(iommu->dev); 1011 WARN_ON_ONCE(ret < 0); 1012 if (ret > 0) { 1013 rk_iommu_disable(iommu); 1014 pm_runtime_put(iommu->dev); 1015 } 1016 1017 return 0; 1018 } 1019 1020 static void rk_iommu_identity_free(struct iommu_domain *domain) 1021 { 1022 } 1023 1024 static struct iommu_domain_ops rk_identity_ops = { 1025 .attach_dev = rk_iommu_identity_attach, 1026 .free = rk_iommu_identity_free, 1027 }; 1028 1029 static struct iommu_domain rk_identity_domain = { 1030 .type = IOMMU_DOMAIN_IDENTITY, 1031 .ops = &rk_identity_ops, 1032 }; 1033 1034 #ifdef CONFIG_ARM 1035 static void rk_iommu_set_platform_dma(struct device *dev) 1036 { 1037 WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev)); 1038 } 1039 #endif 1040 1041 static int rk_iommu_attach_device(struct iommu_domain *domain, 1042 struct device *dev) 1043 { 1044 struct rk_iommu *iommu; 1045 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1046 unsigned long flags; 1047 int ret; 1048 1049 /* 1050 * Allow 'virtual devices' (e.g., drm) to attach to domain. 1051 * Such a device does not belong to an iommu group. 1052 */ 1053 iommu = rk_iommu_from_dev(dev); 1054 if (!iommu) 1055 return 0; 1056 1057 dev_dbg(dev, "Attaching to iommu domain\n"); 1058 1059 /* iommu already attached */ 1060 if (iommu->domain == domain) 1061 return 0; 1062 1063 ret = rk_iommu_identity_attach(&rk_identity_domain, dev); 1064 if (ret) 1065 return ret; 1066 1067 iommu->domain = domain; 1068 1069 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 1070 list_add_tail(&iommu->node, &rk_domain->iommus); 1071 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 1072 1073 ret = pm_runtime_get_if_in_use(iommu->dev); 1074 if (!ret || WARN_ON_ONCE(ret < 0)) 1075 return 0; 1076 1077 ret = rk_iommu_enable(iommu); 1078 if (ret) 1079 WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev)); 1080 1081 pm_runtime_put(iommu->dev); 1082 1083 return ret; 1084 } 1085 1086 static struct iommu_domain *rk_iommu_domain_alloc(unsigned type) 1087 { 1088 struct rk_iommu_domain *rk_domain; 1089 1090 if (type == IOMMU_DOMAIN_IDENTITY) 1091 return &rk_identity_domain; 1092 1093 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) 1094 return NULL; 1095 1096 if (!dma_dev) 1097 return NULL; 1098 1099 rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL); 1100 if (!rk_domain) 1101 return NULL; 1102 1103 /* 1104 * rk32xx iommus use a 2 level pagetable. 1105 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries. 1106 * Allocate one 4 KiB page for each table. 1107 */ 1108 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32); 1109 if (!rk_domain->dt) 1110 goto err_free_domain; 1111 1112 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt, 1113 SPAGE_SIZE, DMA_TO_DEVICE); 1114 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) { 1115 dev_err(dma_dev, "DMA map error for DT\n"); 1116 goto err_free_dt; 1117 } 1118 1119 spin_lock_init(&rk_domain->iommus_lock); 1120 spin_lock_init(&rk_domain->dt_lock); 1121 INIT_LIST_HEAD(&rk_domain->iommus); 1122 1123 rk_domain->domain.geometry.aperture_start = 0; 1124 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32); 1125 rk_domain->domain.geometry.force_aperture = true; 1126 1127 return &rk_domain->domain; 1128 1129 err_free_dt: 1130 free_page((unsigned long)rk_domain->dt); 1131 err_free_domain: 1132 kfree(rk_domain); 1133 1134 return NULL; 1135 } 1136 1137 static void rk_iommu_domain_free(struct iommu_domain *domain) 1138 { 1139 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1140 int i; 1141 1142 WARN_ON(!list_empty(&rk_domain->iommus)); 1143 1144 for (i = 0; i < NUM_DT_ENTRIES; i++) { 1145 u32 dte = rk_domain->dt[i]; 1146 if (rk_dte_is_pt_valid(dte)) { 1147 phys_addr_t pt_phys = rk_ops->pt_address(dte); 1148 u32 *page_table = phys_to_virt(pt_phys); 1149 dma_unmap_single(dma_dev, pt_phys, 1150 SPAGE_SIZE, DMA_TO_DEVICE); 1151 free_page((unsigned long)page_table); 1152 } 1153 } 1154 1155 dma_unmap_single(dma_dev, rk_domain->dt_dma, 1156 SPAGE_SIZE, DMA_TO_DEVICE); 1157 free_page((unsigned long)rk_domain->dt); 1158 1159 kfree(rk_domain); 1160 } 1161 1162 static struct iommu_device *rk_iommu_probe_device(struct device *dev) 1163 { 1164 struct rk_iommudata *data; 1165 struct rk_iommu *iommu; 1166 1167 data = dev_iommu_priv_get(dev); 1168 if (!data) 1169 return ERR_PTR(-ENODEV); 1170 1171 iommu = rk_iommu_from_dev(dev); 1172 1173 data->link = device_link_add(dev, iommu->dev, 1174 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1175 1176 return &iommu->iommu; 1177 } 1178 1179 static void rk_iommu_release_device(struct device *dev) 1180 { 1181 struct rk_iommudata *data = dev_iommu_priv_get(dev); 1182 1183 device_link_del(data->link); 1184 } 1185 1186 static struct iommu_group *rk_iommu_device_group(struct device *dev) 1187 { 1188 struct rk_iommu *iommu; 1189 1190 iommu = rk_iommu_from_dev(dev); 1191 1192 return iommu_group_ref_get(iommu->group); 1193 } 1194 1195 static int rk_iommu_of_xlate(struct device *dev, 1196 struct of_phandle_args *args) 1197 { 1198 struct platform_device *iommu_dev; 1199 struct rk_iommudata *data; 1200 1201 data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL); 1202 if (!data) 1203 return -ENOMEM; 1204 1205 iommu_dev = of_find_device_by_node(args->np); 1206 1207 data->iommu = platform_get_drvdata(iommu_dev); 1208 data->iommu->domain = &rk_identity_domain; 1209 dev_iommu_priv_set(dev, data); 1210 1211 platform_device_put(iommu_dev); 1212 1213 return 0; 1214 } 1215 1216 static const struct iommu_ops rk_iommu_ops = { 1217 .domain_alloc = rk_iommu_domain_alloc, 1218 .probe_device = rk_iommu_probe_device, 1219 .release_device = rk_iommu_release_device, 1220 .device_group = rk_iommu_device_group, 1221 #ifdef CONFIG_ARM 1222 .set_platform_dma_ops = rk_iommu_set_platform_dma, 1223 #endif 1224 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, 1225 .of_xlate = rk_iommu_of_xlate, 1226 .default_domain_ops = &(const struct iommu_domain_ops) { 1227 .attach_dev = rk_iommu_attach_device, 1228 .map = rk_iommu_map, 1229 .unmap = rk_iommu_unmap, 1230 .iova_to_phys = rk_iommu_iova_to_phys, 1231 .free = rk_iommu_domain_free, 1232 } 1233 }; 1234 1235 static int rk_iommu_probe(struct platform_device *pdev) 1236 { 1237 struct device *dev = &pdev->dev; 1238 struct rk_iommu *iommu; 1239 struct resource *res; 1240 const struct rk_iommu_ops *ops; 1241 int num_res = pdev->num_resources; 1242 int err, i; 1243 1244 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); 1245 if (!iommu) 1246 return -ENOMEM; 1247 1248 platform_set_drvdata(pdev, iommu); 1249 iommu->dev = dev; 1250 iommu->num_mmu = 0; 1251 1252 ops = of_device_get_match_data(dev); 1253 if (!rk_ops) 1254 rk_ops = ops; 1255 1256 /* 1257 * That should not happen unless different versions of the 1258 * hardware block are embedded the same SoC 1259 */ 1260 if (WARN_ON(rk_ops != ops)) 1261 return -EINVAL; 1262 1263 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), 1264 GFP_KERNEL); 1265 if (!iommu->bases) 1266 return -ENOMEM; 1267 1268 for (i = 0; i < num_res; i++) { 1269 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 1270 if (!res) 1271 continue; 1272 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res); 1273 if (IS_ERR(iommu->bases[i])) 1274 continue; 1275 iommu->num_mmu++; 1276 } 1277 if (iommu->num_mmu == 0) 1278 return PTR_ERR(iommu->bases[0]); 1279 1280 iommu->num_irq = platform_irq_count(pdev); 1281 if (iommu->num_irq < 0) 1282 return iommu->num_irq; 1283 1284 iommu->reset_disabled = device_property_read_bool(dev, 1285 "rockchip,disable-mmu-reset"); 1286 1287 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks); 1288 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks, 1289 sizeof(*iommu->clocks), GFP_KERNEL); 1290 if (!iommu->clocks) 1291 return -ENOMEM; 1292 1293 for (i = 0; i < iommu->num_clocks; ++i) 1294 iommu->clocks[i].id = rk_iommu_clocks[i]; 1295 1296 /* 1297 * iommu clocks should be present for all new devices and devicetrees 1298 * but there are older devicetrees without clocks out in the wild. 1299 * So clocks as optional for the time being. 1300 */ 1301 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks); 1302 if (err == -ENOENT) 1303 iommu->num_clocks = 0; 1304 else if (err) 1305 return err; 1306 1307 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks); 1308 if (err) 1309 return err; 1310 1311 iommu->group = iommu_group_alloc(); 1312 if (IS_ERR(iommu->group)) { 1313 err = PTR_ERR(iommu->group); 1314 goto err_unprepare_clocks; 1315 } 1316 1317 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev)); 1318 if (err) 1319 goto err_put_group; 1320 1321 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev); 1322 if (err) 1323 goto err_remove_sysfs; 1324 1325 /* 1326 * Use the first registered IOMMU device for domain to use with DMA 1327 * API, since a domain might not physically correspond to a single 1328 * IOMMU device.. 1329 */ 1330 if (!dma_dev) 1331 dma_dev = &pdev->dev; 1332 1333 pm_runtime_enable(dev); 1334 1335 for (i = 0; i < iommu->num_irq; i++) { 1336 int irq = platform_get_irq(pdev, i); 1337 1338 if (irq < 0) { 1339 err = irq; 1340 goto err_pm_disable; 1341 } 1342 1343 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, 1344 IRQF_SHARED, dev_name(dev), iommu); 1345 if (err) 1346 goto err_pm_disable; 1347 } 1348 1349 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask); 1350 1351 return 0; 1352 err_pm_disable: 1353 pm_runtime_disable(dev); 1354 err_remove_sysfs: 1355 iommu_device_sysfs_remove(&iommu->iommu); 1356 err_put_group: 1357 iommu_group_put(iommu->group); 1358 err_unprepare_clocks: 1359 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks); 1360 return err; 1361 } 1362 1363 static void rk_iommu_shutdown(struct platform_device *pdev) 1364 { 1365 struct rk_iommu *iommu = platform_get_drvdata(pdev); 1366 int i; 1367 1368 for (i = 0; i < iommu->num_irq; i++) { 1369 int irq = platform_get_irq(pdev, i); 1370 1371 devm_free_irq(iommu->dev, irq, iommu); 1372 } 1373 1374 pm_runtime_force_suspend(&pdev->dev); 1375 } 1376 1377 static int __maybe_unused rk_iommu_suspend(struct device *dev) 1378 { 1379 struct rk_iommu *iommu = dev_get_drvdata(dev); 1380 1381 if (iommu->domain == &rk_identity_domain) 1382 return 0; 1383 1384 rk_iommu_disable(iommu); 1385 return 0; 1386 } 1387 1388 static int __maybe_unused rk_iommu_resume(struct device *dev) 1389 { 1390 struct rk_iommu *iommu = dev_get_drvdata(dev); 1391 1392 if (iommu->domain == &rk_identity_domain) 1393 return 0; 1394 1395 return rk_iommu_enable(iommu); 1396 } 1397 1398 static const struct dev_pm_ops rk_iommu_pm_ops = { 1399 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL) 1400 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1401 pm_runtime_force_resume) 1402 }; 1403 1404 static struct rk_iommu_ops iommu_data_ops_v1 = { 1405 .pt_address = &rk_dte_pt_address, 1406 .mk_dtentries = &rk_mk_dte, 1407 .mk_ptentries = &rk_mk_pte, 1408 .dte_addr_phys = &rk_dte_addr_phys, 1409 .dma_addr_dte = &rk_dma_addr_dte, 1410 .dma_bit_mask = DMA_BIT_MASK(32), 1411 }; 1412 1413 static struct rk_iommu_ops iommu_data_ops_v2 = { 1414 .pt_address = &rk_dte_pt_address_v2, 1415 .mk_dtentries = &rk_mk_dte_v2, 1416 .mk_ptentries = &rk_mk_pte_v2, 1417 .dte_addr_phys = &rk_dte_addr_phys_v2, 1418 .dma_addr_dte = &rk_dma_addr_dte_v2, 1419 .dma_bit_mask = DMA_BIT_MASK(40), 1420 }; 1421 1422 static const struct of_device_id rk_iommu_dt_ids[] = { 1423 { .compatible = "rockchip,iommu", 1424 .data = &iommu_data_ops_v1, 1425 }, 1426 { .compatible = "rockchip,rk3568-iommu", 1427 .data = &iommu_data_ops_v2, 1428 }, 1429 { /* sentinel */ } 1430 }; 1431 1432 static struct platform_driver rk_iommu_driver = { 1433 .probe = rk_iommu_probe, 1434 .shutdown = rk_iommu_shutdown, 1435 .driver = { 1436 .name = "rk_iommu", 1437 .of_match_table = rk_iommu_dt_ids, 1438 .pm = &rk_iommu_pm_ops, 1439 .suppress_bind_attrs = true, 1440 }, 1441 }; 1442 builtin_platform_driver(rk_iommu_driver); 1443