1 /* 2 * omap iommu: main structures 3 * 4 * Copyright (C) 2008-2009 Nokia Corporation 5 * 6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef _OMAP_IOMMU_H 14 #define _OMAP_IOMMU_H 15 16 #include <linux/bitops.h> 17 #include <linux/iommu.h> 18 19 #define for_each_iotlb_cr(obj, n, __i, cr) \ 20 for (__i = 0; \ 21 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ 22 __i++) 23 24 struct iotlb_entry { 25 u32 da; 26 u32 pa; 27 u32 pgsz, prsvd, valid; 28 u32 endian, elsz, mixed; 29 }; 30 31 /** 32 * struct omap_iommu_domain - omap iommu domain 33 * @pgtable: the page table 34 * @iommu_dev: an omap iommu device attached to this domain. only a single 35 * iommu device can be attached for now. 36 * @dev: Device using this domain. 37 * @lock: domain lock, should be taken when attaching/detaching 38 * @domain: generic domain handle used by iommu core code 39 */ 40 struct omap_iommu_domain { 41 u32 *pgtable; 42 struct omap_iommu *iommu_dev; 43 struct device *dev; 44 spinlock_t lock; 45 struct iommu_domain domain; 46 }; 47 48 struct omap_iommu { 49 const char *name; 50 void __iomem *regbase; 51 struct regmap *syscfg; 52 struct device *dev; 53 struct iommu_domain *domain; 54 struct dentry *debug_dir; 55 56 spinlock_t iommu_lock; /* global for this whole object */ 57 58 /* 59 * We don't change iopgd for a situation like pgd for a task, 60 * but share it globally for each iommu. 61 */ 62 u32 *iopgd; 63 spinlock_t page_table_lock; /* protect iopgd */ 64 dma_addr_t pd_dma; 65 66 int nr_tlb_entries; 67 68 void *ctx; /* iommu context: registres saved area */ 69 70 int has_bus_err_back; 71 u32 id; 72 73 struct iommu_device iommu; 74 struct iommu_group *group; 75 }; 76 77 /** 78 * struct omap_iommu_arch_data - omap iommu private data 79 * @iommu_dev: handle of the iommu device 80 * 81 * This is an omap iommu private data object, which binds an iommu user 82 * to its iommu device. This object should be placed at the iommu user's 83 * dev_archdata so generic IOMMU API can be used without having to 84 * utilize omap-specific plumbing anymore. 85 */ 86 struct omap_iommu_arch_data { 87 struct omap_iommu *iommu_dev; 88 }; 89 90 struct cr_regs { 91 u32 cam; 92 u32 ram; 93 }; 94 95 struct iotlb_lock { 96 short base; 97 short vict; 98 }; 99 100 /** 101 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device 102 * @dev: iommu client device 103 */ 104 static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) 105 { 106 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; 107 108 return arch_data->iommu_dev; 109 } 110 111 /* 112 * MMU Register offsets 113 */ 114 #define MMU_REVISION 0x00 115 #define MMU_IRQSTATUS 0x18 116 #define MMU_IRQENABLE 0x1c 117 #define MMU_WALKING_ST 0x40 118 #define MMU_CNTL 0x44 119 #define MMU_FAULT_AD 0x48 120 #define MMU_TTB 0x4c 121 #define MMU_LOCK 0x50 122 #define MMU_LD_TLB 0x54 123 #define MMU_CAM 0x58 124 #define MMU_RAM 0x5c 125 #define MMU_GFLUSH 0x60 126 #define MMU_FLUSH_ENTRY 0x64 127 #define MMU_READ_CAM 0x68 128 #define MMU_READ_RAM 0x6c 129 #define MMU_EMU_FAULT_AD 0x70 130 #define MMU_GP_REG 0x88 131 132 #define MMU_REG_SIZE 256 133 134 /* 135 * MMU Register bit definitions 136 */ 137 /* IRQSTATUS & IRQENABLE */ 138 #define MMU_IRQ_MULTIHITFAULT BIT(4) 139 #define MMU_IRQ_TABLEWALKFAULT BIT(3) 140 #define MMU_IRQ_EMUMISS BIT(2) 141 #define MMU_IRQ_TRANSLATIONFAULT BIT(1) 142 #define MMU_IRQ_TLBMISS BIT(0) 143 144 #define __MMU_IRQ_FAULT \ 145 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) 146 #define MMU_IRQ_MASK \ 147 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) 148 #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) 149 #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) 150 151 /* MMU_CNTL */ 152 #define MMU_CNTL_SHIFT 1 153 #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) 154 #define MMU_CNTL_EML_TLB BIT(3) 155 #define MMU_CNTL_TWL_EN BIT(2) 156 #define MMU_CNTL_MMU_EN BIT(1) 157 158 /* CAM */ 159 #define MMU_CAM_VATAG_SHIFT 12 160 #define MMU_CAM_VATAG_MASK \ 161 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) 162 #define MMU_CAM_P BIT(3) 163 #define MMU_CAM_V BIT(2) 164 #define MMU_CAM_PGSZ_MASK 3 165 #define MMU_CAM_PGSZ_1M (0 << 0) 166 #define MMU_CAM_PGSZ_64K (1 << 0) 167 #define MMU_CAM_PGSZ_4K (2 << 0) 168 #define MMU_CAM_PGSZ_16M (3 << 0) 169 170 /* RAM */ 171 #define MMU_RAM_PADDR_SHIFT 12 172 #define MMU_RAM_PADDR_MASK \ 173 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) 174 175 #define MMU_RAM_ENDIAN_SHIFT 9 176 #define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT) 177 #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) 178 #define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT) 179 180 #define MMU_RAM_ELSZ_SHIFT 7 181 #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) 182 #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) 183 #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) 184 #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) 185 #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) 186 #define MMU_RAM_MIXED_SHIFT 6 187 #define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT) 188 #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK 189 190 #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1 191 192 #define get_cam_va_mask(pgsz) \ 193 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ 194 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ 195 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ 196 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) 197 198 /* 199 * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP) 200 */ 201 #define DSP_SYS_REVISION 0x00 202 #define DSP_SYS_MMU_CONFIG 0x18 203 #define DSP_SYS_MMU_CONFIG_EN_SHIFT 4 204 205 /* 206 * utilities for super page(16MB, 1MB, 64KB and 4KB) 207 */ 208 209 #define iopgsz_max(bytes) \ 210 (((bytes) >= SZ_16M) ? SZ_16M : \ 211 ((bytes) >= SZ_1M) ? SZ_1M : \ 212 ((bytes) >= SZ_64K) ? SZ_64K : \ 213 ((bytes) >= SZ_4K) ? SZ_4K : 0) 214 215 #define bytes_to_iopgsz(bytes) \ 216 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ 217 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ 218 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ 219 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) 220 221 #define iopgsz_to_bytes(iopgsz) \ 222 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ 223 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ 224 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ 225 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) 226 227 #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) 228 229 /* 230 * global functions 231 */ 232 233 struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n); 234 void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l); 235 void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l); 236 237 #ifdef CONFIG_OMAP_IOMMU_DEBUG 238 void omap_iommu_debugfs_init(void); 239 void omap_iommu_debugfs_exit(void); 240 241 void omap_iommu_debugfs_add(struct omap_iommu *obj); 242 void omap_iommu_debugfs_remove(struct omap_iommu *obj); 243 #else 244 static inline void omap_iommu_debugfs_init(void) { } 245 static inline void omap_iommu_debugfs_exit(void) { } 246 247 static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { } 248 static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { } 249 #endif 250 251 /* 252 * register accessors 253 */ 254 static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs) 255 { 256 return __raw_readl(obj->regbase + offs); 257 } 258 259 static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) 260 { 261 __raw_writel(val, obj->regbase + offs); 262 } 263 264 static inline int iotlb_cr_valid(struct cr_regs *cr) 265 { 266 if (!cr) 267 return -EINVAL; 268 269 return cr->cam & MMU_CAM_V; 270 } 271 272 #endif /* _OMAP_IOMMU_H */ 273