1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2ed1c7de2STony Lindgren /*
3ed1c7de2STony Lindgren * omap iommu: main structures
4ed1c7de2STony Lindgren *
5ed1c7de2STony Lindgren * Copyright (C) 2008-2009 Nokia Corporation
6ed1c7de2STony Lindgren *
7ed1c7de2STony Lindgren * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8ed1c7de2STony Lindgren */
9ed1c7de2STony Lindgren
10533b40ccSSuman Anna #ifndef _OMAP_IOMMU_H
11533b40ccSSuman Anna #define _OMAP_IOMMU_H
12533b40ccSSuman Anna
13eb642a3fSSuman Anna #include <linux/bitops.h>
14e73b7afeSJoerg Roedel #include <linux/iommu.h>
15eb642a3fSSuman Anna
1669c2c196SSuman Anna #define for_each_iotlb_cr(obj, n, __i, cr) \
1769c2c196SSuman Anna for (__i = 0; \
1869c2c196SSuman Anna (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
1969c2c196SSuman Anna __i++)
2069c2c196SSuman Anna
21ed1c7de2STony Lindgren struct iotlb_entry {
22ed1c7de2STony Lindgren u32 da;
23ed1c7de2STony Lindgren u32 pa;
24ed1c7de2STony Lindgren u32 pgsz, prsvd, valid;
25ed1c7de2STony Lindgren u32 endian, elsz, mixed;
26ed1c7de2STony Lindgren };
27ed1c7de2STony Lindgren
28e73b7afeSJoerg Roedel /**
299d5018deSSuman Anna * struct omap_iommu_device - omap iommu device data
309d5018deSSuman Anna * @pgtable: page table used by an omap iommu attached to a domain
319d5018deSSuman Anna * @iommu_dev: pointer to store an omap iommu instance attached to a domain
329d5018deSSuman Anna */
339d5018deSSuman Anna struct omap_iommu_device {
349d5018deSSuman Anna u32 *pgtable;
359d5018deSSuman Anna struct omap_iommu *iommu_dev;
369d5018deSSuman Anna };
379d5018deSSuman Anna
389d5018deSSuman Anna /**
39e73b7afeSJoerg Roedel * struct omap_iommu_domain - omap iommu domain
409d5018deSSuman Anna * @num_iommus: number of iommus in this domain
419d5018deSSuman Anna * @iommus: omap iommu device data for all iommus in this domain
42e73b7afeSJoerg Roedel * @dev: Device using this domain.
43e73b7afeSJoerg Roedel * @lock: domain lock, should be taken when attaching/detaching
44e73b7afeSJoerg Roedel * @domain: generic domain handle used by iommu core code
45e73b7afeSJoerg Roedel */
46e73b7afeSJoerg Roedel struct omap_iommu_domain {
479d5018deSSuman Anna u32 num_iommus;
489d5018deSSuman Anna struct omap_iommu_device *iommus;
49e73b7afeSJoerg Roedel struct device *dev;
50e73b7afeSJoerg Roedel spinlock_t lock;
51e73b7afeSJoerg Roedel struct iommu_domain domain;
52e73b7afeSJoerg Roedel };
53e73b7afeSJoerg Roedel
54ed1c7de2STony Lindgren struct omap_iommu {
55ed1c7de2STony Lindgren const char *name;
56ed1c7de2STony Lindgren void __iomem *regbase;
573ca9299eSSuman Anna struct regmap *syscfg;
58ed1c7de2STony Lindgren struct device *dev;
59ed1c7de2STony Lindgren struct iommu_domain *domain;
6061c75352SSuman Anna struct dentry *debug_dir;
61ed1c7de2STony Lindgren
62ed1c7de2STony Lindgren spinlock_t iommu_lock; /* global for this whole object */
63ed1c7de2STony Lindgren
64ed1c7de2STony Lindgren /*
65ed1c7de2STony Lindgren * We don't change iopgd for a situation like pgd for a task,
66ed1c7de2STony Lindgren * but share it globally for each iommu.
67ed1c7de2STony Lindgren */
68ed1c7de2STony Lindgren u32 *iopgd;
69ed1c7de2STony Lindgren spinlock_t page_table_lock; /* protect iopgd */
70bfee0cf0SJosue Albarran dma_addr_t pd_dma;
71ed1c7de2STony Lindgren
72ed1c7de2STony Lindgren int nr_tlb_entries;
73ed1c7de2STony Lindgren
74ed1c7de2STony Lindgren void *ctx; /* iommu context: registres saved area */
75b148d5fbSSuman Anna
76c3b44a06SSuman Anna struct cr_regs *cr_ctx;
77c3b44a06SSuman Anna u32 num_cr_ctx;
78c3b44a06SSuman Anna
79b148d5fbSSuman Anna int has_bus_err_back;
803ca9299eSSuman Anna u32 id;
8101611fe8SJoerg Roedel
8201611fe8SJoerg Roedel struct iommu_device iommu;
8328ae1e3eSJoerg Roedel struct iommu_group *group;
843846a3b9SSuman Anna
853846a3b9SSuman Anna u8 pwrst;
86ed1c7de2STony Lindgren };
87ed1c7de2STony Lindgren
88e73b7afeSJoerg Roedel /**
89e73b7afeSJoerg Roedel * struct omap_iommu_arch_data - omap iommu private data
90604629bcSTero Kristo * @iommu_dev: handle of the OMAP iommu device
91604629bcSTero Kristo * @dev: handle of the iommu device
92e73b7afeSJoerg Roedel *
93e73b7afeSJoerg Roedel * This is an omap iommu private data object, which binds an iommu user
94e73b7afeSJoerg Roedel * to its iommu device. This object should be placed at the iommu user's
95e73b7afeSJoerg Roedel * dev_archdata so generic IOMMU API can be used without having to
96e73b7afeSJoerg Roedel * utilize omap-specific plumbing anymore.
97e73b7afeSJoerg Roedel */
98e73b7afeSJoerg Roedel struct omap_iommu_arch_data {
99e73b7afeSJoerg Roedel struct omap_iommu *iommu_dev;
100604629bcSTero Kristo struct device *dev;
101e73b7afeSJoerg Roedel };
102e73b7afeSJoerg Roedel
103ed1c7de2STony Lindgren struct cr_regs {
104ed1c7de2STony Lindgren u32 cam;
105ed1c7de2STony Lindgren u32 ram;
106ed1c7de2STony Lindgren };
107ed1c7de2STony Lindgren
10869c2c196SSuman Anna struct iotlb_lock {
10969c2c196SSuman Anna short base;
11069c2c196SSuman Anna short vict;
11169c2c196SSuman Anna };
11269c2c196SSuman Anna
113ed1c7de2STony Lindgren /*
114ed1c7de2STony Lindgren * MMU Register offsets
115ed1c7de2STony Lindgren */
116ed1c7de2STony Lindgren #define MMU_REVISION 0x00
117ed1c7de2STony Lindgren #define MMU_IRQSTATUS 0x18
118ed1c7de2STony Lindgren #define MMU_IRQENABLE 0x1c
119ed1c7de2STony Lindgren #define MMU_WALKING_ST 0x40
120ed1c7de2STony Lindgren #define MMU_CNTL 0x44
121ed1c7de2STony Lindgren #define MMU_FAULT_AD 0x48
122ed1c7de2STony Lindgren #define MMU_TTB 0x4c
123ed1c7de2STony Lindgren #define MMU_LOCK 0x50
124ed1c7de2STony Lindgren #define MMU_LD_TLB 0x54
125ed1c7de2STony Lindgren #define MMU_CAM 0x58
126ed1c7de2STony Lindgren #define MMU_RAM 0x5c
127ed1c7de2STony Lindgren #define MMU_GFLUSH 0x60
128ed1c7de2STony Lindgren #define MMU_FLUSH_ENTRY 0x64
129ed1c7de2STony Lindgren #define MMU_READ_CAM 0x68
130ed1c7de2STony Lindgren #define MMU_READ_RAM 0x6c
131ed1c7de2STony Lindgren #define MMU_EMU_FAULT_AD 0x70
132b148d5fbSSuman Anna #define MMU_GP_REG 0x88
133ed1c7de2STony Lindgren
134ed1c7de2STony Lindgren #define MMU_REG_SIZE 256
135ed1c7de2STony Lindgren
136ed1c7de2STony Lindgren /*
137ed1c7de2STony Lindgren * MMU Register bit definitions
138ed1c7de2STony Lindgren */
139bd4396f0SSuman Anna /* IRQSTATUS & IRQENABLE */
140eb642a3fSSuman Anna #define MMU_IRQ_MULTIHITFAULT BIT(4)
141eb642a3fSSuman Anna #define MMU_IRQ_TABLEWALKFAULT BIT(3)
142eb642a3fSSuman Anna #define MMU_IRQ_EMUMISS BIT(2)
143eb642a3fSSuman Anna #define MMU_IRQ_TRANSLATIONFAULT BIT(1)
144eb642a3fSSuman Anna #define MMU_IRQ_TLBMISS BIT(0)
145bd4396f0SSuman Anna
146bd4396f0SSuman Anna #define __MMU_IRQ_FAULT \
147bd4396f0SSuman Anna (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
148bd4396f0SSuman Anna #define MMU_IRQ_MASK \
149bd4396f0SSuman Anna (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
150bd4396f0SSuman Anna #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
151bd4396f0SSuman Anna #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
152bd4396f0SSuman Anna
153bd4396f0SSuman Anna /* MMU_CNTL */
154bd4396f0SSuman Anna #define MMU_CNTL_SHIFT 1
155bd4396f0SSuman Anna #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
156eb642a3fSSuman Anna #define MMU_CNTL_EML_TLB BIT(3)
157eb642a3fSSuman Anna #define MMU_CNTL_TWL_EN BIT(2)
158eb642a3fSSuman Anna #define MMU_CNTL_MMU_EN BIT(1)
159bd4396f0SSuman Anna
160bd4396f0SSuman Anna /* CAM */
161ed1c7de2STony Lindgren #define MMU_CAM_VATAG_SHIFT 12
162ed1c7de2STony Lindgren #define MMU_CAM_VATAG_MASK \
163ed1c7de2STony Lindgren ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
164eb642a3fSSuman Anna #define MMU_CAM_P BIT(3)
165eb642a3fSSuman Anna #define MMU_CAM_V BIT(2)
166ed1c7de2STony Lindgren #define MMU_CAM_PGSZ_MASK 3
167ed1c7de2STony Lindgren #define MMU_CAM_PGSZ_1M (0 << 0)
168ed1c7de2STony Lindgren #define MMU_CAM_PGSZ_64K (1 << 0)
169ed1c7de2STony Lindgren #define MMU_CAM_PGSZ_4K (2 << 0)
170ed1c7de2STony Lindgren #define MMU_CAM_PGSZ_16M (3 << 0)
171ed1c7de2STony Lindgren
172bd4396f0SSuman Anna /* RAM */
173ed1c7de2STony Lindgren #define MMU_RAM_PADDR_SHIFT 12
174ed1c7de2STony Lindgren #define MMU_RAM_PADDR_MASK \
175ed1c7de2STony Lindgren ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
176ed1c7de2STony Lindgren
177baaa7b5dSLaurent Pinchart #define MMU_RAM_ENDIAN_SHIFT 9
178eb642a3fSSuman Anna #define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
179baaa7b5dSLaurent Pinchart #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
180eb642a3fSSuman Anna #define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT)
181ed1c7de2STony Lindgren
182baaa7b5dSLaurent Pinchart #define MMU_RAM_ELSZ_SHIFT 7
183ed1c7de2STony Lindgren #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
184ed1c7de2STony Lindgren #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
185ed1c7de2STony Lindgren #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
186ed1c7de2STony Lindgren #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
187ed1c7de2STony Lindgren #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
188ed1c7de2STony Lindgren #define MMU_RAM_MIXED_SHIFT 6
189eb642a3fSSuman Anna #define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT)
190ed1c7de2STony Lindgren #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
191ed1c7de2STony Lindgren
192b148d5fbSSuman Anna #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
193b148d5fbSSuman Anna
194bd4396f0SSuman Anna #define get_cam_va_mask(pgsz) \
195bd4396f0SSuman Anna (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
196bd4396f0SSuman Anna ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
197bd4396f0SSuman Anna ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
198bd4396f0SSuman Anna ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
199bd4396f0SSuman Anna
200ed1c7de2STony Lindgren /*
2013ca9299eSSuman Anna * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
2023ca9299eSSuman Anna */
2033ca9299eSSuman Anna #define DSP_SYS_REVISION 0x00
2043ca9299eSSuman Anna #define DSP_SYS_MMU_CONFIG 0x18
2053ca9299eSSuman Anna #define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
2063ca9299eSSuman Anna
2073ca9299eSSuman Anna /*
208ed1c7de2STony Lindgren * utilities for super page(16MB, 1MB, 64KB and 4KB)
209ed1c7de2STony Lindgren */
210ed1c7de2STony Lindgren
211ed1c7de2STony Lindgren #define iopgsz_max(bytes) \
212ed1c7de2STony Lindgren (((bytes) >= SZ_16M) ? SZ_16M : \
213ed1c7de2STony Lindgren ((bytes) >= SZ_1M) ? SZ_1M : \
214ed1c7de2STony Lindgren ((bytes) >= SZ_64K) ? SZ_64K : \
215ed1c7de2STony Lindgren ((bytes) >= SZ_4K) ? SZ_4K : 0)
216ed1c7de2STony Lindgren
217ed1c7de2STony Lindgren #define bytes_to_iopgsz(bytes) \
218ed1c7de2STony Lindgren (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
219ed1c7de2STony Lindgren ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
220ed1c7de2STony Lindgren ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
221ed1c7de2STony Lindgren ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
222ed1c7de2STony Lindgren
223ed1c7de2STony Lindgren #define iopgsz_to_bytes(iopgsz) \
224ed1c7de2STony Lindgren (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
225ed1c7de2STony Lindgren ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
226ed1c7de2STony Lindgren ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
227ed1c7de2STony Lindgren ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
228ed1c7de2STony Lindgren
229ed1c7de2STony Lindgren #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
230ed1c7de2STony Lindgren
231ed1c7de2STony Lindgren /*
232ed1c7de2STony Lindgren * global functions
233ed1c7de2STony Lindgren */
234ed1c7de2STony Lindgren
23569c2c196SSuman Anna struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
23669c2c196SSuman Anna void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
23769c2c196SSuman Anna void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
23869c2c196SSuman Anna
23969c2c196SSuman Anna #ifdef CONFIG_OMAP_IOMMU_DEBUG
24061c75352SSuman Anna void omap_iommu_debugfs_init(void);
24161c75352SSuman Anna void omap_iommu_debugfs_exit(void);
24261c75352SSuman Anna
24361c75352SSuman Anna void omap_iommu_debugfs_add(struct omap_iommu *obj);
24461c75352SSuman Anna void omap_iommu_debugfs_remove(struct omap_iommu *obj);
24561c75352SSuman Anna #else
omap_iommu_debugfs_init(void)24661c75352SSuman Anna static inline void omap_iommu_debugfs_init(void) { }
omap_iommu_debugfs_exit(void)24761c75352SSuman Anna static inline void omap_iommu_debugfs_exit(void) { }
24861c75352SSuman Anna
omap_iommu_debugfs_add(struct omap_iommu * obj)24961c75352SSuman Anna static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
omap_iommu_debugfs_remove(struct omap_iommu * obj)25061c75352SSuman Anna static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
25161c75352SSuman Anna #endif
25261c75352SSuman Anna
253ed1c7de2STony Lindgren /*
254ed1c7de2STony Lindgren * register accessors
255ed1c7de2STony Lindgren */
iommu_read_reg(struct omap_iommu * obj,size_t offs)256ed1c7de2STony Lindgren static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
257ed1c7de2STony Lindgren {
258ed1c7de2STony Lindgren return __raw_readl(obj->regbase + offs);
259ed1c7de2STony Lindgren }
260ed1c7de2STony Lindgren
iommu_write_reg(struct omap_iommu * obj,u32 val,size_t offs)261ed1c7de2STony Lindgren static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
262ed1c7de2STony Lindgren {
263ed1c7de2STony Lindgren __raw_writel(val, obj->regbase + offs);
264ed1c7de2STony Lindgren }
265533b40ccSSuman Anna
iotlb_cr_valid(struct cr_regs * cr)26669c2c196SSuman Anna static inline int iotlb_cr_valid(struct cr_regs *cr)
26769c2c196SSuman Anna {
26869c2c196SSuman Anna if (!cr)
26969c2c196SSuman Anna return -EINVAL;
27069c2c196SSuman Anna
27169c2c196SSuman Anna return cr->cam & MMU_CAM_V;
27269c2c196SSuman Anna }
27369c2c196SSuman Anna
274533b40ccSSuman Anna #endif /* _OMAP_IOMMU_H */
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