1 /* 2 * omap iommu: tlb and pagetable primitives 3 * 4 * Copyright (C) 2008-2010 Nokia Corporation 5 * 6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, 7 * Paul Mundt and Toshihiro Kobayashi 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/err.h> 15 #include <linux/slab.h> 16 #include <linux/interrupt.h> 17 #include <linux/ioport.h> 18 #include <linux/platform_device.h> 19 #include <linux/iommu.h> 20 #include <linux/omap-iommu.h> 21 #include <linux/mutex.h> 22 #include <linux/spinlock.h> 23 #include <linux/io.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/of.h> 26 #include <linux/of_iommu.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_platform.h> 29 30 #include <asm/cacheflush.h> 31 32 #include <linux/platform_data/iommu-omap.h> 33 34 #include "omap-iopgtable.h" 35 #include "omap-iommu.h" 36 37 #define to_iommu(dev) \ 38 ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))) 39 40 /* bitmap of the page sizes currently supported */ 41 #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) 42 43 /** 44 * struct omap_iommu_domain - omap iommu domain 45 * @pgtable: the page table 46 * @iommu_dev: an omap iommu device attached to this domain. only a single 47 * iommu device can be attached for now. 48 * @dev: Device using this domain. 49 * @lock: domain lock, should be taken when attaching/detaching 50 */ 51 struct omap_iommu_domain { 52 u32 *pgtable; 53 struct omap_iommu *iommu_dev; 54 struct device *dev; 55 spinlock_t lock; 56 struct iommu_domain domain; 57 }; 58 59 #define MMU_LOCK_BASE_SHIFT 10 60 #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) 61 #define MMU_LOCK_BASE(x) \ 62 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) 63 64 #define MMU_LOCK_VICT_SHIFT 4 65 #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) 66 #define MMU_LOCK_VICT(x) \ 67 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) 68 69 static struct platform_driver omap_iommu_driver; 70 static struct kmem_cache *iopte_cachep; 71 72 /** 73 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain 74 * @dom: generic iommu domain handle 75 **/ 76 static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom) 77 { 78 return container_of(dom, struct omap_iommu_domain, domain); 79 } 80 81 /** 82 * omap_iommu_save_ctx - Save registers for pm off-mode support 83 * @dev: client device 84 **/ 85 void omap_iommu_save_ctx(struct device *dev) 86 { 87 struct omap_iommu *obj = dev_to_omap_iommu(dev); 88 u32 *p = obj->ctx; 89 int i; 90 91 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { 92 p[i] = iommu_read_reg(obj, i * sizeof(u32)); 93 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); 94 } 95 } 96 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); 97 98 /** 99 * omap_iommu_restore_ctx - Restore registers for pm off-mode support 100 * @dev: client device 101 **/ 102 void omap_iommu_restore_ctx(struct device *dev) 103 { 104 struct omap_iommu *obj = dev_to_omap_iommu(dev); 105 u32 *p = obj->ctx; 106 int i; 107 108 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { 109 iommu_write_reg(obj, p[i], i * sizeof(u32)); 110 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); 111 } 112 } 113 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); 114 115 static void __iommu_set_twl(struct omap_iommu *obj, bool on) 116 { 117 u32 l = iommu_read_reg(obj, MMU_CNTL); 118 119 if (on) 120 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); 121 else 122 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); 123 124 l &= ~MMU_CNTL_MASK; 125 if (on) 126 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); 127 else 128 l |= (MMU_CNTL_MMU_EN); 129 130 iommu_write_reg(obj, l, MMU_CNTL); 131 } 132 133 static int omap2_iommu_enable(struct omap_iommu *obj) 134 { 135 u32 l, pa; 136 137 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) 138 return -EINVAL; 139 140 pa = virt_to_phys(obj->iopgd); 141 if (!IS_ALIGNED(pa, SZ_16K)) 142 return -EINVAL; 143 144 l = iommu_read_reg(obj, MMU_REVISION); 145 dev_info(obj->dev, "%s: version %d.%d\n", obj->name, 146 (l >> 4) & 0xf, l & 0xf); 147 148 iommu_write_reg(obj, pa, MMU_TTB); 149 150 if (obj->has_bus_err_back) 151 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); 152 153 __iommu_set_twl(obj, true); 154 155 return 0; 156 } 157 158 static void omap2_iommu_disable(struct omap_iommu *obj) 159 { 160 u32 l = iommu_read_reg(obj, MMU_CNTL); 161 162 l &= ~MMU_CNTL_MASK; 163 iommu_write_reg(obj, l, MMU_CNTL); 164 165 dev_dbg(obj->dev, "%s is shutting down\n", obj->name); 166 } 167 168 static int iommu_enable(struct omap_iommu *obj) 169 { 170 int err; 171 struct platform_device *pdev = to_platform_device(obj->dev); 172 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); 173 174 if (pdata && pdata->deassert_reset) { 175 err = pdata->deassert_reset(pdev, pdata->reset_name); 176 if (err) { 177 dev_err(obj->dev, "deassert_reset failed: %d\n", err); 178 return err; 179 } 180 } 181 182 pm_runtime_get_sync(obj->dev); 183 184 err = omap2_iommu_enable(obj); 185 186 return err; 187 } 188 189 static void iommu_disable(struct omap_iommu *obj) 190 { 191 struct platform_device *pdev = to_platform_device(obj->dev); 192 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); 193 194 omap2_iommu_disable(obj); 195 196 pm_runtime_put_sync(obj->dev); 197 198 if (pdata && pdata->assert_reset) 199 pdata->assert_reset(pdev, pdata->reset_name); 200 } 201 202 /* 203 * TLB operations 204 */ 205 static u32 iotlb_cr_to_virt(struct cr_regs *cr) 206 { 207 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; 208 u32 mask = get_cam_va_mask(cr->cam & page_size); 209 210 return cr->cam & mask; 211 } 212 213 static u32 get_iopte_attr(struct iotlb_entry *e) 214 { 215 u32 attr; 216 217 attr = e->mixed << 5; 218 attr |= e->endian; 219 attr |= e->elsz >> 3; 220 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) || 221 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6); 222 return attr; 223 } 224 225 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) 226 { 227 u32 status, fault_addr; 228 229 status = iommu_read_reg(obj, MMU_IRQSTATUS); 230 status &= MMU_IRQ_MASK; 231 if (!status) { 232 *da = 0; 233 return 0; 234 } 235 236 fault_addr = iommu_read_reg(obj, MMU_FAULT_AD); 237 *da = fault_addr; 238 239 iommu_write_reg(obj, status, MMU_IRQSTATUS); 240 241 return status; 242 } 243 244 void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) 245 { 246 u32 val; 247 248 val = iommu_read_reg(obj, MMU_LOCK); 249 250 l->base = MMU_LOCK_BASE(val); 251 l->vict = MMU_LOCK_VICT(val); 252 } 253 254 void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) 255 { 256 u32 val; 257 258 val = (l->base << MMU_LOCK_BASE_SHIFT); 259 val |= (l->vict << MMU_LOCK_VICT_SHIFT); 260 261 iommu_write_reg(obj, val, MMU_LOCK); 262 } 263 264 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) 265 { 266 cr->cam = iommu_read_reg(obj, MMU_READ_CAM); 267 cr->ram = iommu_read_reg(obj, MMU_READ_RAM); 268 } 269 270 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) 271 { 272 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); 273 iommu_write_reg(obj, cr->ram, MMU_RAM); 274 275 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); 276 iommu_write_reg(obj, 1, MMU_LD_TLB); 277 } 278 279 /* only used in iotlb iteration for-loop */ 280 struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) 281 { 282 struct cr_regs cr; 283 struct iotlb_lock l; 284 285 iotlb_lock_get(obj, &l); 286 l.vict = n; 287 iotlb_lock_set(obj, &l); 288 iotlb_read_cr(obj, &cr); 289 290 return cr; 291 } 292 293 #ifdef PREFETCH_IOTLB 294 static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, 295 struct iotlb_entry *e) 296 { 297 struct cr_regs *cr; 298 299 if (!e) 300 return NULL; 301 302 if (e->da & ~(get_cam_va_mask(e->pgsz))) { 303 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, 304 e->da); 305 return ERR_PTR(-EINVAL); 306 } 307 308 cr = kmalloc(sizeof(*cr), GFP_KERNEL); 309 if (!cr) 310 return ERR_PTR(-ENOMEM); 311 312 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; 313 cr->ram = e->pa | e->endian | e->elsz | e->mixed; 314 315 return cr; 316 } 317 318 /** 319 * load_iotlb_entry - Set an iommu tlb entry 320 * @obj: target iommu 321 * @e: an iommu tlb entry info 322 **/ 323 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) 324 { 325 int err = 0; 326 struct iotlb_lock l; 327 struct cr_regs *cr; 328 329 if (!obj || !obj->nr_tlb_entries || !e) 330 return -EINVAL; 331 332 pm_runtime_get_sync(obj->dev); 333 334 iotlb_lock_get(obj, &l); 335 if (l.base == obj->nr_tlb_entries) { 336 dev_warn(obj->dev, "%s: preserve entries full\n", __func__); 337 err = -EBUSY; 338 goto out; 339 } 340 if (!e->prsvd) { 341 int i; 342 struct cr_regs tmp; 343 344 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) 345 if (!iotlb_cr_valid(&tmp)) 346 break; 347 348 if (i == obj->nr_tlb_entries) { 349 dev_dbg(obj->dev, "%s: full: no entry\n", __func__); 350 err = -EBUSY; 351 goto out; 352 } 353 354 iotlb_lock_get(obj, &l); 355 } else { 356 l.vict = l.base; 357 iotlb_lock_set(obj, &l); 358 } 359 360 cr = iotlb_alloc_cr(obj, e); 361 if (IS_ERR(cr)) { 362 pm_runtime_put_sync(obj->dev); 363 return PTR_ERR(cr); 364 } 365 366 iotlb_load_cr(obj, cr); 367 kfree(cr); 368 369 if (e->prsvd) 370 l.base++; 371 /* increment victim for next tlb load */ 372 if (++l.vict == obj->nr_tlb_entries) 373 l.vict = l.base; 374 iotlb_lock_set(obj, &l); 375 out: 376 pm_runtime_put_sync(obj->dev); 377 return err; 378 } 379 380 #else /* !PREFETCH_IOTLB */ 381 382 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) 383 { 384 return 0; 385 } 386 387 #endif /* !PREFETCH_IOTLB */ 388 389 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) 390 { 391 return load_iotlb_entry(obj, e); 392 } 393 394 /** 395 * flush_iotlb_page - Clear an iommu tlb entry 396 * @obj: target iommu 397 * @da: iommu device virtual address 398 * 399 * Clear an iommu tlb entry which includes 'da' address. 400 **/ 401 static void flush_iotlb_page(struct omap_iommu *obj, u32 da) 402 { 403 int i; 404 struct cr_regs cr; 405 406 pm_runtime_get_sync(obj->dev); 407 408 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { 409 u32 start; 410 size_t bytes; 411 412 if (!iotlb_cr_valid(&cr)) 413 continue; 414 415 start = iotlb_cr_to_virt(&cr); 416 bytes = iopgsz_to_bytes(cr.cam & 3); 417 418 if ((start <= da) && (da < start + bytes)) { 419 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", 420 __func__, start, da, bytes); 421 iotlb_load_cr(obj, &cr); 422 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); 423 break; 424 } 425 } 426 pm_runtime_put_sync(obj->dev); 427 428 if (i == obj->nr_tlb_entries) 429 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); 430 } 431 432 /** 433 * flush_iotlb_all - Clear all iommu tlb entries 434 * @obj: target iommu 435 **/ 436 static void flush_iotlb_all(struct omap_iommu *obj) 437 { 438 struct iotlb_lock l; 439 440 pm_runtime_get_sync(obj->dev); 441 442 l.base = 0; 443 l.vict = 0; 444 iotlb_lock_set(obj, &l); 445 446 iommu_write_reg(obj, 1, MMU_GFLUSH); 447 448 pm_runtime_put_sync(obj->dev); 449 } 450 451 /* 452 * H/W pagetable operations 453 */ 454 static void flush_iopgd_range(u32 *first, u32 *last) 455 { 456 /* FIXME: L2 cache should be taken care of if it exists */ 457 do { 458 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" 459 : : "r" (first)); 460 first += L1_CACHE_BYTES / sizeof(*first); 461 } while (first <= last); 462 } 463 464 static void flush_iopte_range(u32 *first, u32 *last) 465 { 466 /* FIXME: L2 cache should be taken care of if it exists */ 467 do { 468 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" 469 : : "r" (first)); 470 first += L1_CACHE_BYTES / sizeof(*first); 471 } while (first <= last); 472 } 473 474 static void iopte_free(u32 *iopte) 475 { 476 /* Note: freed iopte's must be clean ready for re-use */ 477 if (iopte) 478 kmem_cache_free(iopte_cachep, iopte); 479 } 480 481 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) 482 { 483 u32 *iopte; 484 485 /* a table has already existed */ 486 if (*iopgd) 487 goto pte_ready; 488 489 /* 490 * do the allocation outside the page table lock 491 */ 492 spin_unlock(&obj->page_table_lock); 493 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); 494 spin_lock(&obj->page_table_lock); 495 496 if (!*iopgd) { 497 if (!iopte) 498 return ERR_PTR(-ENOMEM); 499 500 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; 501 flush_iopgd_range(iopgd, iopgd); 502 503 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); 504 } else { 505 /* We raced, free the reduniovant table */ 506 iopte_free(iopte); 507 } 508 509 pte_ready: 510 iopte = iopte_offset(iopgd, da); 511 512 dev_vdbg(obj->dev, 513 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", 514 __func__, da, iopgd, *iopgd, iopte, *iopte); 515 516 return iopte; 517 } 518 519 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) 520 { 521 u32 *iopgd = iopgd_offset(obj, da); 522 523 if ((da | pa) & ~IOSECTION_MASK) { 524 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", 525 __func__, da, pa, IOSECTION_SIZE); 526 return -EINVAL; 527 } 528 529 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; 530 flush_iopgd_range(iopgd, iopgd); 531 return 0; 532 } 533 534 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) 535 { 536 u32 *iopgd = iopgd_offset(obj, da); 537 int i; 538 539 if ((da | pa) & ~IOSUPER_MASK) { 540 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", 541 __func__, da, pa, IOSUPER_SIZE); 542 return -EINVAL; 543 } 544 545 for (i = 0; i < 16; i++) 546 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; 547 flush_iopgd_range(iopgd, iopgd + 15); 548 return 0; 549 } 550 551 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) 552 { 553 u32 *iopgd = iopgd_offset(obj, da); 554 u32 *iopte = iopte_alloc(obj, iopgd, da); 555 556 if (IS_ERR(iopte)) 557 return PTR_ERR(iopte); 558 559 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; 560 flush_iopte_range(iopte, iopte); 561 562 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", 563 __func__, da, pa, iopte, *iopte); 564 565 return 0; 566 } 567 568 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) 569 { 570 u32 *iopgd = iopgd_offset(obj, da); 571 u32 *iopte = iopte_alloc(obj, iopgd, da); 572 int i; 573 574 if ((da | pa) & ~IOLARGE_MASK) { 575 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", 576 __func__, da, pa, IOLARGE_SIZE); 577 return -EINVAL; 578 } 579 580 if (IS_ERR(iopte)) 581 return PTR_ERR(iopte); 582 583 for (i = 0; i < 16; i++) 584 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; 585 flush_iopte_range(iopte, iopte + 15); 586 return 0; 587 } 588 589 static int 590 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) 591 { 592 int (*fn)(struct omap_iommu *, u32, u32, u32); 593 u32 prot; 594 int err; 595 596 if (!obj || !e) 597 return -EINVAL; 598 599 switch (e->pgsz) { 600 case MMU_CAM_PGSZ_16M: 601 fn = iopgd_alloc_super; 602 break; 603 case MMU_CAM_PGSZ_1M: 604 fn = iopgd_alloc_section; 605 break; 606 case MMU_CAM_PGSZ_64K: 607 fn = iopte_alloc_large; 608 break; 609 case MMU_CAM_PGSZ_4K: 610 fn = iopte_alloc_page; 611 break; 612 default: 613 fn = NULL; 614 BUG(); 615 break; 616 } 617 618 prot = get_iopte_attr(e); 619 620 spin_lock(&obj->page_table_lock); 621 err = fn(obj, e->da, e->pa, prot); 622 spin_unlock(&obj->page_table_lock); 623 624 return err; 625 } 626 627 /** 628 * omap_iopgtable_store_entry - Make an iommu pte entry 629 * @obj: target iommu 630 * @e: an iommu tlb entry info 631 **/ 632 static int 633 omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) 634 { 635 int err; 636 637 flush_iotlb_page(obj, e->da); 638 err = iopgtable_store_entry_core(obj, e); 639 if (!err) 640 prefetch_iotlb_entry(obj, e); 641 return err; 642 } 643 644 /** 645 * iopgtable_lookup_entry - Lookup an iommu pte entry 646 * @obj: target iommu 647 * @da: iommu device virtual address 648 * @ppgd: iommu pgd entry pointer to be returned 649 * @ppte: iommu pte entry pointer to be returned 650 **/ 651 static void 652 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) 653 { 654 u32 *iopgd, *iopte = NULL; 655 656 iopgd = iopgd_offset(obj, da); 657 if (!*iopgd) 658 goto out; 659 660 if (iopgd_is_table(*iopgd)) 661 iopte = iopte_offset(iopgd, da); 662 out: 663 *ppgd = iopgd; 664 *ppte = iopte; 665 } 666 667 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) 668 { 669 size_t bytes; 670 u32 *iopgd = iopgd_offset(obj, da); 671 int nent = 1; 672 673 if (!*iopgd) 674 return 0; 675 676 if (iopgd_is_table(*iopgd)) { 677 int i; 678 u32 *iopte = iopte_offset(iopgd, da); 679 680 bytes = IOPTE_SIZE; 681 if (*iopte & IOPTE_LARGE) { 682 nent *= 16; 683 /* rewind to the 1st entry */ 684 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); 685 } 686 bytes *= nent; 687 memset(iopte, 0, nent * sizeof(*iopte)); 688 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); 689 690 /* 691 * do table walk to check if this table is necessary or not 692 */ 693 iopte = iopte_offset(iopgd, 0); 694 for (i = 0; i < PTRS_PER_IOPTE; i++) 695 if (iopte[i]) 696 goto out; 697 698 iopte_free(iopte); 699 nent = 1; /* for the next L1 entry */ 700 } else { 701 bytes = IOPGD_SIZE; 702 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { 703 nent *= 16; 704 /* rewind to the 1st entry */ 705 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); 706 } 707 bytes *= nent; 708 } 709 memset(iopgd, 0, nent * sizeof(*iopgd)); 710 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); 711 out: 712 return bytes; 713 } 714 715 /** 716 * iopgtable_clear_entry - Remove an iommu pte entry 717 * @obj: target iommu 718 * @da: iommu device virtual address 719 **/ 720 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) 721 { 722 size_t bytes; 723 724 spin_lock(&obj->page_table_lock); 725 726 bytes = iopgtable_clear_entry_core(obj, da); 727 flush_iotlb_page(obj, da); 728 729 spin_unlock(&obj->page_table_lock); 730 731 return bytes; 732 } 733 734 static void iopgtable_clear_entry_all(struct omap_iommu *obj) 735 { 736 int i; 737 738 spin_lock(&obj->page_table_lock); 739 740 for (i = 0; i < PTRS_PER_IOPGD; i++) { 741 u32 da; 742 u32 *iopgd; 743 744 da = i << IOPGD_SHIFT; 745 iopgd = iopgd_offset(obj, da); 746 747 if (!*iopgd) 748 continue; 749 750 if (iopgd_is_table(*iopgd)) 751 iopte_free(iopte_offset(iopgd, 0)); 752 753 *iopgd = 0; 754 flush_iopgd_range(iopgd, iopgd); 755 } 756 757 flush_iotlb_all(obj); 758 759 spin_unlock(&obj->page_table_lock); 760 } 761 762 /* 763 * Device IOMMU generic operations 764 */ 765 static irqreturn_t iommu_fault_handler(int irq, void *data) 766 { 767 u32 da, errs; 768 u32 *iopgd, *iopte; 769 struct omap_iommu *obj = data; 770 struct iommu_domain *domain = obj->domain; 771 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 772 773 if (!omap_domain->iommu_dev) 774 return IRQ_NONE; 775 776 errs = iommu_report_fault(obj, &da); 777 if (errs == 0) 778 return IRQ_HANDLED; 779 780 /* Fault callback or TLB/PTE Dynamic loading */ 781 if (!report_iommu_fault(domain, obj->dev, da, 0)) 782 return IRQ_HANDLED; 783 784 iommu_disable(obj); 785 786 iopgd = iopgd_offset(obj, da); 787 788 if (!iopgd_is_table(*iopgd)) { 789 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", 790 obj->name, errs, da, iopgd, *iopgd); 791 return IRQ_NONE; 792 } 793 794 iopte = iopte_offset(iopgd, da); 795 796 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", 797 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); 798 799 return IRQ_NONE; 800 } 801 802 static int device_match_by_alias(struct device *dev, void *data) 803 { 804 struct omap_iommu *obj = to_iommu(dev); 805 const char *name = data; 806 807 pr_debug("%s: %s %s\n", __func__, obj->name, name); 808 809 return strcmp(obj->name, name) == 0; 810 } 811 812 /** 813 * omap_iommu_attach() - attach iommu device to an iommu domain 814 * @name: name of target omap iommu device 815 * @iopgd: page table 816 **/ 817 static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) 818 { 819 int err; 820 struct device *dev; 821 struct omap_iommu *obj; 822 823 dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, 824 device_match_by_alias); 825 if (!dev) 826 return ERR_PTR(-ENODEV); 827 828 obj = to_iommu(dev); 829 830 spin_lock(&obj->iommu_lock); 831 832 obj->iopgd = iopgd; 833 err = iommu_enable(obj); 834 if (err) 835 goto err_enable; 836 flush_iotlb_all(obj); 837 838 spin_unlock(&obj->iommu_lock); 839 840 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); 841 return obj; 842 843 err_enable: 844 spin_unlock(&obj->iommu_lock); 845 return ERR_PTR(err); 846 } 847 848 /** 849 * omap_iommu_detach - release iommu device 850 * @obj: target iommu 851 **/ 852 static void omap_iommu_detach(struct omap_iommu *obj) 853 { 854 if (!obj || IS_ERR(obj)) 855 return; 856 857 spin_lock(&obj->iommu_lock); 858 859 iommu_disable(obj); 860 obj->iopgd = NULL; 861 862 spin_unlock(&obj->iommu_lock); 863 864 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); 865 } 866 867 /* 868 * OMAP Device MMU(IOMMU) detection 869 */ 870 static int omap_iommu_probe(struct platform_device *pdev) 871 { 872 int err = -ENODEV; 873 int irq; 874 struct omap_iommu *obj; 875 struct resource *res; 876 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); 877 struct device_node *of = pdev->dev.of_node; 878 879 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); 880 if (!obj) 881 return -ENOMEM; 882 883 if (of) { 884 obj->name = dev_name(&pdev->dev); 885 obj->nr_tlb_entries = 32; 886 err = of_property_read_u32(of, "ti,#tlb-entries", 887 &obj->nr_tlb_entries); 888 if (err && err != -EINVAL) 889 return err; 890 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) 891 return -EINVAL; 892 if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) 893 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; 894 } else { 895 obj->nr_tlb_entries = pdata->nr_tlb_entries; 896 obj->name = pdata->name; 897 } 898 899 obj->dev = &pdev->dev; 900 obj->ctx = (void *)obj + sizeof(*obj); 901 902 spin_lock_init(&obj->iommu_lock); 903 spin_lock_init(&obj->page_table_lock); 904 905 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 906 obj->regbase = devm_ioremap_resource(obj->dev, res); 907 if (IS_ERR(obj->regbase)) 908 return PTR_ERR(obj->regbase); 909 910 irq = platform_get_irq(pdev, 0); 911 if (irq < 0) 912 return -ENODEV; 913 914 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, 915 dev_name(obj->dev), obj); 916 if (err < 0) 917 return err; 918 platform_set_drvdata(pdev, obj); 919 920 pm_runtime_irq_safe(obj->dev); 921 pm_runtime_enable(obj->dev); 922 923 omap_iommu_debugfs_add(obj); 924 925 dev_info(&pdev->dev, "%s registered\n", obj->name); 926 return 0; 927 } 928 929 static int omap_iommu_remove(struct platform_device *pdev) 930 { 931 struct omap_iommu *obj = platform_get_drvdata(pdev); 932 933 iopgtable_clear_entry_all(obj); 934 omap_iommu_debugfs_remove(obj); 935 936 pm_runtime_disable(obj->dev); 937 938 dev_info(&pdev->dev, "%s removed\n", obj->name); 939 return 0; 940 } 941 942 static const struct of_device_id omap_iommu_of_match[] = { 943 { .compatible = "ti,omap2-iommu" }, 944 { .compatible = "ti,omap4-iommu" }, 945 { .compatible = "ti,dra7-iommu" }, 946 {}, 947 }; 948 949 static struct platform_driver omap_iommu_driver = { 950 .probe = omap_iommu_probe, 951 .remove = omap_iommu_remove, 952 .driver = { 953 .name = "omap-iommu", 954 .of_match_table = of_match_ptr(omap_iommu_of_match), 955 }, 956 }; 957 958 static void iopte_cachep_ctor(void *iopte) 959 { 960 clean_dcache_area(iopte, IOPTE_TABLE_SIZE); 961 } 962 963 static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz) 964 { 965 memset(e, 0, sizeof(*e)); 966 967 e->da = da; 968 e->pa = pa; 969 e->valid = MMU_CAM_V; 970 e->pgsz = pgsz; 971 e->endian = MMU_RAM_ENDIAN_LITTLE; 972 e->elsz = MMU_RAM_ELSZ_8; 973 e->mixed = 0; 974 975 return iopgsz_to_bytes(e->pgsz); 976 } 977 978 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, 979 phys_addr_t pa, size_t bytes, int prot) 980 { 981 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 982 struct omap_iommu *oiommu = omap_domain->iommu_dev; 983 struct device *dev = oiommu->dev; 984 struct iotlb_entry e; 985 int omap_pgsz; 986 u32 ret; 987 988 omap_pgsz = bytes_to_iopgsz(bytes); 989 if (omap_pgsz < 0) { 990 dev_err(dev, "invalid size to map: %d\n", bytes); 991 return -EINVAL; 992 } 993 994 dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes); 995 996 iotlb_init_entry(&e, da, pa, omap_pgsz); 997 998 ret = omap_iopgtable_store_entry(oiommu, &e); 999 if (ret) 1000 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); 1001 1002 return ret; 1003 } 1004 1005 static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, 1006 size_t size) 1007 { 1008 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1009 struct omap_iommu *oiommu = omap_domain->iommu_dev; 1010 struct device *dev = oiommu->dev; 1011 1012 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); 1013 1014 return iopgtable_clear_entry(oiommu, da); 1015 } 1016 1017 static int 1018 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) 1019 { 1020 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1021 struct omap_iommu *oiommu; 1022 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; 1023 int ret = 0; 1024 1025 if (!arch_data || !arch_data->name) { 1026 dev_err(dev, "device doesn't have an associated iommu\n"); 1027 return -EINVAL; 1028 } 1029 1030 spin_lock(&omap_domain->lock); 1031 1032 /* only a single device is supported per domain for now */ 1033 if (omap_domain->iommu_dev) { 1034 dev_err(dev, "iommu domain is already attached\n"); 1035 ret = -EBUSY; 1036 goto out; 1037 } 1038 1039 /* get a handle to and enable the omap iommu */ 1040 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); 1041 if (IS_ERR(oiommu)) { 1042 ret = PTR_ERR(oiommu); 1043 dev_err(dev, "can't get omap iommu: %d\n", ret); 1044 goto out; 1045 } 1046 1047 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; 1048 omap_domain->dev = dev; 1049 oiommu->domain = domain; 1050 1051 out: 1052 spin_unlock(&omap_domain->lock); 1053 return ret; 1054 } 1055 1056 static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, 1057 struct device *dev) 1058 { 1059 struct omap_iommu *oiommu = dev_to_omap_iommu(dev); 1060 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; 1061 1062 /* only a single device is supported per domain for now */ 1063 if (omap_domain->iommu_dev != oiommu) { 1064 dev_err(dev, "invalid iommu device\n"); 1065 return; 1066 } 1067 1068 iopgtable_clear_entry_all(oiommu); 1069 1070 omap_iommu_detach(oiommu); 1071 1072 omap_domain->iommu_dev = arch_data->iommu_dev = NULL; 1073 omap_domain->dev = NULL; 1074 oiommu->domain = NULL; 1075 } 1076 1077 static void omap_iommu_detach_dev(struct iommu_domain *domain, 1078 struct device *dev) 1079 { 1080 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1081 1082 spin_lock(&omap_domain->lock); 1083 _omap_iommu_detach_dev(omap_domain, dev); 1084 spin_unlock(&omap_domain->lock); 1085 } 1086 1087 static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) 1088 { 1089 struct omap_iommu_domain *omap_domain; 1090 1091 if (type != IOMMU_DOMAIN_UNMANAGED) 1092 return NULL; 1093 1094 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); 1095 if (!omap_domain) 1096 goto out; 1097 1098 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); 1099 if (!omap_domain->pgtable) 1100 goto fail_nomem; 1101 1102 /* 1103 * should never fail, but please keep this around to ensure 1104 * we keep the hardware happy 1105 */ 1106 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); 1107 1108 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); 1109 spin_lock_init(&omap_domain->lock); 1110 1111 omap_domain->domain.geometry.aperture_start = 0; 1112 omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1; 1113 omap_domain->domain.geometry.force_aperture = true; 1114 1115 return &omap_domain->domain; 1116 1117 fail_nomem: 1118 kfree(omap_domain); 1119 out: 1120 return NULL; 1121 } 1122 1123 static void omap_iommu_domain_free(struct iommu_domain *domain) 1124 { 1125 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1126 1127 /* 1128 * An iommu device is still attached 1129 * (currently, only one device can be attached) ? 1130 */ 1131 if (omap_domain->iommu_dev) 1132 _omap_iommu_detach_dev(omap_domain, omap_domain->dev); 1133 1134 kfree(omap_domain->pgtable); 1135 kfree(omap_domain); 1136 } 1137 1138 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, 1139 dma_addr_t da) 1140 { 1141 struct omap_iommu_domain *omap_domain = to_omap_domain(domain); 1142 struct omap_iommu *oiommu = omap_domain->iommu_dev; 1143 struct device *dev = oiommu->dev; 1144 u32 *pgd, *pte; 1145 phys_addr_t ret = 0; 1146 1147 iopgtable_lookup_entry(oiommu, da, &pgd, &pte); 1148 1149 if (pte) { 1150 if (iopte_is_small(*pte)) 1151 ret = omap_iommu_translate(*pte, da, IOPTE_MASK); 1152 else if (iopte_is_large(*pte)) 1153 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); 1154 else 1155 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, 1156 (unsigned long long)da); 1157 } else { 1158 if (iopgd_is_section(*pgd)) 1159 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); 1160 else if (iopgd_is_super(*pgd)) 1161 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); 1162 else 1163 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, 1164 (unsigned long long)da); 1165 } 1166 1167 return ret; 1168 } 1169 1170 static int omap_iommu_add_device(struct device *dev) 1171 { 1172 struct omap_iommu_arch_data *arch_data; 1173 struct device_node *np; 1174 struct platform_device *pdev; 1175 1176 /* 1177 * Allocate the archdata iommu structure for DT-based devices. 1178 * 1179 * TODO: Simplify this when removing non-DT support completely from the 1180 * IOMMU users. 1181 */ 1182 if (!dev->of_node) 1183 return 0; 1184 1185 np = of_parse_phandle(dev->of_node, "iommus", 0); 1186 if (!np) 1187 return 0; 1188 1189 pdev = of_find_device_by_node(np); 1190 if (WARN_ON(!pdev)) { 1191 of_node_put(np); 1192 return -EINVAL; 1193 } 1194 1195 arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL); 1196 if (!arch_data) { 1197 of_node_put(np); 1198 return -ENOMEM; 1199 } 1200 1201 arch_data->name = kstrdup(dev_name(&pdev->dev), GFP_KERNEL); 1202 dev->archdata.iommu = arch_data; 1203 1204 of_node_put(np); 1205 1206 return 0; 1207 } 1208 1209 static void omap_iommu_remove_device(struct device *dev) 1210 { 1211 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; 1212 1213 if (!dev->of_node || !arch_data) 1214 return; 1215 1216 kfree(arch_data->name); 1217 kfree(arch_data); 1218 } 1219 1220 static const struct iommu_ops omap_iommu_ops = { 1221 .domain_alloc = omap_iommu_domain_alloc, 1222 .domain_free = omap_iommu_domain_free, 1223 .attach_dev = omap_iommu_attach_dev, 1224 .detach_dev = omap_iommu_detach_dev, 1225 .map = omap_iommu_map, 1226 .unmap = omap_iommu_unmap, 1227 .map_sg = default_iommu_map_sg, 1228 .iova_to_phys = omap_iommu_iova_to_phys, 1229 .add_device = omap_iommu_add_device, 1230 .remove_device = omap_iommu_remove_device, 1231 .pgsize_bitmap = OMAP_IOMMU_PGSIZES, 1232 }; 1233 1234 static int __init omap_iommu_init(void) 1235 { 1236 struct kmem_cache *p; 1237 const unsigned long flags = SLAB_HWCACHE_ALIGN; 1238 size_t align = 1 << 10; /* L2 pagetable alignement */ 1239 struct device_node *np; 1240 1241 np = of_find_matching_node(NULL, omap_iommu_of_match); 1242 if (!np) 1243 return 0; 1244 1245 of_node_put(np); 1246 1247 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, 1248 iopte_cachep_ctor); 1249 if (!p) 1250 return -ENOMEM; 1251 iopte_cachep = p; 1252 1253 bus_set_iommu(&platform_bus_type, &omap_iommu_ops); 1254 1255 omap_iommu_debugfs_init(); 1256 1257 return platform_driver_register(&omap_iommu_driver); 1258 } 1259 subsys_initcall(omap_iommu_init); 1260 /* must be ready before omap3isp is probed */ 1261