1 /* 2 * Copyright (c) 2015-2016 MediaTek Inc. 3 * Author: Honghui Zhang <honghui.zhang@mediatek.com> 4 * 5 * Based on driver/iommu/mtk_iommu.c 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 #include <linux/bootmem.h> 17 #include <linux/bug.h> 18 #include <linux/clk.h> 19 #include <linux/component.h> 20 #include <linux/device.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/dma-iommu.h> 23 #include <linux/err.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/iommu.h> 27 #include <linux/iopoll.h> 28 #include <linux/list.h> 29 #include <linux/of_address.h> 30 #include <linux/of_iommu.h> 31 #include <linux/of_irq.h> 32 #include <linux/of_platform.h> 33 #include <linux/platform_device.h> 34 #include <linux/slab.h> 35 #include <linux/spinlock.h> 36 #include <asm/barrier.h> 37 #include <asm/dma-iommu.h> 38 #include <linux/module.h> 39 #include <dt-bindings/memory/mt2701-larb-port.h> 40 #include <soc/mediatek/smi.h> 41 #include "mtk_iommu.h" 42 43 #define REG_MMU_PT_BASE_ADDR 0x000 44 45 #define F_ALL_INVLD 0x2 46 #define F_MMU_INV_RANGE 0x1 47 #define F_INVLD_EN0 BIT(0) 48 #define F_INVLD_EN1 BIT(1) 49 50 #define F_MMU_FAULT_VA_MSK 0xfffff000 51 #define MTK_PROTECT_PA_ALIGN 128 52 53 #define REG_MMU_CTRL_REG 0x210 54 #define F_MMU_CTRL_COHERENT_EN BIT(8) 55 #define REG_MMU_IVRP_PADDR 0x214 56 #define REG_MMU_INT_CONTROL 0x220 57 #define F_INT_TRANSLATION_FAULT BIT(0) 58 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 59 #define F_INT_INVALID_PA_FAULT BIT(2) 60 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 61 #define F_INT_TABLE_WALK_FAULT BIT(4) 62 #define F_INT_TLB_MISS_FAULT BIT(5) 63 #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) 64 #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) 65 66 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) 67 #define F_INT_CLR_BIT BIT(12) 68 69 #define REG_MMU_FAULT_ST 0x224 70 #define REG_MMU_FAULT_VA 0x228 71 #define REG_MMU_INVLD_PA 0x22C 72 #define REG_MMU_INT_ID 0x388 73 #define REG_MMU_INVALIDATE 0x5c0 74 #define REG_MMU_INVLD_START_A 0x5c4 75 #define REG_MMU_INVLD_END_A 0x5c8 76 77 #define REG_MMU_INV_SEL 0x5d8 78 #define REG_MMU_STANDARD_AXI_MODE 0x5e8 79 80 #define REG_MMU_DCM 0x5f0 81 #define F_MMU_DCM_ON BIT(1) 82 #define REG_MMU_CPE_DONE 0x60c 83 #define F_DESC_VALID 0x2 84 #define F_DESC_NONSEC BIT(3) 85 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) 86 #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) 87 /* MTK generation one iommu HW only support 4K size mapping */ 88 #define MT2701_IOMMU_PAGE_SHIFT 12 89 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) 90 91 /* 92 * MTK m4u support 4GB iova address space, and only support 4K page 93 * mapping. So the pagetable size should be exactly as 4M. 94 */ 95 #define M2701_IOMMU_PGT_SIZE SZ_4M 96 97 struct mtk_iommu_domain { 98 spinlock_t pgtlock; /* lock for page table */ 99 struct iommu_domain domain; 100 u32 *pgt_va; 101 dma_addr_t pgt_pa; 102 struct mtk_iommu_data *data; 103 }; 104 105 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 106 { 107 return container_of(dom, struct mtk_iommu_domain, domain); 108 } 109 110 static const int mt2701_m4u_in_larb[] = { 111 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 112 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 113 }; 114 115 static inline int mt2701_m4u_to_larb(int id) 116 { 117 int i; 118 119 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) 120 if ((id) >= mt2701_m4u_in_larb[i]) 121 return i; 122 123 return 0; 124 } 125 126 static inline int mt2701_m4u_to_port(int id) 127 { 128 int larb = mt2701_m4u_to_larb(id); 129 130 return id - mt2701_m4u_in_larb[larb]; 131 } 132 133 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 134 { 135 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 136 data->base + REG_MMU_INV_SEL); 137 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 138 wmb(); /* Make sure the tlb flush all done */ 139 } 140 141 static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data, 142 unsigned long iova, size_t size) 143 { 144 int ret; 145 u32 tmp; 146 147 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 148 data->base + REG_MMU_INV_SEL); 149 writel_relaxed(iova & F_MMU_FAULT_VA_MSK, 150 data->base + REG_MMU_INVLD_START_A); 151 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, 152 data->base + REG_MMU_INVLD_END_A); 153 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); 154 155 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 156 tmp, tmp != 0, 10, 100000); 157 if (ret) { 158 dev_warn(data->dev, 159 "Partial TLB flush timed out, falling back to full flush\n"); 160 mtk_iommu_tlb_flush_all(data); 161 } 162 /* Clear the CPE status */ 163 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 164 } 165 166 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 167 { 168 struct mtk_iommu_data *data = dev_id; 169 struct mtk_iommu_domain *dom = data->m4u_dom; 170 u32 int_state, regval, fault_iova, fault_pa; 171 unsigned int fault_larb, fault_port; 172 173 /* Read error information from registers */ 174 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); 175 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 176 177 fault_iova &= F_MMU_FAULT_VA_MSK; 178 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 179 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 180 fault_larb = MT2701_M4U_TF_LARB(regval); 181 fault_port = MT2701_M4U_TF_PORT(regval); 182 183 /* 184 * MTK v1 iommu HW could not determine whether the fault is read or 185 * write fault, report as read fault. 186 */ 187 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 188 IOMMU_FAULT_READ)) 189 dev_err_ratelimited(data->dev, 190 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", 191 int_state, fault_iova, fault_pa, 192 fault_larb, fault_port); 193 194 /* Interrupt clear */ 195 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); 196 regval |= F_INT_CLR_BIT; 197 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 198 199 mtk_iommu_tlb_flush_all(data); 200 201 return IRQ_HANDLED; 202 } 203 204 static void mtk_iommu_config(struct mtk_iommu_data *data, 205 struct device *dev, bool enable) 206 { 207 struct mtk_smi_larb_iommu *larb_mmu; 208 unsigned int larbid, portid; 209 struct iommu_fwspec *fwspec = dev->iommu_fwspec; 210 int i; 211 212 for (i = 0; i < fwspec->num_ids; ++i) { 213 larbid = mt2701_m4u_to_larb(fwspec->ids[i]); 214 portid = mt2701_m4u_to_port(fwspec->ids[i]); 215 larb_mmu = &data->smi_imu.larb_imu[larbid]; 216 217 dev_dbg(dev, "%s iommu port: %d\n", 218 enable ? "enable" : "disable", portid); 219 220 if (enable) 221 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 222 else 223 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 224 } 225 } 226 227 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data) 228 { 229 struct mtk_iommu_domain *dom = data->m4u_dom; 230 231 spin_lock_init(&dom->pgtlock); 232 233 dom->pgt_va = dma_zalloc_coherent(data->dev, 234 M2701_IOMMU_PGT_SIZE, 235 &dom->pgt_pa, GFP_KERNEL); 236 if (!dom->pgt_va) 237 return -ENOMEM; 238 239 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); 240 241 dom->data = data; 242 243 return 0; 244 } 245 246 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 247 { 248 struct mtk_iommu_domain *dom; 249 250 if (type != IOMMU_DOMAIN_UNMANAGED) 251 return NULL; 252 253 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 254 if (!dom) 255 return NULL; 256 257 return &dom->domain; 258 } 259 260 static void mtk_iommu_domain_free(struct iommu_domain *domain) 261 { 262 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 263 struct mtk_iommu_data *data = dom->data; 264 265 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 266 dom->pgt_va, dom->pgt_pa); 267 kfree(to_mtk_domain(domain)); 268 } 269 270 static int mtk_iommu_attach_device(struct iommu_domain *domain, 271 struct device *dev) 272 { 273 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 274 struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; 275 int ret; 276 277 if (!data) 278 return -ENODEV; 279 280 if (!data->m4u_dom) { 281 data->m4u_dom = dom; 282 ret = mtk_iommu_domain_finalise(data); 283 if (ret) { 284 data->m4u_dom = NULL; 285 return ret; 286 } 287 } 288 289 mtk_iommu_config(data, dev, true); 290 return 0; 291 } 292 293 static void mtk_iommu_detach_device(struct iommu_domain *domain, 294 struct device *dev) 295 { 296 struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; 297 298 if (!data) 299 return; 300 301 mtk_iommu_config(data, dev, false); 302 } 303 304 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 305 phys_addr_t paddr, size_t size, int prot) 306 { 307 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 308 unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 309 unsigned long flags; 310 unsigned int i; 311 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 312 u32 pabase = (u32)paddr; 313 int map_size = 0; 314 315 spin_lock_irqsave(&dom->pgtlock, flags); 316 for (i = 0; i < page_num; i++) { 317 if (pgt_base_iova[i]) { 318 memset(pgt_base_iova, 0, i * sizeof(u32)); 319 break; 320 } 321 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; 322 pabase += MT2701_IOMMU_PAGE_SIZE; 323 map_size += MT2701_IOMMU_PAGE_SIZE; 324 } 325 326 spin_unlock_irqrestore(&dom->pgtlock, flags); 327 328 mtk_iommu_tlb_flush_range(dom->data, iova, size); 329 330 return map_size == size ? 0 : -EEXIST; 331 } 332 333 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 334 unsigned long iova, size_t size) 335 { 336 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 337 unsigned long flags; 338 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 339 unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 340 341 spin_lock_irqsave(&dom->pgtlock, flags); 342 memset(pgt_base_iova, 0, page_num * sizeof(u32)); 343 spin_unlock_irqrestore(&dom->pgtlock, flags); 344 345 mtk_iommu_tlb_flush_range(dom->data, iova, size); 346 347 return size; 348 } 349 350 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 351 dma_addr_t iova) 352 { 353 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 354 unsigned long flags; 355 phys_addr_t pa; 356 357 spin_lock_irqsave(&dom->pgtlock, flags); 358 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); 359 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); 360 spin_unlock_irqrestore(&dom->pgtlock, flags); 361 362 return pa; 363 } 364 365 static struct iommu_ops mtk_iommu_ops; 366 367 /* 368 * MTK generation one iommu HW only support one iommu domain, and all the client 369 * sharing the same iova address space. 370 */ 371 static int mtk_iommu_create_mapping(struct device *dev, 372 struct of_phandle_args *args) 373 { 374 struct mtk_iommu_data *data; 375 struct platform_device *m4updev; 376 struct dma_iommu_mapping *mtk_mapping; 377 struct device *m4udev; 378 int ret; 379 380 if (args->args_count != 1) { 381 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 382 args->args_count); 383 return -EINVAL; 384 } 385 386 if (!dev->iommu_fwspec) { 387 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops); 388 if (ret) 389 return ret; 390 } else if (dev->iommu_fwspec->ops != &mtk_iommu_ops) { 391 return -EINVAL; 392 } 393 394 if (!dev->iommu_fwspec->iommu_priv) { 395 /* Get the m4u device */ 396 m4updev = of_find_device_by_node(args->np); 397 if (WARN_ON(!m4updev)) 398 return -EINVAL; 399 400 dev->iommu_fwspec->iommu_priv = platform_get_drvdata(m4updev); 401 } 402 403 ret = iommu_fwspec_add_ids(dev, args->args, 1); 404 if (ret) 405 return ret; 406 407 data = dev->iommu_fwspec->iommu_priv; 408 m4udev = data->dev; 409 mtk_mapping = m4udev->archdata.iommu; 410 if (!mtk_mapping) { 411 /* MTK iommu support 4GB iova address space. */ 412 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, 413 0, 1ULL << 32); 414 if (IS_ERR(mtk_mapping)) 415 return PTR_ERR(mtk_mapping); 416 417 m4udev->archdata.iommu = mtk_mapping; 418 } 419 420 return 0; 421 } 422 423 static int mtk_iommu_add_device(struct device *dev) 424 { 425 struct dma_iommu_mapping *mtk_mapping; 426 struct of_phandle_args iommu_spec; 427 struct of_phandle_iterator it; 428 struct mtk_iommu_data *data; 429 struct iommu_group *group; 430 int err; 431 432 of_for_each_phandle(&it, err, dev->of_node, "iommus", 433 "#iommu-cells", 0) { 434 int count = of_phandle_iterator_args(&it, iommu_spec.args, 435 MAX_PHANDLE_ARGS); 436 iommu_spec.np = of_node_get(it.node); 437 iommu_spec.args_count = count; 438 439 mtk_iommu_create_mapping(dev, &iommu_spec); 440 of_node_put(iommu_spec.np); 441 } 442 443 if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops) 444 return -ENODEV; /* Not a iommu client device */ 445 446 /* 447 * This is a short-term bodge because the ARM DMA code doesn't 448 * understand multi-device groups, but we have to call into it 449 * successfully (and not just rely on a normal IOMMU API attach 450 * here) in order to set the correct DMA API ops on @dev. 451 */ 452 group = iommu_group_alloc(); 453 if (IS_ERR(group)) 454 return PTR_ERR(group); 455 456 err = iommu_group_add_device(group, dev); 457 iommu_group_put(group); 458 if (err) 459 return err; 460 461 data = dev->iommu_fwspec->iommu_priv; 462 mtk_mapping = data->dev->archdata.iommu; 463 err = arm_iommu_attach_device(dev, mtk_mapping); 464 if (err) { 465 iommu_group_remove_device(dev); 466 return err; 467 } 468 469 return iommu_device_link(&data->iommu, dev);; 470 } 471 472 static void mtk_iommu_remove_device(struct device *dev) 473 { 474 struct mtk_iommu_data *data; 475 476 if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops) 477 return; 478 479 data = dev->iommu_fwspec->iommu_priv; 480 iommu_device_unlink(&data->iommu, dev); 481 482 iommu_group_remove_device(dev); 483 iommu_fwspec_free(dev); 484 } 485 486 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 487 { 488 u32 regval; 489 int ret; 490 491 ret = clk_prepare_enable(data->bclk); 492 if (ret) { 493 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 494 return ret; 495 } 496 497 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); 498 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 499 500 regval = F_INT_TRANSLATION_FAULT | 501 F_INT_MAIN_MULTI_HIT_FAULT | 502 F_INT_INVALID_PA_FAULT | 503 F_INT_ENTRY_REPLACEMENT_FAULT | 504 F_INT_TABLE_WALK_FAULT | 505 F_INT_TLB_MISS_FAULT | 506 F_INT_PFH_DMA_FIFO_OVERFLOW | 507 F_INT_MISS_DMA_FIFO_OVERFLOW; 508 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 509 510 /* protect memory,hw will write here while translation fault */ 511 writel_relaxed(data->protect_base, 512 data->base + REG_MMU_IVRP_PADDR); 513 514 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); 515 516 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 517 dev_name(data->dev), (void *)data)) { 518 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 519 clk_disable_unprepare(data->bclk); 520 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 521 return -ENODEV; 522 } 523 524 return 0; 525 } 526 527 static struct iommu_ops mtk_iommu_ops = { 528 .domain_alloc = mtk_iommu_domain_alloc, 529 .domain_free = mtk_iommu_domain_free, 530 .attach_dev = mtk_iommu_attach_device, 531 .detach_dev = mtk_iommu_detach_device, 532 .map = mtk_iommu_map, 533 .unmap = mtk_iommu_unmap, 534 .map_sg = default_iommu_map_sg, 535 .iova_to_phys = mtk_iommu_iova_to_phys, 536 .add_device = mtk_iommu_add_device, 537 .remove_device = mtk_iommu_remove_device, 538 .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT, 539 }; 540 541 static const struct of_device_id mtk_iommu_of_ids[] = { 542 { .compatible = "mediatek,mt2701-m4u", }, 543 {} 544 }; 545 546 static const struct component_master_ops mtk_iommu_com_ops = { 547 .bind = mtk_iommu_bind, 548 .unbind = mtk_iommu_unbind, 549 }; 550 551 static int mtk_iommu_probe(struct platform_device *pdev) 552 { 553 struct mtk_iommu_data *data; 554 struct device *dev = &pdev->dev; 555 struct resource *res; 556 struct component_match *match = NULL; 557 struct of_phandle_args larb_spec; 558 struct of_phandle_iterator it; 559 void *protect; 560 int larb_nr, ret, err; 561 562 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 563 if (!data) 564 return -ENOMEM; 565 566 data->dev = dev; 567 568 /* Protect memory. HW will access here while translation fault.*/ 569 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, 570 GFP_KERNEL | GFP_DMA); 571 if (!protect) 572 return -ENOMEM; 573 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 574 575 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 576 data->base = devm_ioremap_resource(dev, res); 577 if (IS_ERR(data->base)) 578 return PTR_ERR(data->base); 579 580 data->irq = platform_get_irq(pdev, 0); 581 if (data->irq < 0) 582 return data->irq; 583 584 data->bclk = devm_clk_get(dev, "bclk"); 585 if (IS_ERR(data->bclk)) 586 return PTR_ERR(data->bclk); 587 588 larb_nr = 0; 589 of_for_each_phandle(&it, err, dev->of_node, 590 "mediatek,larbs", NULL, 0) { 591 struct platform_device *plarbdev; 592 int count = of_phandle_iterator_args(&it, larb_spec.args, 593 MAX_PHANDLE_ARGS); 594 595 if (count) 596 continue; 597 598 larb_spec.np = of_node_get(it.node); 599 if (!of_device_is_available(larb_spec.np)) 600 continue; 601 602 plarbdev = of_find_device_by_node(larb_spec.np); 603 if (!plarbdev) { 604 plarbdev = of_platform_device_create( 605 larb_spec.np, NULL, 606 platform_bus_type.dev_root); 607 if (!plarbdev) { 608 of_node_put(larb_spec.np); 609 return -EPROBE_DEFER; 610 } 611 } 612 613 data->smi_imu.larb_imu[larb_nr].dev = &plarbdev->dev; 614 component_match_add_release(dev, &match, release_of, 615 compare_of, larb_spec.np); 616 larb_nr++; 617 } 618 619 data->smi_imu.larb_nr = larb_nr; 620 621 platform_set_drvdata(pdev, data); 622 623 ret = mtk_iommu_hw_init(data); 624 if (ret) 625 return ret; 626 627 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 628 dev_name(&pdev->dev)); 629 if (ret) 630 return ret; 631 632 iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); 633 634 ret = iommu_device_register(&data->iommu); 635 if (ret) 636 return ret; 637 638 if (!iommu_present(&platform_bus_type)) 639 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 640 641 return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 642 } 643 644 static int mtk_iommu_remove(struct platform_device *pdev) 645 { 646 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 647 648 iommu_device_sysfs_remove(&data->iommu); 649 iommu_device_unregister(&data->iommu); 650 651 if (iommu_present(&platform_bus_type)) 652 bus_set_iommu(&platform_bus_type, NULL); 653 654 clk_disable_unprepare(data->bclk); 655 devm_free_irq(&pdev->dev, data->irq, data); 656 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 657 return 0; 658 } 659 660 static int __maybe_unused mtk_iommu_suspend(struct device *dev) 661 { 662 struct mtk_iommu_data *data = dev_get_drvdata(dev); 663 struct mtk_iommu_suspend_reg *reg = &data->reg; 664 void __iomem *base = data->base; 665 666 reg->standard_axi_mode = readl_relaxed(base + 667 REG_MMU_STANDARD_AXI_MODE); 668 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); 669 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 670 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); 671 return 0; 672 } 673 674 static int __maybe_unused mtk_iommu_resume(struct device *dev) 675 { 676 struct mtk_iommu_data *data = dev_get_drvdata(dev); 677 struct mtk_iommu_suspend_reg *reg = &data->reg; 678 void __iomem *base = data->base; 679 680 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); 681 writel_relaxed(reg->standard_axi_mode, 682 base + REG_MMU_STANDARD_AXI_MODE); 683 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); 684 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 685 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); 686 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); 687 return 0; 688 } 689 690 static const struct dev_pm_ops mtk_iommu_pm_ops = { 691 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) 692 }; 693 694 static struct platform_driver mtk_iommu_driver = { 695 .probe = mtk_iommu_probe, 696 .remove = mtk_iommu_remove, 697 .driver = { 698 .name = "mtk-iommu-v1", 699 .of_match_table = mtk_iommu_of_ids, 700 .pm = &mtk_iommu_pm_ops, 701 } 702 }; 703 704 static int __init m4u_init(void) 705 { 706 return platform_driver_register(&mtk_iommu_driver); 707 } 708 709 static void __exit m4u_exit(void) 710 { 711 return platform_driver_unregister(&mtk_iommu_driver); 712 } 713 714 subsys_initcall(m4u_init); 715 module_exit(m4u_exit); 716 717 MODULE_DESCRIPTION("IOMMU API for MTK architected m4u v1 implementations"); 718 MODULE_AUTHOR("Honghui Zhang <honghui.zhang@mediatek.com>"); 719 MODULE_LICENSE("GPL v2"); 720