1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IOMMU API for MTK architected m4u v1 implementations 4 * 5 * Copyright (c) 2015-2016 MediaTek Inc. 6 * Author: Honghui Zhang <honghui.zhang@mediatek.com> 7 * 8 * Based on driver/iommu/mtk_iommu.c 9 */ 10 #include <linux/memblock.h> 11 #include <linux/bug.h> 12 #include <linux/clk.h> 13 #include <linux/component.h> 14 #include <linux/device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/dma-iommu.h> 17 #include <linux/err.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/iommu.h> 21 #include <linux/iopoll.h> 22 #include <linux/list.h> 23 #include <linux/of_address.h> 24 #include <linux/of_iommu.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_device.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <asm/barrier.h> 31 #include <asm/dma-iommu.h> 32 #include <linux/init.h> 33 #include <dt-bindings/memory/mt2701-larb-port.h> 34 #include <soc/mediatek/smi.h> 35 #include "mtk_iommu.h" 36 37 #define REG_MMU_PT_BASE_ADDR 0x000 38 39 #define F_ALL_INVLD 0x2 40 #define F_MMU_INV_RANGE 0x1 41 #define F_INVLD_EN0 BIT(0) 42 #define F_INVLD_EN1 BIT(1) 43 44 #define F_MMU_FAULT_VA_MSK 0xfffff000 45 #define MTK_PROTECT_PA_ALIGN 128 46 47 #define REG_MMU_CTRL_REG 0x210 48 #define F_MMU_CTRL_COHERENT_EN BIT(8) 49 #define REG_MMU_IVRP_PADDR 0x214 50 #define REG_MMU_INT_CONTROL 0x220 51 #define F_INT_TRANSLATION_FAULT BIT(0) 52 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 53 #define F_INT_INVALID_PA_FAULT BIT(2) 54 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 55 #define F_INT_TABLE_WALK_FAULT BIT(4) 56 #define F_INT_TLB_MISS_FAULT BIT(5) 57 #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) 58 #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) 59 60 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) 61 #define F_INT_CLR_BIT BIT(12) 62 63 #define REG_MMU_FAULT_ST 0x224 64 #define REG_MMU_FAULT_VA 0x228 65 #define REG_MMU_INVLD_PA 0x22C 66 #define REG_MMU_INT_ID 0x388 67 #define REG_MMU_INVALIDATE 0x5c0 68 #define REG_MMU_INVLD_START_A 0x5c4 69 #define REG_MMU_INVLD_END_A 0x5c8 70 71 #define REG_MMU_INV_SEL 0x5d8 72 #define REG_MMU_STANDARD_AXI_MODE 0x5e8 73 74 #define REG_MMU_DCM 0x5f0 75 #define F_MMU_DCM_ON BIT(1) 76 #define REG_MMU_CPE_DONE 0x60c 77 #define F_DESC_VALID 0x2 78 #define F_DESC_NONSEC BIT(3) 79 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) 80 #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) 81 /* MTK generation one iommu HW only support 4K size mapping */ 82 #define MT2701_IOMMU_PAGE_SHIFT 12 83 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) 84 85 /* 86 * MTK m4u support 4GB iova address space, and only support 4K page 87 * mapping. So the pagetable size should be exactly as 4M. 88 */ 89 #define M2701_IOMMU_PGT_SIZE SZ_4M 90 91 struct mtk_iommu_domain { 92 spinlock_t pgtlock; /* lock for page table */ 93 struct iommu_domain domain; 94 u32 *pgt_va; 95 dma_addr_t pgt_pa; 96 struct mtk_iommu_data *data; 97 }; 98 99 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 100 { 101 return container_of(dom, struct mtk_iommu_domain, domain); 102 } 103 104 static const int mt2701_m4u_in_larb[] = { 105 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 106 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 107 }; 108 109 static inline int mt2701_m4u_to_larb(int id) 110 { 111 int i; 112 113 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) 114 if ((id) >= mt2701_m4u_in_larb[i]) 115 return i; 116 117 return 0; 118 } 119 120 static inline int mt2701_m4u_to_port(int id) 121 { 122 int larb = mt2701_m4u_to_larb(id); 123 124 return id - mt2701_m4u_in_larb[larb]; 125 } 126 127 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 128 { 129 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 130 data->base + REG_MMU_INV_SEL); 131 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 132 wmb(); /* Make sure the tlb flush all done */ 133 } 134 135 static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data, 136 unsigned long iova, size_t size) 137 { 138 int ret; 139 u32 tmp; 140 141 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 142 data->base + REG_MMU_INV_SEL); 143 writel_relaxed(iova & F_MMU_FAULT_VA_MSK, 144 data->base + REG_MMU_INVLD_START_A); 145 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, 146 data->base + REG_MMU_INVLD_END_A); 147 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); 148 149 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 150 tmp, tmp != 0, 10, 100000); 151 if (ret) { 152 dev_warn(data->dev, 153 "Partial TLB flush timed out, falling back to full flush\n"); 154 mtk_iommu_tlb_flush_all(data); 155 } 156 /* Clear the CPE status */ 157 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 158 } 159 160 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 161 { 162 struct mtk_iommu_data *data = dev_id; 163 struct mtk_iommu_domain *dom = data->m4u_dom; 164 u32 int_state, regval, fault_iova, fault_pa; 165 unsigned int fault_larb, fault_port; 166 167 /* Read error information from registers */ 168 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); 169 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 170 171 fault_iova &= F_MMU_FAULT_VA_MSK; 172 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 173 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 174 fault_larb = MT2701_M4U_TF_LARB(regval); 175 fault_port = MT2701_M4U_TF_PORT(regval); 176 177 /* 178 * MTK v1 iommu HW could not determine whether the fault is read or 179 * write fault, report as read fault. 180 */ 181 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 182 IOMMU_FAULT_READ)) 183 dev_err_ratelimited(data->dev, 184 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", 185 int_state, fault_iova, fault_pa, 186 fault_larb, fault_port); 187 188 /* Interrupt clear */ 189 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); 190 regval |= F_INT_CLR_BIT; 191 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 192 193 mtk_iommu_tlb_flush_all(data); 194 195 return IRQ_HANDLED; 196 } 197 198 static void mtk_iommu_config(struct mtk_iommu_data *data, 199 struct device *dev, bool enable) 200 { 201 struct mtk_smi_larb_iommu *larb_mmu; 202 unsigned int larbid, portid; 203 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 204 int i; 205 206 for (i = 0; i < fwspec->num_ids; ++i) { 207 larbid = mt2701_m4u_to_larb(fwspec->ids[i]); 208 portid = mt2701_m4u_to_port(fwspec->ids[i]); 209 larb_mmu = &data->smi_imu.larb_imu[larbid]; 210 211 dev_dbg(dev, "%s iommu port: %d\n", 212 enable ? "enable" : "disable", portid); 213 214 if (enable) 215 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 216 else 217 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 218 } 219 } 220 221 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data) 222 { 223 struct mtk_iommu_domain *dom = data->m4u_dom; 224 225 spin_lock_init(&dom->pgtlock); 226 227 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 228 &dom->pgt_pa, GFP_KERNEL); 229 if (!dom->pgt_va) 230 return -ENOMEM; 231 232 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); 233 234 dom->data = data; 235 236 return 0; 237 } 238 239 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 240 { 241 struct mtk_iommu_domain *dom; 242 243 if (type != IOMMU_DOMAIN_UNMANAGED) 244 return NULL; 245 246 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 247 if (!dom) 248 return NULL; 249 250 return &dom->domain; 251 } 252 253 static void mtk_iommu_domain_free(struct iommu_domain *domain) 254 { 255 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 256 struct mtk_iommu_data *data = dom->data; 257 258 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 259 dom->pgt_va, dom->pgt_pa); 260 kfree(to_mtk_domain(domain)); 261 } 262 263 static int mtk_iommu_attach_device(struct iommu_domain *domain, 264 struct device *dev) 265 { 266 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 267 struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv; 268 int ret; 269 270 if (!data) 271 return -ENODEV; 272 273 if (!data->m4u_dom) { 274 data->m4u_dom = dom; 275 ret = mtk_iommu_domain_finalise(data); 276 if (ret) { 277 data->m4u_dom = NULL; 278 return ret; 279 } 280 } 281 282 mtk_iommu_config(data, dev, true); 283 return 0; 284 } 285 286 static void mtk_iommu_detach_device(struct iommu_domain *domain, 287 struct device *dev) 288 { 289 struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv; 290 291 if (!data) 292 return; 293 294 mtk_iommu_config(data, dev, false); 295 } 296 297 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 298 phys_addr_t paddr, size_t size, int prot) 299 { 300 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 301 unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 302 unsigned long flags; 303 unsigned int i; 304 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 305 u32 pabase = (u32)paddr; 306 int map_size = 0; 307 308 spin_lock_irqsave(&dom->pgtlock, flags); 309 for (i = 0; i < page_num; i++) { 310 if (pgt_base_iova[i]) { 311 memset(pgt_base_iova, 0, i * sizeof(u32)); 312 break; 313 } 314 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; 315 pabase += MT2701_IOMMU_PAGE_SIZE; 316 map_size += MT2701_IOMMU_PAGE_SIZE; 317 } 318 319 spin_unlock_irqrestore(&dom->pgtlock, flags); 320 321 mtk_iommu_tlb_flush_range(dom->data, iova, size); 322 323 return map_size == size ? 0 : -EEXIST; 324 } 325 326 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 327 unsigned long iova, size_t size) 328 { 329 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 330 unsigned long flags; 331 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 332 unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 333 334 spin_lock_irqsave(&dom->pgtlock, flags); 335 memset(pgt_base_iova, 0, page_num * sizeof(u32)); 336 spin_unlock_irqrestore(&dom->pgtlock, flags); 337 338 mtk_iommu_tlb_flush_range(dom->data, iova, size); 339 340 return size; 341 } 342 343 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 344 dma_addr_t iova) 345 { 346 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 347 unsigned long flags; 348 phys_addr_t pa; 349 350 spin_lock_irqsave(&dom->pgtlock, flags); 351 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); 352 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); 353 spin_unlock_irqrestore(&dom->pgtlock, flags); 354 355 return pa; 356 } 357 358 static const struct iommu_ops mtk_iommu_ops; 359 360 /* 361 * MTK generation one iommu HW only support one iommu domain, and all the client 362 * sharing the same iova address space. 363 */ 364 static int mtk_iommu_create_mapping(struct device *dev, 365 struct of_phandle_args *args) 366 { 367 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 368 struct mtk_iommu_data *data; 369 struct platform_device *m4updev; 370 struct dma_iommu_mapping *mtk_mapping; 371 struct device *m4udev; 372 int ret; 373 374 if (args->args_count != 1) { 375 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 376 args->args_count); 377 return -EINVAL; 378 } 379 380 if (!fwspec) { 381 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops); 382 if (ret) 383 return ret; 384 fwspec = dev_iommu_fwspec_get(dev); 385 } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) { 386 return -EINVAL; 387 } 388 389 if (!fwspec->iommu_priv) { 390 /* Get the m4u device */ 391 m4updev = of_find_device_by_node(args->np); 392 if (WARN_ON(!m4updev)) 393 return -EINVAL; 394 395 fwspec->iommu_priv = platform_get_drvdata(m4updev); 396 } 397 398 ret = iommu_fwspec_add_ids(dev, args->args, 1); 399 if (ret) 400 return ret; 401 402 data = fwspec->iommu_priv; 403 m4udev = data->dev; 404 mtk_mapping = m4udev->archdata.iommu; 405 if (!mtk_mapping) { 406 /* MTK iommu support 4GB iova address space. */ 407 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, 408 0, 1ULL << 32); 409 if (IS_ERR(mtk_mapping)) 410 return PTR_ERR(mtk_mapping); 411 412 m4udev->archdata.iommu = mtk_mapping; 413 } 414 415 return 0; 416 } 417 418 static int mtk_iommu_add_device(struct device *dev) 419 { 420 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 421 struct dma_iommu_mapping *mtk_mapping; 422 struct of_phandle_args iommu_spec; 423 struct of_phandle_iterator it; 424 struct mtk_iommu_data *data; 425 struct iommu_group *group; 426 int err; 427 428 of_for_each_phandle(&it, err, dev->of_node, "iommus", 429 "#iommu-cells", 0) { 430 int count = of_phandle_iterator_args(&it, iommu_spec.args, 431 MAX_PHANDLE_ARGS); 432 iommu_spec.np = of_node_get(it.node); 433 iommu_spec.args_count = count; 434 435 mtk_iommu_create_mapping(dev, &iommu_spec); 436 437 /* dev->iommu_fwspec might have changed */ 438 fwspec = dev_iommu_fwspec_get(dev); 439 440 of_node_put(iommu_spec.np); 441 } 442 443 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 444 return -ENODEV; /* Not a iommu client device */ 445 446 /* 447 * This is a short-term bodge because the ARM DMA code doesn't 448 * understand multi-device groups, but we have to call into it 449 * successfully (and not just rely on a normal IOMMU API attach 450 * here) in order to set the correct DMA API ops on @dev. 451 */ 452 group = iommu_group_alloc(); 453 if (IS_ERR(group)) 454 return PTR_ERR(group); 455 456 err = iommu_group_add_device(group, dev); 457 iommu_group_put(group); 458 if (err) 459 return err; 460 461 data = fwspec->iommu_priv; 462 mtk_mapping = data->dev->archdata.iommu; 463 err = arm_iommu_attach_device(dev, mtk_mapping); 464 if (err) { 465 iommu_group_remove_device(dev); 466 return err; 467 } 468 469 return iommu_device_link(&data->iommu, dev); 470 } 471 472 static void mtk_iommu_remove_device(struct device *dev) 473 { 474 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 475 struct mtk_iommu_data *data; 476 477 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 478 return; 479 480 data = fwspec->iommu_priv; 481 iommu_device_unlink(&data->iommu, dev); 482 483 iommu_group_remove_device(dev); 484 iommu_fwspec_free(dev); 485 } 486 487 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 488 { 489 u32 regval; 490 int ret; 491 492 ret = clk_prepare_enable(data->bclk); 493 if (ret) { 494 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 495 return ret; 496 } 497 498 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); 499 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 500 501 regval = F_INT_TRANSLATION_FAULT | 502 F_INT_MAIN_MULTI_HIT_FAULT | 503 F_INT_INVALID_PA_FAULT | 504 F_INT_ENTRY_REPLACEMENT_FAULT | 505 F_INT_TABLE_WALK_FAULT | 506 F_INT_TLB_MISS_FAULT | 507 F_INT_PFH_DMA_FIFO_OVERFLOW | 508 F_INT_MISS_DMA_FIFO_OVERFLOW; 509 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 510 511 /* protect memory,hw will write here while translation fault */ 512 writel_relaxed(data->protect_base, 513 data->base + REG_MMU_IVRP_PADDR); 514 515 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); 516 517 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 518 dev_name(data->dev), (void *)data)) { 519 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 520 clk_disable_unprepare(data->bclk); 521 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 522 return -ENODEV; 523 } 524 525 return 0; 526 } 527 528 static const struct iommu_ops mtk_iommu_ops = { 529 .domain_alloc = mtk_iommu_domain_alloc, 530 .domain_free = mtk_iommu_domain_free, 531 .attach_dev = mtk_iommu_attach_device, 532 .detach_dev = mtk_iommu_detach_device, 533 .map = mtk_iommu_map, 534 .unmap = mtk_iommu_unmap, 535 .iova_to_phys = mtk_iommu_iova_to_phys, 536 .add_device = mtk_iommu_add_device, 537 .remove_device = mtk_iommu_remove_device, 538 .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT, 539 }; 540 541 static const struct of_device_id mtk_iommu_of_ids[] = { 542 { .compatible = "mediatek,mt2701-m4u", }, 543 {} 544 }; 545 546 static const struct component_master_ops mtk_iommu_com_ops = { 547 .bind = mtk_iommu_bind, 548 .unbind = mtk_iommu_unbind, 549 }; 550 551 static int mtk_iommu_probe(struct platform_device *pdev) 552 { 553 struct mtk_iommu_data *data; 554 struct device *dev = &pdev->dev; 555 struct resource *res; 556 struct component_match *match = NULL; 557 struct of_phandle_args larb_spec; 558 struct of_phandle_iterator it; 559 void *protect; 560 int larb_nr, ret, err; 561 562 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 563 if (!data) 564 return -ENOMEM; 565 566 data->dev = dev; 567 568 /* Protect memory. HW will access here while translation fault.*/ 569 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, 570 GFP_KERNEL | GFP_DMA); 571 if (!protect) 572 return -ENOMEM; 573 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 574 575 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 576 data->base = devm_ioremap_resource(dev, res); 577 if (IS_ERR(data->base)) 578 return PTR_ERR(data->base); 579 580 data->irq = platform_get_irq(pdev, 0); 581 if (data->irq < 0) 582 return data->irq; 583 584 data->bclk = devm_clk_get(dev, "bclk"); 585 if (IS_ERR(data->bclk)) 586 return PTR_ERR(data->bclk); 587 588 larb_nr = 0; 589 of_for_each_phandle(&it, err, dev->of_node, 590 "mediatek,larbs", NULL, 0) { 591 struct platform_device *plarbdev; 592 int count = of_phandle_iterator_args(&it, larb_spec.args, 593 MAX_PHANDLE_ARGS); 594 595 if (count) 596 continue; 597 598 larb_spec.np = of_node_get(it.node); 599 if (!of_device_is_available(larb_spec.np)) 600 continue; 601 602 plarbdev = of_find_device_by_node(larb_spec.np); 603 if (!plarbdev) { 604 plarbdev = of_platform_device_create( 605 larb_spec.np, NULL, 606 platform_bus_type.dev_root); 607 if (!plarbdev) { 608 of_node_put(larb_spec.np); 609 return -EPROBE_DEFER; 610 } 611 } 612 613 data->smi_imu.larb_imu[larb_nr].dev = &plarbdev->dev; 614 component_match_add_release(dev, &match, release_of, 615 compare_of, larb_spec.np); 616 larb_nr++; 617 } 618 619 data->smi_imu.larb_nr = larb_nr; 620 621 platform_set_drvdata(pdev, data); 622 623 ret = mtk_iommu_hw_init(data); 624 if (ret) 625 return ret; 626 627 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 628 dev_name(&pdev->dev)); 629 if (ret) 630 return ret; 631 632 iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); 633 634 ret = iommu_device_register(&data->iommu); 635 if (ret) 636 return ret; 637 638 if (!iommu_present(&platform_bus_type)) 639 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 640 641 return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 642 } 643 644 static int mtk_iommu_remove(struct platform_device *pdev) 645 { 646 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 647 648 iommu_device_sysfs_remove(&data->iommu); 649 iommu_device_unregister(&data->iommu); 650 651 if (iommu_present(&platform_bus_type)) 652 bus_set_iommu(&platform_bus_type, NULL); 653 654 clk_disable_unprepare(data->bclk); 655 devm_free_irq(&pdev->dev, data->irq, data); 656 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 657 return 0; 658 } 659 660 static int __maybe_unused mtk_iommu_suspend(struct device *dev) 661 { 662 struct mtk_iommu_data *data = dev_get_drvdata(dev); 663 struct mtk_iommu_suspend_reg *reg = &data->reg; 664 void __iomem *base = data->base; 665 666 reg->standard_axi_mode = readl_relaxed(base + 667 REG_MMU_STANDARD_AXI_MODE); 668 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); 669 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 670 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); 671 return 0; 672 } 673 674 static int __maybe_unused mtk_iommu_resume(struct device *dev) 675 { 676 struct mtk_iommu_data *data = dev_get_drvdata(dev); 677 struct mtk_iommu_suspend_reg *reg = &data->reg; 678 void __iomem *base = data->base; 679 680 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); 681 writel_relaxed(reg->standard_axi_mode, 682 base + REG_MMU_STANDARD_AXI_MODE); 683 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); 684 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 685 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); 686 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); 687 return 0; 688 } 689 690 static const struct dev_pm_ops mtk_iommu_pm_ops = { 691 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) 692 }; 693 694 static struct platform_driver mtk_iommu_driver = { 695 .probe = mtk_iommu_probe, 696 .remove = mtk_iommu_remove, 697 .driver = { 698 .name = "mtk-iommu-v1", 699 .of_match_table = mtk_iommu_of_ids, 700 .pm = &mtk_iommu_pm_ops, 701 } 702 }; 703 704 static int __init m4u_init(void) 705 { 706 return platform_driver_register(&mtk_iommu_driver); 707 } 708 subsys_initcall(m4u_init); 709