1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IOMMU API for MTK architected m4u v1 implementations 4 * 5 * Copyright (c) 2015-2016 MediaTek Inc. 6 * Author: Honghui Zhang <honghui.zhang@mediatek.com> 7 * 8 * Based on driver/iommu/mtk_iommu.c 9 */ 10 #include <linux/memblock.h> 11 #include <linux/bug.h> 12 #include <linux/clk.h> 13 #include <linux/component.h> 14 #include <linux/device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iommu.h> 20 #include <linux/iopoll.h> 21 #include <linux/list.h> 22 #include <linux/module.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <asm/barrier.h> 30 #include <asm/dma-iommu.h> 31 #include <linux/init.h> 32 #include <dt-bindings/memory/mt2701-larb-port.h> 33 #include <soc/mediatek/smi.h> 34 #include "mtk_iommu.h" 35 36 #define REG_MMU_PT_BASE_ADDR 0x000 37 38 #define F_ALL_INVLD 0x2 39 #define F_MMU_INV_RANGE 0x1 40 #define F_INVLD_EN0 BIT(0) 41 #define F_INVLD_EN1 BIT(1) 42 43 #define F_MMU_FAULT_VA_MSK 0xfffff000 44 #define MTK_PROTECT_PA_ALIGN 128 45 46 #define REG_MMU_CTRL_REG 0x210 47 #define F_MMU_CTRL_COHERENT_EN BIT(8) 48 #define REG_MMU_IVRP_PADDR 0x214 49 #define REG_MMU_INT_CONTROL 0x220 50 #define F_INT_TRANSLATION_FAULT BIT(0) 51 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 52 #define F_INT_INVALID_PA_FAULT BIT(2) 53 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 54 #define F_INT_TABLE_WALK_FAULT BIT(4) 55 #define F_INT_TLB_MISS_FAULT BIT(5) 56 #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) 57 #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) 58 59 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) 60 #define F_INT_CLR_BIT BIT(12) 61 62 #define REG_MMU_FAULT_ST 0x224 63 #define REG_MMU_FAULT_VA 0x228 64 #define REG_MMU_INVLD_PA 0x22C 65 #define REG_MMU_INT_ID 0x388 66 #define REG_MMU_INVALIDATE 0x5c0 67 #define REG_MMU_INVLD_START_A 0x5c4 68 #define REG_MMU_INVLD_END_A 0x5c8 69 70 #define REG_MMU_INV_SEL 0x5d8 71 #define REG_MMU_STANDARD_AXI_MODE 0x5e8 72 73 #define REG_MMU_DCM 0x5f0 74 #define F_MMU_DCM_ON BIT(1) 75 #define REG_MMU_CPE_DONE 0x60c 76 #define F_DESC_VALID 0x2 77 #define F_DESC_NONSEC BIT(3) 78 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) 79 #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) 80 /* MTK generation one iommu HW only support 4K size mapping */ 81 #define MT2701_IOMMU_PAGE_SHIFT 12 82 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) 83 84 /* 85 * MTK m4u support 4GB iova address space, and only support 4K page 86 * mapping. So the pagetable size should be exactly as 4M. 87 */ 88 #define M2701_IOMMU_PGT_SIZE SZ_4M 89 90 struct mtk_iommu_domain { 91 spinlock_t pgtlock; /* lock for page table */ 92 struct iommu_domain domain; 93 u32 *pgt_va; 94 dma_addr_t pgt_pa; 95 struct mtk_iommu_data *data; 96 }; 97 98 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 99 { 100 return container_of(dom, struct mtk_iommu_domain, domain); 101 } 102 103 static const int mt2701_m4u_in_larb[] = { 104 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 105 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 106 }; 107 108 static inline int mt2701_m4u_to_larb(int id) 109 { 110 int i; 111 112 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) 113 if ((id) >= mt2701_m4u_in_larb[i]) 114 return i; 115 116 return 0; 117 } 118 119 static inline int mt2701_m4u_to_port(int id) 120 { 121 int larb = mt2701_m4u_to_larb(id); 122 123 return id - mt2701_m4u_in_larb[larb]; 124 } 125 126 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 127 { 128 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 129 data->base + REG_MMU_INV_SEL); 130 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 131 wmb(); /* Make sure the tlb flush all done */ 132 } 133 134 static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data, 135 unsigned long iova, size_t size) 136 { 137 int ret; 138 u32 tmp; 139 140 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 141 data->base + REG_MMU_INV_SEL); 142 writel_relaxed(iova & F_MMU_FAULT_VA_MSK, 143 data->base + REG_MMU_INVLD_START_A); 144 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, 145 data->base + REG_MMU_INVLD_END_A); 146 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); 147 148 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 149 tmp, tmp != 0, 10, 100000); 150 if (ret) { 151 dev_warn(data->dev, 152 "Partial TLB flush timed out, falling back to full flush\n"); 153 mtk_iommu_tlb_flush_all(data); 154 } 155 /* Clear the CPE status */ 156 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 157 } 158 159 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 160 { 161 struct mtk_iommu_data *data = dev_id; 162 struct mtk_iommu_domain *dom = data->m4u_dom; 163 u32 int_state, regval, fault_iova, fault_pa; 164 unsigned int fault_larb, fault_port; 165 166 /* Read error information from registers */ 167 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); 168 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 169 170 fault_iova &= F_MMU_FAULT_VA_MSK; 171 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 172 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 173 fault_larb = MT2701_M4U_TF_LARB(regval); 174 fault_port = MT2701_M4U_TF_PORT(regval); 175 176 /* 177 * MTK v1 iommu HW could not determine whether the fault is read or 178 * write fault, report as read fault. 179 */ 180 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 181 IOMMU_FAULT_READ)) 182 dev_err_ratelimited(data->dev, 183 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", 184 int_state, fault_iova, fault_pa, 185 fault_larb, fault_port); 186 187 /* Interrupt clear */ 188 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); 189 regval |= F_INT_CLR_BIT; 190 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 191 192 mtk_iommu_tlb_flush_all(data); 193 194 return IRQ_HANDLED; 195 } 196 197 static void mtk_iommu_config(struct mtk_iommu_data *data, 198 struct device *dev, bool enable) 199 { 200 struct mtk_smi_larb_iommu *larb_mmu; 201 unsigned int larbid, portid; 202 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 203 int i; 204 205 for (i = 0; i < fwspec->num_ids; ++i) { 206 larbid = mt2701_m4u_to_larb(fwspec->ids[i]); 207 portid = mt2701_m4u_to_port(fwspec->ids[i]); 208 larb_mmu = &data->larb_imu[larbid]; 209 210 dev_dbg(dev, "%s iommu port: %d\n", 211 enable ? "enable" : "disable", portid); 212 213 if (enable) 214 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 215 else 216 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 217 } 218 } 219 220 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data) 221 { 222 struct mtk_iommu_domain *dom = data->m4u_dom; 223 224 spin_lock_init(&dom->pgtlock); 225 226 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 227 &dom->pgt_pa, GFP_KERNEL); 228 if (!dom->pgt_va) 229 return -ENOMEM; 230 231 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); 232 233 dom->data = data; 234 235 return 0; 236 } 237 238 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 239 { 240 struct mtk_iommu_domain *dom; 241 242 if (type != IOMMU_DOMAIN_UNMANAGED) 243 return NULL; 244 245 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 246 if (!dom) 247 return NULL; 248 249 return &dom->domain; 250 } 251 252 static void mtk_iommu_domain_free(struct iommu_domain *domain) 253 { 254 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 255 struct mtk_iommu_data *data = dom->data; 256 257 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 258 dom->pgt_va, dom->pgt_pa); 259 kfree(to_mtk_domain(domain)); 260 } 261 262 static int mtk_iommu_attach_device(struct iommu_domain *domain, 263 struct device *dev) 264 { 265 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 266 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 267 struct dma_iommu_mapping *mtk_mapping; 268 int ret; 269 270 /* Only allow the domain created internally. */ 271 mtk_mapping = data->mapping; 272 if (mtk_mapping->domain != domain) 273 return 0; 274 275 if (!data->m4u_dom) { 276 data->m4u_dom = dom; 277 ret = mtk_iommu_domain_finalise(data); 278 if (ret) { 279 data->m4u_dom = NULL; 280 return ret; 281 } 282 } 283 284 mtk_iommu_config(data, dev, true); 285 return 0; 286 } 287 288 static void mtk_iommu_detach_device(struct iommu_domain *domain, 289 struct device *dev) 290 { 291 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 292 293 mtk_iommu_config(data, dev, false); 294 } 295 296 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 297 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 298 { 299 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 300 unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 301 unsigned long flags; 302 unsigned int i; 303 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 304 u32 pabase = (u32)paddr; 305 int map_size = 0; 306 307 spin_lock_irqsave(&dom->pgtlock, flags); 308 for (i = 0; i < page_num; i++) { 309 if (pgt_base_iova[i]) { 310 memset(pgt_base_iova, 0, i * sizeof(u32)); 311 break; 312 } 313 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; 314 pabase += MT2701_IOMMU_PAGE_SIZE; 315 map_size += MT2701_IOMMU_PAGE_SIZE; 316 } 317 318 spin_unlock_irqrestore(&dom->pgtlock, flags); 319 320 mtk_iommu_tlb_flush_range(dom->data, iova, size); 321 322 return map_size == size ? 0 : -EEXIST; 323 } 324 325 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 326 unsigned long iova, size_t size, 327 struct iommu_iotlb_gather *gather) 328 { 329 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 330 unsigned long flags; 331 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 332 unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 333 334 spin_lock_irqsave(&dom->pgtlock, flags); 335 memset(pgt_base_iova, 0, page_num * sizeof(u32)); 336 spin_unlock_irqrestore(&dom->pgtlock, flags); 337 338 mtk_iommu_tlb_flush_range(dom->data, iova, size); 339 340 return size; 341 } 342 343 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 344 dma_addr_t iova) 345 { 346 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 347 unsigned long flags; 348 phys_addr_t pa; 349 350 spin_lock_irqsave(&dom->pgtlock, flags); 351 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); 352 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); 353 spin_unlock_irqrestore(&dom->pgtlock, flags); 354 355 return pa; 356 } 357 358 static const struct iommu_ops mtk_iommu_ops; 359 360 /* 361 * MTK generation one iommu HW only support one iommu domain, and all the client 362 * sharing the same iova address space. 363 */ 364 static int mtk_iommu_create_mapping(struct device *dev, 365 struct of_phandle_args *args) 366 { 367 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 368 struct mtk_iommu_data *data; 369 struct platform_device *m4updev; 370 struct dma_iommu_mapping *mtk_mapping; 371 int ret; 372 373 if (args->args_count != 1) { 374 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 375 args->args_count); 376 return -EINVAL; 377 } 378 379 if (!fwspec) { 380 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops); 381 if (ret) 382 return ret; 383 fwspec = dev_iommu_fwspec_get(dev); 384 } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) { 385 return -EINVAL; 386 } 387 388 if (!dev_iommu_priv_get(dev)) { 389 /* Get the m4u device */ 390 m4updev = of_find_device_by_node(args->np); 391 if (WARN_ON(!m4updev)) 392 return -EINVAL; 393 394 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 395 } 396 397 ret = iommu_fwspec_add_ids(dev, args->args, 1); 398 if (ret) 399 return ret; 400 401 data = dev_iommu_priv_get(dev); 402 mtk_mapping = data->mapping; 403 if (!mtk_mapping) { 404 /* MTK iommu support 4GB iova address space. */ 405 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, 406 0, 1ULL << 32); 407 if (IS_ERR(mtk_mapping)) 408 return PTR_ERR(mtk_mapping); 409 410 data->mapping = mtk_mapping; 411 } 412 413 return 0; 414 } 415 416 static int mtk_iommu_def_domain_type(struct device *dev) 417 { 418 return IOMMU_DOMAIN_UNMANAGED; 419 } 420 421 static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 422 { 423 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 424 struct of_phandle_args iommu_spec; 425 struct mtk_iommu_data *data; 426 int err, idx = 0; 427 428 while (!of_parse_phandle_with_args(dev->of_node, "iommus", 429 "#iommu-cells", 430 idx, &iommu_spec)) { 431 432 err = mtk_iommu_create_mapping(dev, &iommu_spec); 433 of_node_put(iommu_spec.np); 434 if (err) 435 return ERR_PTR(err); 436 437 /* dev->iommu_fwspec might have changed */ 438 fwspec = dev_iommu_fwspec_get(dev); 439 idx++; 440 } 441 442 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 443 return ERR_PTR(-ENODEV); /* Not a iommu client device */ 444 445 data = dev_iommu_priv_get(dev); 446 447 return &data->iommu; 448 } 449 450 static void mtk_iommu_probe_finalize(struct device *dev) 451 { 452 struct dma_iommu_mapping *mtk_mapping; 453 struct mtk_iommu_data *data; 454 int err; 455 456 data = dev_iommu_priv_get(dev); 457 mtk_mapping = data->mapping; 458 459 err = arm_iommu_attach_device(dev, mtk_mapping); 460 if (err) 461 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); 462 } 463 464 static void mtk_iommu_release_device(struct device *dev) 465 { 466 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 467 468 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 469 return; 470 471 iommu_fwspec_free(dev); 472 } 473 474 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 475 { 476 u32 regval; 477 int ret; 478 479 ret = clk_prepare_enable(data->bclk); 480 if (ret) { 481 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 482 return ret; 483 } 484 485 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); 486 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 487 488 regval = F_INT_TRANSLATION_FAULT | 489 F_INT_MAIN_MULTI_HIT_FAULT | 490 F_INT_INVALID_PA_FAULT | 491 F_INT_ENTRY_REPLACEMENT_FAULT | 492 F_INT_TABLE_WALK_FAULT | 493 F_INT_TLB_MISS_FAULT | 494 F_INT_PFH_DMA_FIFO_OVERFLOW | 495 F_INT_MISS_DMA_FIFO_OVERFLOW; 496 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 497 498 /* protect memory,hw will write here while translation fault */ 499 writel_relaxed(data->protect_base, 500 data->base + REG_MMU_IVRP_PADDR); 501 502 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); 503 504 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 505 dev_name(data->dev), (void *)data)) { 506 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 507 clk_disable_unprepare(data->bclk); 508 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 509 return -ENODEV; 510 } 511 512 return 0; 513 } 514 515 static const struct iommu_ops mtk_iommu_ops = { 516 .domain_alloc = mtk_iommu_domain_alloc, 517 .domain_free = mtk_iommu_domain_free, 518 .attach_dev = mtk_iommu_attach_device, 519 .detach_dev = mtk_iommu_detach_device, 520 .map = mtk_iommu_map, 521 .unmap = mtk_iommu_unmap, 522 .iova_to_phys = mtk_iommu_iova_to_phys, 523 .probe_device = mtk_iommu_probe_device, 524 .probe_finalize = mtk_iommu_probe_finalize, 525 .release_device = mtk_iommu_release_device, 526 .def_domain_type = mtk_iommu_def_domain_type, 527 .device_group = generic_device_group, 528 .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT, 529 .owner = THIS_MODULE, 530 }; 531 532 static const struct of_device_id mtk_iommu_of_ids[] = { 533 { .compatible = "mediatek,mt2701-m4u", }, 534 {} 535 }; 536 537 static const struct component_master_ops mtk_iommu_com_ops = { 538 .bind = mtk_iommu_bind, 539 .unbind = mtk_iommu_unbind, 540 }; 541 542 static int mtk_iommu_probe(struct platform_device *pdev) 543 { 544 struct mtk_iommu_data *data; 545 struct device *dev = &pdev->dev; 546 struct resource *res; 547 struct component_match *match = NULL; 548 void *protect; 549 int larb_nr, ret, i; 550 551 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 552 if (!data) 553 return -ENOMEM; 554 555 data->dev = dev; 556 557 /* Protect memory. HW will access here while translation fault.*/ 558 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, 559 GFP_KERNEL | GFP_DMA); 560 if (!protect) 561 return -ENOMEM; 562 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 563 564 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 565 data->base = devm_ioremap_resource(dev, res); 566 if (IS_ERR(data->base)) 567 return PTR_ERR(data->base); 568 569 data->irq = platform_get_irq(pdev, 0); 570 if (data->irq < 0) 571 return data->irq; 572 573 data->bclk = devm_clk_get(dev, "bclk"); 574 if (IS_ERR(data->bclk)) 575 return PTR_ERR(data->bclk); 576 577 larb_nr = of_count_phandle_with_args(dev->of_node, 578 "mediatek,larbs", NULL); 579 if (larb_nr < 0) 580 return larb_nr; 581 582 for (i = 0; i < larb_nr; i++) { 583 struct device_node *larbnode; 584 struct platform_device *plarbdev; 585 586 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 587 if (!larbnode) 588 return -EINVAL; 589 590 if (!of_device_is_available(larbnode)) { 591 of_node_put(larbnode); 592 continue; 593 } 594 595 plarbdev = of_find_device_by_node(larbnode); 596 if (!plarbdev) { 597 of_node_put(larbnode); 598 return -EPROBE_DEFER; 599 } 600 data->larb_imu[i].dev = &plarbdev->dev; 601 602 component_match_add_release(dev, &match, release_of, 603 compare_of, larbnode); 604 } 605 606 platform_set_drvdata(pdev, data); 607 608 ret = mtk_iommu_hw_init(data); 609 if (ret) 610 return ret; 611 612 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 613 dev_name(&pdev->dev)); 614 if (ret) 615 return ret; 616 617 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 618 if (ret) 619 goto out_sysfs_remove; 620 621 if (!iommu_present(&platform_bus_type)) { 622 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 623 if (ret) 624 goto out_dev_unreg; 625 } 626 627 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 628 if (ret) 629 goto out_bus_set_null; 630 return ret; 631 632 out_bus_set_null: 633 bus_set_iommu(&platform_bus_type, NULL); 634 out_dev_unreg: 635 iommu_device_unregister(&data->iommu); 636 out_sysfs_remove: 637 iommu_device_sysfs_remove(&data->iommu); 638 return ret; 639 } 640 641 static int mtk_iommu_remove(struct platform_device *pdev) 642 { 643 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 644 645 iommu_device_sysfs_remove(&data->iommu); 646 iommu_device_unregister(&data->iommu); 647 648 if (iommu_present(&platform_bus_type)) 649 bus_set_iommu(&platform_bus_type, NULL); 650 651 clk_disable_unprepare(data->bclk); 652 devm_free_irq(&pdev->dev, data->irq, data); 653 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 654 return 0; 655 } 656 657 static int __maybe_unused mtk_iommu_suspend(struct device *dev) 658 { 659 struct mtk_iommu_data *data = dev_get_drvdata(dev); 660 struct mtk_iommu_suspend_reg *reg = &data->reg; 661 void __iomem *base = data->base; 662 663 reg->standard_axi_mode = readl_relaxed(base + 664 REG_MMU_STANDARD_AXI_MODE); 665 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); 666 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 667 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); 668 return 0; 669 } 670 671 static int __maybe_unused mtk_iommu_resume(struct device *dev) 672 { 673 struct mtk_iommu_data *data = dev_get_drvdata(dev); 674 struct mtk_iommu_suspend_reg *reg = &data->reg; 675 void __iomem *base = data->base; 676 677 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); 678 writel_relaxed(reg->standard_axi_mode, 679 base + REG_MMU_STANDARD_AXI_MODE); 680 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); 681 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 682 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); 683 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); 684 return 0; 685 } 686 687 static const struct dev_pm_ops mtk_iommu_pm_ops = { 688 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) 689 }; 690 691 static struct platform_driver mtk_iommu_driver = { 692 .probe = mtk_iommu_probe, 693 .remove = mtk_iommu_remove, 694 .driver = { 695 .name = "mtk-iommu-v1", 696 .of_match_table = mtk_iommu_of_ids, 697 .pm = &mtk_iommu_pm_ops, 698 } 699 }; 700 module_platform_driver(mtk_iommu_driver); 701 702 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations"); 703 MODULE_LICENSE("GPL v2"); 704