11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2b17336c5SHonghui Zhang /* 3d4cf5bbdSPaul Gortmaker * IOMMU API for MTK architected m4u v1 implementations 4d4cf5bbdSPaul Gortmaker * 5b17336c5SHonghui Zhang * Copyright (c) 2015-2016 MediaTek Inc. 6b17336c5SHonghui Zhang * Author: Honghui Zhang <honghui.zhang@mediatek.com> 7b17336c5SHonghui Zhang * 8b17336c5SHonghui Zhang * Based on driver/iommu/mtk_iommu.c 9b17336c5SHonghui Zhang */ 1057c8a661SMike Rapoport #include <linux/memblock.h> 11b17336c5SHonghui Zhang #include <linux/bug.h> 12b17336c5SHonghui Zhang #include <linux/clk.h> 13b17336c5SHonghui Zhang #include <linux/component.h> 14b17336c5SHonghui Zhang #include <linux/device.h> 15745b6e74SArnd Bergmann #include <linux/dma-mapping.h> 16b17336c5SHonghui Zhang #include <linux/dma-iommu.h> 17b17336c5SHonghui Zhang #include <linux/err.h> 18b17336c5SHonghui Zhang #include <linux/interrupt.h> 19b17336c5SHonghui Zhang #include <linux/io.h> 20b17336c5SHonghui Zhang #include <linux/iommu.h> 21b17336c5SHonghui Zhang #include <linux/iopoll.h> 22b17336c5SHonghui Zhang #include <linux/list.h> 23*8de000cfSYong Wu #include <linux/module.h> 24b17336c5SHonghui Zhang #include <linux/of_address.h> 25b17336c5SHonghui Zhang #include <linux/of_iommu.h> 26b17336c5SHonghui Zhang #include <linux/of_irq.h> 27b17336c5SHonghui Zhang #include <linux/of_platform.h> 28b17336c5SHonghui Zhang #include <linux/platform_device.h> 29b17336c5SHonghui Zhang #include <linux/slab.h> 30b17336c5SHonghui Zhang #include <linux/spinlock.h> 31b17336c5SHonghui Zhang #include <asm/barrier.h> 32b17336c5SHonghui Zhang #include <asm/dma-iommu.h> 33d4cf5bbdSPaul Gortmaker #include <linux/init.h> 34b17336c5SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 35b17336c5SHonghui Zhang #include <soc/mediatek/smi.h> 36b17336c5SHonghui Zhang #include "mtk_iommu.h" 37b17336c5SHonghui Zhang 38b17336c5SHonghui Zhang #define REG_MMU_PT_BASE_ADDR 0x000 39b17336c5SHonghui Zhang 40b17336c5SHonghui Zhang #define F_ALL_INVLD 0x2 41b17336c5SHonghui Zhang #define F_MMU_INV_RANGE 0x1 42b17336c5SHonghui Zhang #define F_INVLD_EN0 BIT(0) 43b17336c5SHonghui Zhang #define F_INVLD_EN1 BIT(1) 44b17336c5SHonghui Zhang 45b17336c5SHonghui Zhang #define F_MMU_FAULT_VA_MSK 0xfffff000 46b17336c5SHonghui Zhang #define MTK_PROTECT_PA_ALIGN 128 47b17336c5SHonghui Zhang 48b17336c5SHonghui Zhang #define REG_MMU_CTRL_REG 0x210 49b17336c5SHonghui Zhang #define F_MMU_CTRL_COHERENT_EN BIT(8) 50b17336c5SHonghui Zhang #define REG_MMU_IVRP_PADDR 0x214 51b17336c5SHonghui Zhang #define REG_MMU_INT_CONTROL 0x220 52b17336c5SHonghui Zhang #define F_INT_TRANSLATION_FAULT BIT(0) 53b17336c5SHonghui Zhang #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 54b17336c5SHonghui Zhang #define F_INT_INVALID_PA_FAULT BIT(2) 55b17336c5SHonghui Zhang #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 56b17336c5SHonghui Zhang #define F_INT_TABLE_WALK_FAULT BIT(4) 57b17336c5SHonghui Zhang #define F_INT_TLB_MISS_FAULT BIT(5) 58b17336c5SHonghui Zhang #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) 59b17336c5SHonghui Zhang #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) 60b17336c5SHonghui Zhang 61b17336c5SHonghui Zhang #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) 62b17336c5SHonghui Zhang #define F_INT_CLR_BIT BIT(12) 63b17336c5SHonghui Zhang 64b17336c5SHonghui Zhang #define REG_MMU_FAULT_ST 0x224 65b17336c5SHonghui Zhang #define REG_MMU_FAULT_VA 0x228 66b17336c5SHonghui Zhang #define REG_MMU_INVLD_PA 0x22C 67b17336c5SHonghui Zhang #define REG_MMU_INT_ID 0x388 68b17336c5SHonghui Zhang #define REG_MMU_INVALIDATE 0x5c0 69b17336c5SHonghui Zhang #define REG_MMU_INVLD_START_A 0x5c4 70b17336c5SHonghui Zhang #define REG_MMU_INVLD_END_A 0x5c8 71b17336c5SHonghui Zhang 72b17336c5SHonghui Zhang #define REG_MMU_INV_SEL 0x5d8 73b17336c5SHonghui Zhang #define REG_MMU_STANDARD_AXI_MODE 0x5e8 74b17336c5SHonghui Zhang 75b17336c5SHonghui Zhang #define REG_MMU_DCM 0x5f0 76b17336c5SHonghui Zhang #define F_MMU_DCM_ON BIT(1) 77b17336c5SHonghui Zhang #define REG_MMU_CPE_DONE 0x60c 78b17336c5SHonghui Zhang #define F_DESC_VALID 0x2 79b17336c5SHonghui Zhang #define F_DESC_NONSEC BIT(3) 80b17336c5SHonghui Zhang #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) 81b17336c5SHonghui Zhang #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) 82b17336c5SHonghui Zhang /* MTK generation one iommu HW only support 4K size mapping */ 83b17336c5SHonghui Zhang #define MT2701_IOMMU_PAGE_SHIFT 12 84b17336c5SHonghui Zhang #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) 85b17336c5SHonghui Zhang 86b17336c5SHonghui Zhang /* 87b17336c5SHonghui Zhang * MTK m4u support 4GB iova address space, and only support 4K page 88b17336c5SHonghui Zhang * mapping. So the pagetable size should be exactly as 4M. 89b17336c5SHonghui Zhang */ 90b17336c5SHonghui Zhang #define M2701_IOMMU_PGT_SIZE SZ_4M 91b17336c5SHonghui Zhang 92b17336c5SHonghui Zhang struct mtk_iommu_domain { 93b17336c5SHonghui Zhang spinlock_t pgtlock; /* lock for page table */ 94b17336c5SHonghui Zhang struct iommu_domain domain; 95b17336c5SHonghui Zhang u32 *pgt_va; 96b17336c5SHonghui Zhang dma_addr_t pgt_pa; 97b17336c5SHonghui Zhang struct mtk_iommu_data *data; 98b17336c5SHonghui Zhang }; 99b17336c5SHonghui Zhang 100b17336c5SHonghui Zhang static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 101b17336c5SHonghui Zhang { 102b17336c5SHonghui Zhang return container_of(dom, struct mtk_iommu_domain, domain); 103b17336c5SHonghui Zhang } 104b17336c5SHonghui Zhang 105b17336c5SHonghui Zhang static const int mt2701_m4u_in_larb[] = { 106b17336c5SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 107b17336c5SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 108b17336c5SHonghui Zhang }; 109b17336c5SHonghui Zhang 110b17336c5SHonghui Zhang static inline int mt2701_m4u_to_larb(int id) 111b17336c5SHonghui Zhang { 112b17336c5SHonghui Zhang int i; 113b17336c5SHonghui Zhang 114b17336c5SHonghui Zhang for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) 115b17336c5SHonghui Zhang if ((id) >= mt2701_m4u_in_larb[i]) 116b17336c5SHonghui Zhang return i; 117b17336c5SHonghui Zhang 118b17336c5SHonghui Zhang return 0; 119b17336c5SHonghui Zhang } 120b17336c5SHonghui Zhang 121b17336c5SHonghui Zhang static inline int mt2701_m4u_to_port(int id) 122b17336c5SHonghui Zhang { 123b17336c5SHonghui Zhang int larb = mt2701_m4u_to_larb(id); 124b17336c5SHonghui Zhang 125b17336c5SHonghui Zhang return id - mt2701_m4u_in_larb[larb]; 126b17336c5SHonghui Zhang } 127b17336c5SHonghui Zhang 128b17336c5SHonghui Zhang static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 129b17336c5SHonghui Zhang { 130b17336c5SHonghui Zhang writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 131b17336c5SHonghui Zhang data->base + REG_MMU_INV_SEL); 132b17336c5SHonghui Zhang writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 133b17336c5SHonghui Zhang wmb(); /* Make sure the tlb flush all done */ 134b17336c5SHonghui Zhang } 135b17336c5SHonghui Zhang 136b17336c5SHonghui Zhang static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data, 137b17336c5SHonghui Zhang unsigned long iova, size_t size) 138b17336c5SHonghui Zhang { 139b17336c5SHonghui Zhang int ret; 140b17336c5SHonghui Zhang u32 tmp; 141b17336c5SHonghui Zhang 142b17336c5SHonghui Zhang writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 143b17336c5SHonghui Zhang data->base + REG_MMU_INV_SEL); 144b17336c5SHonghui Zhang writel_relaxed(iova & F_MMU_FAULT_VA_MSK, 145b17336c5SHonghui Zhang data->base + REG_MMU_INVLD_START_A); 146b17336c5SHonghui Zhang writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, 147b17336c5SHonghui Zhang data->base + REG_MMU_INVLD_END_A); 148b17336c5SHonghui Zhang writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); 149b17336c5SHonghui Zhang 150b17336c5SHonghui Zhang ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 151b17336c5SHonghui Zhang tmp, tmp != 0, 10, 100000); 152b17336c5SHonghui Zhang if (ret) { 153b17336c5SHonghui Zhang dev_warn(data->dev, 154b17336c5SHonghui Zhang "Partial TLB flush timed out, falling back to full flush\n"); 155b17336c5SHonghui Zhang mtk_iommu_tlb_flush_all(data); 156b17336c5SHonghui Zhang } 157b17336c5SHonghui Zhang /* Clear the CPE status */ 158b17336c5SHonghui Zhang writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 159b17336c5SHonghui Zhang } 160b17336c5SHonghui Zhang 161b17336c5SHonghui Zhang static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 162b17336c5SHonghui Zhang { 163b17336c5SHonghui Zhang struct mtk_iommu_data *data = dev_id; 164b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = data->m4u_dom; 165b17336c5SHonghui Zhang u32 int_state, regval, fault_iova, fault_pa; 166b17336c5SHonghui Zhang unsigned int fault_larb, fault_port; 167b17336c5SHonghui Zhang 168b17336c5SHonghui Zhang /* Read error information from registers */ 169b17336c5SHonghui Zhang int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); 170b17336c5SHonghui Zhang fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 171b17336c5SHonghui Zhang 172b17336c5SHonghui Zhang fault_iova &= F_MMU_FAULT_VA_MSK; 173b17336c5SHonghui Zhang fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 174b17336c5SHonghui Zhang regval = readl_relaxed(data->base + REG_MMU_INT_ID); 175b17336c5SHonghui Zhang fault_larb = MT2701_M4U_TF_LARB(regval); 176b17336c5SHonghui Zhang fault_port = MT2701_M4U_TF_PORT(regval); 177b17336c5SHonghui Zhang 178b17336c5SHonghui Zhang /* 179b17336c5SHonghui Zhang * MTK v1 iommu HW could not determine whether the fault is read or 180b17336c5SHonghui Zhang * write fault, report as read fault. 181b17336c5SHonghui Zhang */ 182b17336c5SHonghui Zhang if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 183b17336c5SHonghui Zhang IOMMU_FAULT_READ)) 184b17336c5SHonghui Zhang dev_err_ratelimited(data->dev, 185b17336c5SHonghui Zhang "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", 186b17336c5SHonghui Zhang int_state, fault_iova, fault_pa, 187b17336c5SHonghui Zhang fault_larb, fault_port); 188b17336c5SHonghui Zhang 189b17336c5SHonghui Zhang /* Interrupt clear */ 190b17336c5SHonghui Zhang regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); 191b17336c5SHonghui Zhang regval |= F_INT_CLR_BIT; 192b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 193b17336c5SHonghui Zhang 194b17336c5SHonghui Zhang mtk_iommu_tlb_flush_all(data); 195b17336c5SHonghui Zhang 196b17336c5SHonghui Zhang return IRQ_HANDLED; 197b17336c5SHonghui Zhang } 198b17336c5SHonghui Zhang 199b17336c5SHonghui Zhang static void mtk_iommu_config(struct mtk_iommu_data *data, 200b17336c5SHonghui Zhang struct device *dev, bool enable) 201b17336c5SHonghui Zhang { 202b17336c5SHonghui Zhang struct mtk_smi_larb_iommu *larb_mmu; 203b17336c5SHonghui Zhang unsigned int larbid, portid; 204a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 20584672f19SRobin Murphy int i; 206b17336c5SHonghui Zhang 20784672f19SRobin Murphy for (i = 0; i < fwspec->num_ids; ++i) { 20884672f19SRobin Murphy larbid = mt2701_m4u_to_larb(fwspec->ids[i]); 20984672f19SRobin Murphy portid = mt2701_m4u_to_port(fwspec->ids[i]); 2101ee9feb2SYong Wu larb_mmu = &data->larb_imu[larbid]; 211b17336c5SHonghui Zhang 212b17336c5SHonghui Zhang dev_dbg(dev, "%s iommu port: %d\n", 213b17336c5SHonghui Zhang enable ? "enable" : "disable", portid); 214b17336c5SHonghui Zhang 215b17336c5SHonghui Zhang if (enable) 216b17336c5SHonghui Zhang larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 217b17336c5SHonghui Zhang else 218b17336c5SHonghui Zhang larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 219b17336c5SHonghui Zhang } 220b17336c5SHonghui Zhang } 221b17336c5SHonghui Zhang 222b17336c5SHonghui Zhang static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data) 223b17336c5SHonghui Zhang { 224b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = data->m4u_dom; 225b17336c5SHonghui Zhang 226b17336c5SHonghui Zhang spin_lock_init(&dom->pgtlock); 227b17336c5SHonghui Zhang 228750afb08SLuis Chamberlain dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 229b17336c5SHonghui Zhang &dom->pgt_pa, GFP_KERNEL); 230b17336c5SHonghui Zhang if (!dom->pgt_va) 231b17336c5SHonghui Zhang return -ENOMEM; 232b17336c5SHonghui Zhang 233b17336c5SHonghui Zhang writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); 234b17336c5SHonghui Zhang 235b17336c5SHonghui Zhang dom->data = data; 236b17336c5SHonghui Zhang 237b17336c5SHonghui Zhang return 0; 238b17336c5SHonghui Zhang } 239b17336c5SHonghui Zhang 240b17336c5SHonghui Zhang static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 241b17336c5SHonghui Zhang { 242b17336c5SHonghui Zhang struct mtk_iommu_domain *dom; 243b17336c5SHonghui Zhang 244b17336c5SHonghui Zhang if (type != IOMMU_DOMAIN_UNMANAGED) 245b17336c5SHonghui Zhang return NULL; 246b17336c5SHonghui Zhang 247b17336c5SHonghui Zhang dom = kzalloc(sizeof(*dom), GFP_KERNEL); 248b17336c5SHonghui Zhang if (!dom) 249b17336c5SHonghui Zhang return NULL; 250b17336c5SHonghui Zhang 251b17336c5SHonghui Zhang return &dom->domain; 252b17336c5SHonghui Zhang } 253b17336c5SHonghui Zhang 254b17336c5SHonghui Zhang static void mtk_iommu_domain_free(struct iommu_domain *domain) 255b17336c5SHonghui Zhang { 256b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 257b17336c5SHonghui Zhang struct mtk_iommu_data *data = dom->data; 258b17336c5SHonghui Zhang 259b17336c5SHonghui Zhang dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 260b17336c5SHonghui Zhang dom->pgt_va, dom->pgt_pa); 261b17336c5SHonghui Zhang kfree(to_mtk_domain(domain)); 262b17336c5SHonghui Zhang } 263b17336c5SHonghui Zhang 264b17336c5SHonghui Zhang static int mtk_iommu_attach_device(struct iommu_domain *domain, 265b17336c5SHonghui Zhang struct device *dev) 266b17336c5SHonghui Zhang { 2673524b559SJoerg Roedel struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 268b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 2698bbe13f5SYong Wu struct dma_iommu_mapping *mtk_mapping; 270b17336c5SHonghui Zhang int ret; 271b17336c5SHonghui Zhang 2728bbe13f5SYong Wu /* Only allow the domain created internally. */ 27358960172SJoerg Roedel mtk_mapping = data->mapping; 2748bbe13f5SYong Wu if (mtk_mapping->domain != domain) 2758bbe13f5SYong Wu return 0; 276b17336c5SHonghui Zhang 277b17336c5SHonghui Zhang if (!data->m4u_dom) { 278b17336c5SHonghui Zhang data->m4u_dom = dom; 279b17336c5SHonghui Zhang ret = mtk_iommu_domain_finalise(data); 280b17336c5SHonghui Zhang if (ret) { 281b17336c5SHonghui Zhang data->m4u_dom = NULL; 282b17336c5SHonghui Zhang return ret; 283b17336c5SHonghui Zhang } 284b17336c5SHonghui Zhang } 285b17336c5SHonghui Zhang 286b17336c5SHonghui Zhang mtk_iommu_config(data, dev, true); 287b17336c5SHonghui Zhang return 0; 288b17336c5SHonghui Zhang } 289b17336c5SHonghui Zhang 290b17336c5SHonghui Zhang static void mtk_iommu_detach_device(struct iommu_domain *domain, 291b17336c5SHonghui Zhang struct device *dev) 292b17336c5SHonghui Zhang { 2933524b559SJoerg Roedel struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 294b17336c5SHonghui Zhang 295b17336c5SHonghui Zhang mtk_iommu_config(data, dev, false); 296b17336c5SHonghui Zhang } 297b17336c5SHonghui Zhang 298b17336c5SHonghui Zhang static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 299781ca2deSTom Murphy phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 300b17336c5SHonghui Zhang { 301b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 302b17336c5SHonghui Zhang unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 303b17336c5SHonghui Zhang unsigned long flags; 304b17336c5SHonghui Zhang unsigned int i; 305b17336c5SHonghui Zhang u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 306b17336c5SHonghui Zhang u32 pabase = (u32)paddr; 307b17336c5SHonghui Zhang int map_size = 0; 308b17336c5SHonghui Zhang 309b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags); 310b17336c5SHonghui Zhang for (i = 0; i < page_num; i++) { 311b17336c5SHonghui Zhang if (pgt_base_iova[i]) { 312b17336c5SHonghui Zhang memset(pgt_base_iova, 0, i * sizeof(u32)); 313b17336c5SHonghui Zhang break; 314b17336c5SHonghui Zhang } 315b17336c5SHonghui Zhang pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; 316b17336c5SHonghui Zhang pabase += MT2701_IOMMU_PAGE_SIZE; 317b17336c5SHonghui Zhang map_size += MT2701_IOMMU_PAGE_SIZE; 318b17336c5SHonghui Zhang } 319b17336c5SHonghui Zhang 320b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags); 321b17336c5SHonghui Zhang 322b17336c5SHonghui Zhang mtk_iommu_tlb_flush_range(dom->data, iova, size); 323b17336c5SHonghui Zhang 324b17336c5SHonghui Zhang return map_size == size ? 0 : -EEXIST; 325b17336c5SHonghui Zhang } 326b17336c5SHonghui Zhang 327b17336c5SHonghui Zhang static size_t mtk_iommu_unmap(struct iommu_domain *domain, 32856f8af5eSWill Deacon unsigned long iova, size_t size, 32956f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 330b17336c5SHonghui Zhang { 331b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 332b17336c5SHonghui Zhang unsigned long flags; 333b17336c5SHonghui Zhang u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 334b17336c5SHonghui Zhang unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 335b17336c5SHonghui Zhang 336b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags); 337b17336c5SHonghui Zhang memset(pgt_base_iova, 0, page_num * sizeof(u32)); 338b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags); 339b17336c5SHonghui Zhang 340b17336c5SHonghui Zhang mtk_iommu_tlb_flush_range(dom->data, iova, size); 341b17336c5SHonghui Zhang 342b17336c5SHonghui Zhang return size; 343b17336c5SHonghui Zhang } 344b17336c5SHonghui Zhang 345b17336c5SHonghui Zhang static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 346b17336c5SHonghui Zhang dma_addr_t iova) 347b17336c5SHonghui Zhang { 348b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 349b17336c5SHonghui Zhang unsigned long flags; 350b17336c5SHonghui Zhang phys_addr_t pa; 351b17336c5SHonghui Zhang 352b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags); 353b17336c5SHonghui Zhang pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); 354b17336c5SHonghui Zhang pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); 355b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags); 356b17336c5SHonghui Zhang 357b17336c5SHonghui Zhang return pa; 358b17336c5SHonghui Zhang } 359b17336c5SHonghui Zhang 360b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops; 36184672f19SRobin Murphy 362b17336c5SHonghui Zhang /* 363b17336c5SHonghui Zhang * MTK generation one iommu HW only support one iommu domain, and all the client 364b17336c5SHonghui Zhang * sharing the same iova address space. 365b17336c5SHonghui Zhang */ 366b17336c5SHonghui Zhang static int mtk_iommu_create_mapping(struct device *dev, 367b17336c5SHonghui Zhang struct of_phandle_args *args) 368b17336c5SHonghui Zhang { 369a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 37084672f19SRobin Murphy struct mtk_iommu_data *data; 371b17336c5SHonghui Zhang struct platform_device *m4updev; 372b17336c5SHonghui Zhang struct dma_iommu_mapping *mtk_mapping; 373b17336c5SHonghui Zhang int ret; 374b17336c5SHonghui Zhang 375b17336c5SHonghui Zhang if (args->args_count != 1) { 376b17336c5SHonghui Zhang dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 377b17336c5SHonghui Zhang args->args_count); 378b17336c5SHonghui Zhang return -EINVAL; 379b17336c5SHonghui Zhang } 380b17336c5SHonghui Zhang 381a9bf2eecSJoerg Roedel if (!fwspec) { 38284672f19SRobin Murphy ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops); 38384672f19SRobin Murphy if (ret) 38484672f19SRobin Murphy return ret; 385a9bf2eecSJoerg Roedel fwspec = dev_iommu_fwspec_get(dev); 386a9bf2eecSJoerg Roedel } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) { 38784672f19SRobin Murphy return -EINVAL; 38884672f19SRobin Murphy } 38984672f19SRobin Murphy 3903524b559SJoerg Roedel if (!dev_iommu_priv_get(dev)) { 391b17336c5SHonghui Zhang /* Get the m4u device */ 392b17336c5SHonghui Zhang m4updev = of_find_device_by_node(args->np); 393b17336c5SHonghui Zhang if (WARN_ON(!m4updev)) 394b17336c5SHonghui Zhang return -EINVAL; 395b17336c5SHonghui Zhang 3963524b559SJoerg Roedel dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 397b17336c5SHonghui Zhang } 398b17336c5SHonghui Zhang 39984672f19SRobin Murphy ret = iommu_fwspec_add_ids(dev, args->args, 1); 40084672f19SRobin Murphy if (ret) 40184672f19SRobin Murphy return ret; 402b17336c5SHonghui Zhang 4033524b559SJoerg Roedel data = dev_iommu_priv_get(dev); 40458960172SJoerg Roedel mtk_mapping = data->mapping; 405b17336c5SHonghui Zhang if (!mtk_mapping) { 406b17336c5SHonghui Zhang /* MTK iommu support 4GB iova address space. */ 407b17336c5SHonghui Zhang mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, 408b17336c5SHonghui Zhang 0, 1ULL << 32); 40984672f19SRobin Murphy if (IS_ERR(mtk_mapping)) 41084672f19SRobin Murphy return PTR_ERR(mtk_mapping); 41184672f19SRobin Murphy 41258960172SJoerg Roedel data->mapping = mtk_mapping; 413b17336c5SHonghui Zhang } 414b17336c5SHonghui Zhang 415b17336c5SHonghui Zhang return 0; 416b17336c5SHonghui Zhang } 417b17336c5SHonghui Zhang 4188bbe13f5SYong Wu static int mtk_iommu_def_domain_type(struct device *dev) 4198bbe13f5SYong Wu { 4208bbe13f5SYong Wu return IOMMU_DOMAIN_UNMANAGED; 4218bbe13f5SYong Wu } 4228bbe13f5SYong Wu 42357dbf81fSJoerg Roedel static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 424b17336c5SHonghui Zhang { 425a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 426b17336c5SHonghui Zhang struct of_phandle_args iommu_spec; 427b17336c5SHonghui Zhang struct of_phandle_iterator it; 4286f66ea09SJoerg Roedel struct mtk_iommu_data *data; 429b17336c5SHonghui Zhang int err; 430b17336c5SHonghui Zhang 431b17336c5SHonghui Zhang of_for_each_phandle(&it, err, dev->of_node, "iommus", 432c680e9abSUwe Kleine-König "#iommu-cells", -1) { 433b17336c5SHonghui Zhang int count = of_phandle_iterator_args(&it, iommu_spec.args, 434b17336c5SHonghui Zhang MAX_PHANDLE_ARGS); 435b17336c5SHonghui Zhang iommu_spec.np = of_node_get(it.node); 436b17336c5SHonghui Zhang iommu_spec.args_count = count; 437b17336c5SHonghui Zhang 438b17336c5SHonghui Zhang mtk_iommu_create_mapping(dev, &iommu_spec); 439da5d2748SJoerg Roedel 440da5d2748SJoerg Roedel /* dev->iommu_fwspec might have changed */ 441da5d2748SJoerg Roedel fwspec = dev_iommu_fwspec_get(dev); 442da5d2748SJoerg Roedel 443b17336c5SHonghui Zhang of_node_put(iommu_spec.np); 444b17336c5SHonghui Zhang } 445b17336c5SHonghui Zhang 446a9bf2eecSJoerg Roedel if (!fwspec || fwspec->ops != &mtk_iommu_ops) 44757dbf81fSJoerg Roedel return ERR_PTR(-ENODEV); /* Not a iommu client device */ 448b17336c5SHonghui Zhang 44957dbf81fSJoerg Roedel data = dev_iommu_priv_get(dev); 450b17336c5SHonghui Zhang 45157dbf81fSJoerg Roedel return &data->iommu; 45257dbf81fSJoerg Roedel } 45357dbf81fSJoerg Roedel 45457dbf81fSJoerg Roedel static void mtk_iommu_probe_finalize(struct device *dev) 45557dbf81fSJoerg Roedel { 45657dbf81fSJoerg Roedel struct dma_iommu_mapping *mtk_mapping; 45757dbf81fSJoerg Roedel struct mtk_iommu_data *data; 45857dbf81fSJoerg Roedel int err; 459f3e827d7SYong Wu 4603524b559SJoerg Roedel data = dev_iommu_priv_get(dev); 46158960172SJoerg Roedel mtk_mapping = data->mapping; 46257dbf81fSJoerg Roedel 463f3e827d7SYong Wu err = arm_iommu_attach_device(dev, mtk_mapping); 46457dbf81fSJoerg Roedel if (err) 46557dbf81fSJoerg Roedel dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); 466f3e827d7SYong Wu } 467f3e827d7SYong Wu 46857dbf81fSJoerg Roedel static void mtk_iommu_release_device(struct device *dev) 469b17336c5SHonghui Zhang { 470a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 4716f66ea09SJoerg Roedel 472a9bf2eecSJoerg Roedel if (!fwspec || fwspec->ops != &mtk_iommu_ops) 473b17336c5SHonghui Zhang return; 474b17336c5SHonghui Zhang 47584672f19SRobin Murphy iommu_fwspec_free(dev); 476b17336c5SHonghui Zhang } 477b17336c5SHonghui Zhang 478b17336c5SHonghui Zhang static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 479b17336c5SHonghui Zhang { 480b17336c5SHonghui Zhang u32 regval; 481b17336c5SHonghui Zhang int ret; 482b17336c5SHonghui Zhang 483b17336c5SHonghui Zhang ret = clk_prepare_enable(data->bclk); 484b17336c5SHonghui Zhang if (ret) { 485b17336c5SHonghui Zhang dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 486b17336c5SHonghui Zhang return ret; 487b17336c5SHonghui Zhang } 488b17336c5SHonghui Zhang 489b17336c5SHonghui Zhang regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); 490b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 491b17336c5SHonghui Zhang 492b17336c5SHonghui Zhang regval = F_INT_TRANSLATION_FAULT | 493b17336c5SHonghui Zhang F_INT_MAIN_MULTI_HIT_FAULT | 494b17336c5SHonghui Zhang F_INT_INVALID_PA_FAULT | 495b17336c5SHonghui Zhang F_INT_ENTRY_REPLACEMENT_FAULT | 496b17336c5SHonghui Zhang F_INT_TABLE_WALK_FAULT | 497b17336c5SHonghui Zhang F_INT_TLB_MISS_FAULT | 498b17336c5SHonghui Zhang F_INT_PFH_DMA_FIFO_OVERFLOW | 499b17336c5SHonghui Zhang F_INT_MISS_DMA_FIFO_OVERFLOW; 500b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 501b17336c5SHonghui Zhang 502b17336c5SHonghui Zhang /* protect memory,hw will write here while translation fault */ 503b17336c5SHonghui Zhang writel_relaxed(data->protect_base, 504b17336c5SHonghui Zhang data->base + REG_MMU_IVRP_PADDR); 505b17336c5SHonghui Zhang 506b17336c5SHonghui Zhang writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); 507b17336c5SHonghui Zhang 508b17336c5SHonghui Zhang if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 509b17336c5SHonghui Zhang dev_name(data->dev), (void *)data)) { 510b17336c5SHonghui Zhang writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 511b17336c5SHonghui Zhang clk_disable_unprepare(data->bclk); 512b17336c5SHonghui Zhang dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 513b17336c5SHonghui Zhang return -ENODEV; 514b17336c5SHonghui Zhang } 515b17336c5SHonghui Zhang 516b17336c5SHonghui Zhang return 0; 517b17336c5SHonghui Zhang } 518b17336c5SHonghui Zhang 519b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops = { 520b17336c5SHonghui Zhang .domain_alloc = mtk_iommu_domain_alloc, 521b17336c5SHonghui Zhang .domain_free = mtk_iommu_domain_free, 522b17336c5SHonghui Zhang .attach_dev = mtk_iommu_attach_device, 523b17336c5SHonghui Zhang .detach_dev = mtk_iommu_detach_device, 524b17336c5SHonghui Zhang .map = mtk_iommu_map, 525b17336c5SHonghui Zhang .unmap = mtk_iommu_unmap, 526b17336c5SHonghui Zhang .iova_to_phys = mtk_iommu_iova_to_phys, 52757dbf81fSJoerg Roedel .probe_device = mtk_iommu_probe_device, 52857dbf81fSJoerg Roedel .probe_finalize = mtk_iommu_probe_finalize, 52957dbf81fSJoerg Roedel .release_device = mtk_iommu_release_device, 5308bbe13f5SYong Wu .def_domain_type = mtk_iommu_def_domain_type, 53157dbf81fSJoerg Roedel .device_group = generic_device_group, 532b17336c5SHonghui Zhang .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT, 533*8de000cfSYong Wu .owner = THIS_MODULE, 534b17336c5SHonghui Zhang }; 535b17336c5SHonghui Zhang 536b17336c5SHonghui Zhang static const struct of_device_id mtk_iommu_of_ids[] = { 537b17336c5SHonghui Zhang { .compatible = "mediatek,mt2701-m4u", }, 538b17336c5SHonghui Zhang {} 539b17336c5SHonghui Zhang }; 540b17336c5SHonghui Zhang 541b17336c5SHonghui Zhang static const struct component_master_ops mtk_iommu_com_ops = { 542b17336c5SHonghui Zhang .bind = mtk_iommu_bind, 543b17336c5SHonghui Zhang .unbind = mtk_iommu_unbind, 544b17336c5SHonghui Zhang }; 545b17336c5SHonghui Zhang 546b17336c5SHonghui Zhang static int mtk_iommu_probe(struct platform_device *pdev) 547b17336c5SHonghui Zhang { 548b17336c5SHonghui Zhang struct mtk_iommu_data *data; 549b17336c5SHonghui Zhang struct device *dev = &pdev->dev; 550b17336c5SHonghui Zhang struct resource *res; 551b17336c5SHonghui Zhang struct component_match *match = NULL; 552b17336c5SHonghui Zhang struct of_phandle_args larb_spec; 553b17336c5SHonghui Zhang struct of_phandle_iterator it; 554b17336c5SHonghui Zhang void *protect; 555b17336c5SHonghui Zhang int larb_nr, ret, err; 556b17336c5SHonghui Zhang 557b17336c5SHonghui Zhang data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 558b17336c5SHonghui Zhang if (!data) 559b17336c5SHonghui Zhang return -ENOMEM; 560b17336c5SHonghui Zhang 561b17336c5SHonghui Zhang data->dev = dev; 562b17336c5SHonghui Zhang 563b17336c5SHonghui Zhang /* Protect memory. HW will access here while translation fault.*/ 564b17336c5SHonghui Zhang protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, 565b17336c5SHonghui Zhang GFP_KERNEL | GFP_DMA); 566b17336c5SHonghui Zhang if (!protect) 567b17336c5SHonghui Zhang return -ENOMEM; 568b17336c5SHonghui Zhang data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 569b17336c5SHonghui Zhang 570b17336c5SHonghui Zhang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 571b17336c5SHonghui Zhang data->base = devm_ioremap_resource(dev, res); 572b17336c5SHonghui Zhang if (IS_ERR(data->base)) 573b17336c5SHonghui Zhang return PTR_ERR(data->base); 574b17336c5SHonghui Zhang 575b17336c5SHonghui Zhang data->irq = platform_get_irq(pdev, 0); 576b17336c5SHonghui Zhang if (data->irq < 0) 577b17336c5SHonghui Zhang return data->irq; 578b17336c5SHonghui Zhang 579b17336c5SHonghui Zhang data->bclk = devm_clk_get(dev, "bclk"); 580b17336c5SHonghui Zhang if (IS_ERR(data->bclk)) 581b17336c5SHonghui Zhang return PTR_ERR(data->bclk); 582b17336c5SHonghui Zhang 583b17336c5SHonghui Zhang larb_nr = 0; 584b17336c5SHonghui Zhang of_for_each_phandle(&it, err, dev->of_node, 585b17336c5SHonghui Zhang "mediatek,larbs", NULL, 0) { 586b17336c5SHonghui Zhang struct platform_device *plarbdev; 587b17336c5SHonghui Zhang int count = of_phandle_iterator_args(&it, larb_spec.args, 588b17336c5SHonghui Zhang MAX_PHANDLE_ARGS); 589b17336c5SHonghui Zhang 590b17336c5SHonghui Zhang if (count) 591b17336c5SHonghui Zhang continue; 592b17336c5SHonghui Zhang 593b17336c5SHonghui Zhang larb_spec.np = of_node_get(it.node); 594b17336c5SHonghui Zhang if (!of_device_is_available(larb_spec.np)) 595b17336c5SHonghui Zhang continue; 596b17336c5SHonghui Zhang 597b17336c5SHonghui Zhang plarbdev = of_find_device_by_node(larb_spec.np); 598b17336c5SHonghui Zhang if (!plarbdev) { 599b17336c5SHonghui Zhang plarbdev = of_platform_device_create( 600b17336c5SHonghui Zhang larb_spec.np, NULL, 601b17336c5SHonghui Zhang platform_bus_type.dev_root); 60200c7c81fSRussell King if (!plarbdev) { 60300c7c81fSRussell King of_node_put(larb_spec.np); 604b17336c5SHonghui Zhang return -EPROBE_DEFER; 605b17336c5SHonghui Zhang } 60600c7c81fSRussell King } 607b17336c5SHonghui Zhang 6081ee9feb2SYong Wu data->larb_imu[larb_nr].dev = &plarbdev->dev; 60900c7c81fSRussell King component_match_add_release(dev, &match, release_of, 61000c7c81fSRussell King compare_of, larb_spec.np); 611b17336c5SHonghui Zhang larb_nr++; 612b17336c5SHonghui Zhang } 613b17336c5SHonghui Zhang 614b17336c5SHonghui Zhang platform_set_drvdata(pdev, data); 615b17336c5SHonghui Zhang 616b17336c5SHonghui Zhang ret = mtk_iommu_hw_init(data); 617b17336c5SHonghui Zhang if (ret) 618b17336c5SHonghui Zhang return ret; 619b17336c5SHonghui Zhang 6206f66ea09SJoerg Roedel ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 6216f66ea09SJoerg Roedel dev_name(&pdev->dev)); 6226f66ea09SJoerg Roedel if (ret) 6236f66ea09SJoerg Roedel return ret; 6246f66ea09SJoerg Roedel 6256f66ea09SJoerg Roedel iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); 6266f66ea09SJoerg Roedel 6276f66ea09SJoerg Roedel ret = iommu_device_register(&data->iommu); 6286f66ea09SJoerg Roedel if (ret) 6296f66ea09SJoerg Roedel return ret; 6306f66ea09SJoerg Roedel 631b17336c5SHonghui Zhang if (!iommu_present(&platform_bus_type)) 632b17336c5SHonghui Zhang bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 633b17336c5SHonghui Zhang 634b17336c5SHonghui Zhang return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 635b17336c5SHonghui Zhang } 636b17336c5SHonghui Zhang 637b17336c5SHonghui Zhang static int mtk_iommu_remove(struct platform_device *pdev) 638b17336c5SHonghui Zhang { 639b17336c5SHonghui Zhang struct mtk_iommu_data *data = platform_get_drvdata(pdev); 640b17336c5SHonghui Zhang 6416f66ea09SJoerg Roedel iommu_device_sysfs_remove(&data->iommu); 6426f66ea09SJoerg Roedel iommu_device_unregister(&data->iommu); 6436f66ea09SJoerg Roedel 644b17336c5SHonghui Zhang if (iommu_present(&platform_bus_type)) 645b17336c5SHonghui Zhang bus_set_iommu(&platform_bus_type, NULL); 646b17336c5SHonghui Zhang 647b17336c5SHonghui Zhang clk_disable_unprepare(data->bclk); 648b17336c5SHonghui Zhang devm_free_irq(&pdev->dev, data->irq, data); 649b17336c5SHonghui Zhang component_master_del(&pdev->dev, &mtk_iommu_com_ops); 650b17336c5SHonghui Zhang return 0; 651b17336c5SHonghui Zhang } 652b17336c5SHonghui Zhang 653b17336c5SHonghui Zhang static int __maybe_unused mtk_iommu_suspend(struct device *dev) 654b17336c5SHonghui Zhang { 655b17336c5SHonghui Zhang struct mtk_iommu_data *data = dev_get_drvdata(dev); 656b17336c5SHonghui Zhang struct mtk_iommu_suspend_reg *reg = &data->reg; 657b17336c5SHonghui Zhang void __iomem *base = data->base; 658b17336c5SHonghui Zhang 659b17336c5SHonghui Zhang reg->standard_axi_mode = readl_relaxed(base + 660b17336c5SHonghui Zhang REG_MMU_STANDARD_AXI_MODE); 661b17336c5SHonghui Zhang reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); 662b17336c5SHonghui Zhang reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 663b17336c5SHonghui Zhang reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); 664b17336c5SHonghui Zhang return 0; 665b17336c5SHonghui Zhang } 666b17336c5SHonghui Zhang 667b17336c5SHonghui Zhang static int __maybe_unused mtk_iommu_resume(struct device *dev) 668b17336c5SHonghui Zhang { 669b17336c5SHonghui Zhang struct mtk_iommu_data *data = dev_get_drvdata(dev); 670b17336c5SHonghui Zhang struct mtk_iommu_suspend_reg *reg = &data->reg; 671b17336c5SHonghui Zhang void __iomem *base = data->base; 672b17336c5SHonghui Zhang 673b17336c5SHonghui Zhang writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); 674b17336c5SHonghui Zhang writel_relaxed(reg->standard_axi_mode, 675b17336c5SHonghui Zhang base + REG_MMU_STANDARD_AXI_MODE); 676b17336c5SHonghui Zhang writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); 677b17336c5SHonghui Zhang writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 678b17336c5SHonghui Zhang writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); 679b17336c5SHonghui Zhang writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); 680b17336c5SHonghui Zhang return 0; 681b17336c5SHonghui Zhang } 682b17336c5SHonghui Zhang 683131bc8ebSJoerg Roedel static const struct dev_pm_ops mtk_iommu_pm_ops = { 684b17336c5SHonghui Zhang SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) 685b17336c5SHonghui Zhang }; 686b17336c5SHonghui Zhang 687b17336c5SHonghui Zhang static struct platform_driver mtk_iommu_driver = { 688b17336c5SHonghui Zhang .probe = mtk_iommu_probe, 689b17336c5SHonghui Zhang .remove = mtk_iommu_remove, 690b17336c5SHonghui Zhang .driver = { 691395df08dSMatthias Brugger .name = "mtk-iommu-v1", 692b17336c5SHonghui Zhang .of_match_table = mtk_iommu_of_ids, 693b17336c5SHonghui Zhang .pm = &mtk_iommu_pm_ops, 694b17336c5SHonghui Zhang } 695b17336c5SHonghui Zhang }; 696*8de000cfSYong Wu module_platform_driver(mtk_iommu_driver); 697b17336c5SHonghui Zhang 698*8de000cfSYong Wu MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations"); 699*8de000cfSYong Wu MODULE_LICENSE("GPL v2"); 700