1b17336c5SHonghui Zhang /* 2b17336c5SHonghui Zhang * Copyright (c) 2015-2016 MediaTek Inc. 3b17336c5SHonghui Zhang * Author: Honghui Zhang <honghui.zhang@mediatek.com> 4b17336c5SHonghui Zhang * 5b17336c5SHonghui Zhang * Based on driver/iommu/mtk_iommu.c 6b17336c5SHonghui Zhang * 7b17336c5SHonghui Zhang * This program is free software; you can redistribute it and/or modify 8b17336c5SHonghui Zhang * it under the terms of the GNU General Public License version 2 as 9b17336c5SHonghui Zhang * published by the Free Software Foundation. 10b17336c5SHonghui Zhang * 11b17336c5SHonghui Zhang * This program is distributed in the hope that it will be useful, 12b17336c5SHonghui Zhang * but WITHOUT ANY WARRANTY; without even the implied warranty of 13b17336c5SHonghui Zhang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14b17336c5SHonghui Zhang * GNU General Public License for more details. 15b17336c5SHonghui Zhang */ 1657c8a661SMike Rapoport #include <linux/memblock.h> 17b17336c5SHonghui Zhang #include <linux/bug.h> 18b17336c5SHonghui Zhang #include <linux/clk.h> 19b17336c5SHonghui Zhang #include <linux/component.h> 20b17336c5SHonghui Zhang #include <linux/device.h> 21745b6e74SArnd Bergmann #include <linux/dma-mapping.h> 22b17336c5SHonghui Zhang #include <linux/dma-iommu.h> 23b17336c5SHonghui Zhang #include <linux/err.h> 24b17336c5SHonghui Zhang #include <linux/interrupt.h> 25b17336c5SHonghui Zhang #include <linux/io.h> 26b17336c5SHonghui Zhang #include <linux/iommu.h> 27b17336c5SHonghui Zhang #include <linux/iopoll.h> 28b17336c5SHonghui Zhang #include <linux/list.h> 29b17336c5SHonghui Zhang #include <linux/of_address.h> 30b17336c5SHonghui Zhang #include <linux/of_iommu.h> 31b17336c5SHonghui Zhang #include <linux/of_irq.h> 32b17336c5SHonghui Zhang #include <linux/of_platform.h> 33b17336c5SHonghui Zhang #include <linux/platform_device.h> 34b17336c5SHonghui Zhang #include <linux/slab.h> 35b17336c5SHonghui Zhang #include <linux/spinlock.h> 36b17336c5SHonghui Zhang #include <asm/barrier.h> 37b17336c5SHonghui Zhang #include <asm/dma-iommu.h> 38b17336c5SHonghui Zhang #include <linux/module.h> 39b17336c5SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 40b17336c5SHonghui Zhang #include <soc/mediatek/smi.h> 41b17336c5SHonghui Zhang #include "mtk_iommu.h" 42b17336c5SHonghui Zhang 43b17336c5SHonghui Zhang #define REG_MMU_PT_BASE_ADDR 0x000 44b17336c5SHonghui Zhang 45b17336c5SHonghui Zhang #define F_ALL_INVLD 0x2 46b17336c5SHonghui Zhang #define F_MMU_INV_RANGE 0x1 47b17336c5SHonghui Zhang #define F_INVLD_EN0 BIT(0) 48b17336c5SHonghui Zhang #define F_INVLD_EN1 BIT(1) 49b17336c5SHonghui Zhang 50b17336c5SHonghui Zhang #define F_MMU_FAULT_VA_MSK 0xfffff000 51b17336c5SHonghui Zhang #define MTK_PROTECT_PA_ALIGN 128 52b17336c5SHonghui Zhang 53b17336c5SHonghui Zhang #define REG_MMU_CTRL_REG 0x210 54b17336c5SHonghui Zhang #define F_MMU_CTRL_COHERENT_EN BIT(8) 55b17336c5SHonghui Zhang #define REG_MMU_IVRP_PADDR 0x214 56b17336c5SHonghui Zhang #define REG_MMU_INT_CONTROL 0x220 57b17336c5SHonghui Zhang #define F_INT_TRANSLATION_FAULT BIT(0) 58b17336c5SHonghui Zhang #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 59b17336c5SHonghui Zhang #define F_INT_INVALID_PA_FAULT BIT(2) 60b17336c5SHonghui Zhang #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 61b17336c5SHonghui Zhang #define F_INT_TABLE_WALK_FAULT BIT(4) 62b17336c5SHonghui Zhang #define F_INT_TLB_MISS_FAULT BIT(5) 63b17336c5SHonghui Zhang #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) 64b17336c5SHonghui Zhang #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) 65b17336c5SHonghui Zhang 66b17336c5SHonghui Zhang #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) 67b17336c5SHonghui Zhang #define F_INT_CLR_BIT BIT(12) 68b17336c5SHonghui Zhang 69b17336c5SHonghui Zhang #define REG_MMU_FAULT_ST 0x224 70b17336c5SHonghui Zhang #define REG_MMU_FAULT_VA 0x228 71b17336c5SHonghui Zhang #define REG_MMU_INVLD_PA 0x22C 72b17336c5SHonghui Zhang #define REG_MMU_INT_ID 0x388 73b17336c5SHonghui Zhang #define REG_MMU_INVALIDATE 0x5c0 74b17336c5SHonghui Zhang #define REG_MMU_INVLD_START_A 0x5c4 75b17336c5SHonghui Zhang #define REG_MMU_INVLD_END_A 0x5c8 76b17336c5SHonghui Zhang 77b17336c5SHonghui Zhang #define REG_MMU_INV_SEL 0x5d8 78b17336c5SHonghui Zhang #define REG_MMU_STANDARD_AXI_MODE 0x5e8 79b17336c5SHonghui Zhang 80b17336c5SHonghui Zhang #define REG_MMU_DCM 0x5f0 81b17336c5SHonghui Zhang #define F_MMU_DCM_ON BIT(1) 82b17336c5SHonghui Zhang #define REG_MMU_CPE_DONE 0x60c 83b17336c5SHonghui Zhang #define F_DESC_VALID 0x2 84b17336c5SHonghui Zhang #define F_DESC_NONSEC BIT(3) 85b17336c5SHonghui Zhang #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) 86b17336c5SHonghui Zhang #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) 87b17336c5SHonghui Zhang /* MTK generation one iommu HW only support 4K size mapping */ 88b17336c5SHonghui Zhang #define MT2701_IOMMU_PAGE_SHIFT 12 89b17336c5SHonghui Zhang #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) 90b17336c5SHonghui Zhang 91b17336c5SHonghui Zhang /* 92b17336c5SHonghui Zhang * MTK m4u support 4GB iova address space, and only support 4K page 93b17336c5SHonghui Zhang * mapping. So the pagetable size should be exactly as 4M. 94b17336c5SHonghui Zhang */ 95b17336c5SHonghui Zhang #define M2701_IOMMU_PGT_SIZE SZ_4M 96b17336c5SHonghui Zhang 97b17336c5SHonghui Zhang struct mtk_iommu_domain { 98b17336c5SHonghui Zhang spinlock_t pgtlock; /* lock for page table */ 99b17336c5SHonghui Zhang struct iommu_domain domain; 100b17336c5SHonghui Zhang u32 *pgt_va; 101b17336c5SHonghui Zhang dma_addr_t pgt_pa; 102b17336c5SHonghui Zhang struct mtk_iommu_data *data; 103b17336c5SHonghui Zhang }; 104b17336c5SHonghui Zhang 105b17336c5SHonghui Zhang static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 106b17336c5SHonghui Zhang { 107b17336c5SHonghui Zhang return container_of(dom, struct mtk_iommu_domain, domain); 108b17336c5SHonghui Zhang } 109b17336c5SHonghui Zhang 110b17336c5SHonghui Zhang static const int mt2701_m4u_in_larb[] = { 111b17336c5SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 112b17336c5SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 113b17336c5SHonghui Zhang }; 114b17336c5SHonghui Zhang 115b17336c5SHonghui Zhang static inline int mt2701_m4u_to_larb(int id) 116b17336c5SHonghui Zhang { 117b17336c5SHonghui Zhang int i; 118b17336c5SHonghui Zhang 119b17336c5SHonghui Zhang for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) 120b17336c5SHonghui Zhang if ((id) >= mt2701_m4u_in_larb[i]) 121b17336c5SHonghui Zhang return i; 122b17336c5SHonghui Zhang 123b17336c5SHonghui Zhang return 0; 124b17336c5SHonghui Zhang } 125b17336c5SHonghui Zhang 126b17336c5SHonghui Zhang static inline int mt2701_m4u_to_port(int id) 127b17336c5SHonghui Zhang { 128b17336c5SHonghui Zhang int larb = mt2701_m4u_to_larb(id); 129b17336c5SHonghui Zhang 130b17336c5SHonghui Zhang return id - mt2701_m4u_in_larb[larb]; 131b17336c5SHonghui Zhang } 132b17336c5SHonghui Zhang 133b17336c5SHonghui Zhang static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 134b17336c5SHonghui Zhang { 135b17336c5SHonghui Zhang writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 136b17336c5SHonghui Zhang data->base + REG_MMU_INV_SEL); 137b17336c5SHonghui Zhang writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 138b17336c5SHonghui Zhang wmb(); /* Make sure the tlb flush all done */ 139b17336c5SHonghui Zhang } 140b17336c5SHonghui Zhang 141b17336c5SHonghui Zhang static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data, 142b17336c5SHonghui Zhang unsigned long iova, size_t size) 143b17336c5SHonghui Zhang { 144b17336c5SHonghui Zhang int ret; 145b17336c5SHonghui Zhang u32 tmp; 146b17336c5SHonghui Zhang 147b17336c5SHonghui Zhang writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 148b17336c5SHonghui Zhang data->base + REG_MMU_INV_SEL); 149b17336c5SHonghui Zhang writel_relaxed(iova & F_MMU_FAULT_VA_MSK, 150b17336c5SHonghui Zhang data->base + REG_MMU_INVLD_START_A); 151b17336c5SHonghui Zhang writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, 152b17336c5SHonghui Zhang data->base + REG_MMU_INVLD_END_A); 153b17336c5SHonghui Zhang writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); 154b17336c5SHonghui Zhang 155b17336c5SHonghui Zhang ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 156b17336c5SHonghui Zhang tmp, tmp != 0, 10, 100000); 157b17336c5SHonghui Zhang if (ret) { 158b17336c5SHonghui Zhang dev_warn(data->dev, 159b17336c5SHonghui Zhang "Partial TLB flush timed out, falling back to full flush\n"); 160b17336c5SHonghui Zhang mtk_iommu_tlb_flush_all(data); 161b17336c5SHonghui Zhang } 162b17336c5SHonghui Zhang /* Clear the CPE status */ 163b17336c5SHonghui Zhang writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 164b17336c5SHonghui Zhang } 165b17336c5SHonghui Zhang 166b17336c5SHonghui Zhang static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 167b17336c5SHonghui Zhang { 168b17336c5SHonghui Zhang struct mtk_iommu_data *data = dev_id; 169b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = data->m4u_dom; 170b17336c5SHonghui Zhang u32 int_state, regval, fault_iova, fault_pa; 171b17336c5SHonghui Zhang unsigned int fault_larb, fault_port; 172b17336c5SHonghui Zhang 173b17336c5SHonghui Zhang /* Read error information from registers */ 174b17336c5SHonghui Zhang int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); 175b17336c5SHonghui Zhang fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 176b17336c5SHonghui Zhang 177b17336c5SHonghui Zhang fault_iova &= F_MMU_FAULT_VA_MSK; 178b17336c5SHonghui Zhang fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 179b17336c5SHonghui Zhang regval = readl_relaxed(data->base + REG_MMU_INT_ID); 180b17336c5SHonghui Zhang fault_larb = MT2701_M4U_TF_LARB(regval); 181b17336c5SHonghui Zhang fault_port = MT2701_M4U_TF_PORT(regval); 182b17336c5SHonghui Zhang 183b17336c5SHonghui Zhang /* 184b17336c5SHonghui Zhang * MTK v1 iommu HW could not determine whether the fault is read or 185b17336c5SHonghui Zhang * write fault, report as read fault. 186b17336c5SHonghui Zhang */ 187b17336c5SHonghui Zhang if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 188b17336c5SHonghui Zhang IOMMU_FAULT_READ)) 189b17336c5SHonghui Zhang dev_err_ratelimited(data->dev, 190b17336c5SHonghui Zhang "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", 191b17336c5SHonghui Zhang int_state, fault_iova, fault_pa, 192b17336c5SHonghui Zhang fault_larb, fault_port); 193b17336c5SHonghui Zhang 194b17336c5SHonghui Zhang /* Interrupt clear */ 195b17336c5SHonghui Zhang regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); 196b17336c5SHonghui Zhang regval |= F_INT_CLR_BIT; 197b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 198b17336c5SHonghui Zhang 199b17336c5SHonghui Zhang mtk_iommu_tlb_flush_all(data); 200b17336c5SHonghui Zhang 201b17336c5SHonghui Zhang return IRQ_HANDLED; 202b17336c5SHonghui Zhang } 203b17336c5SHonghui Zhang 204b17336c5SHonghui Zhang static void mtk_iommu_config(struct mtk_iommu_data *data, 205b17336c5SHonghui Zhang struct device *dev, bool enable) 206b17336c5SHonghui Zhang { 207b17336c5SHonghui Zhang struct mtk_smi_larb_iommu *larb_mmu; 208b17336c5SHonghui Zhang unsigned int larbid, portid; 20984672f19SRobin Murphy struct iommu_fwspec *fwspec = dev->iommu_fwspec; 21084672f19SRobin Murphy int i; 211b17336c5SHonghui Zhang 21284672f19SRobin Murphy for (i = 0; i < fwspec->num_ids; ++i) { 21384672f19SRobin Murphy larbid = mt2701_m4u_to_larb(fwspec->ids[i]); 21484672f19SRobin Murphy portid = mt2701_m4u_to_port(fwspec->ids[i]); 215b17336c5SHonghui Zhang larb_mmu = &data->smi_imu.larb_imu[larbid]; 216b17336c5SHonghui Zhang 217b17336c5SHonghui Zhang dev_dbg(dev, "%s iommu port: %d\n", 218b17336c5SHonghui Zhang enable ? "enable" : "disable", portid); 219b17336c5SHonghui Zhang 220b17336c5SHonghui Zhang if (enable) 221b17336c5SHonghui Zhang larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 222b17336c5SHonghui Zhang else 223b17336c5SHonghui Zhang larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 224b17336c5SHonghui Zhang } 225b17336c5SHonghui Zhang } 226b17336c5SHonghui Zhang 227b17336c5SHonghui Zhang static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data) 228b17336c5SHonghui Zhang { 229b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = data->m4u_dom; 230b17336c5SHonghui Zhang 231b17336c5SHonghui Zhang spin_lock_init(&dom->pgtlock); 232b17336c5SHonghui Zhang 233b17336c5SHonghui Zhang dom->pgt_va = dma_zalloc_coherent(data->dev, 234b17336c5SHonghui Zhang M2701_IOMMU_PGT_SIZE, 235b17336c5SHonghui Zhang &dom->pgt_pa, GFP_KERNEL); 236b17336c5SHonghui Zhang if (!dom->pgt_va) 237b17336c5SHonghui Zhang return -ENOMEM; 238b17336c5SHonghui Zhang 239b17336c5SHonghui Zhang writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); 240b17336c5SHonghui Zhang 241b17336c5SHonghui Zhang dom->data = data; 242b17336c5SHonghui Zhang 243b17336c5SHonghui Zhang return 0; 244b17336c5SHonghui Zhang } 245b17336c5SHonghui Zhang 246b17336c5SHonghui Zhang static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 247b17336c5SHonghui Zhang { 248b17336c5SHonghui Zhang struct mtk_iommu_domain *dom; 249b17336c5SHonghui Zhang 250b17336c5SHonghui Zhang if (type != IOMMU_DOMAIN_UNMANAGED) 251b17336c5SHonghui Zhang return NULL; 252b17336c5SHonghui Zhang 253b17336c5SHonghui Zhang dom = kzalloc(sizeof(*dom), GFP_KERNEL); 254b17336c5SHonghui Zhang if (!dom) 255b17336c5SHonghui Zhang return NULL; 256b17336c5SHonghui Zhang 257b17336c5SHonghui Zhang return &dom->domain; 258b17336c5SHonghui Zhang } 259b17336c5SHonghui Zhang 260b17336c5SHonghui Zhang static void mtk_iommu_domain_free(struct iommu_domain *domain) 261b17336c5SHonghui Zhang { 262b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 263b17336c5SHonghui Zhang struct mtk_iommu_data *data = dom->data; 264b17336c5SHonghui Zhang 265b17336c5SHonghui Zhang dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 266b17336c5SHonghui Zhang dom->pgt_va, dom->pgt_pa); 267b17336c5SHonghui Zhang kfree(to_mtk_domain(domain)); 268b17336c5SHonghui Zhang } 269b17336c5SHonghui Zhang 270b17336c5SHonghui Zhang static int mtk_iommu_attach_device(struct iommu_domain *domain, 271b17336c5SHonghui Zhang struct device *dev) 272b17336c5SHonghui Zhang { 273b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 27484672f19SRobin Murphy struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; 275b17336c5SHonghui Zhang int ret; 276b17336c5SHonghui Zhang 27784672f19SRobin Murphy if (!data) 278b17336c5SHonghui Zhang return -ENODEV; 279b17336c5SHonghui Zhang 280b17336c5SHonghui Zhang if (!data->m4u_dom) { 281b17336c5SHonghui Zhang data->m4u_dom = dom; 282b17336c5SHonghui Zhang ret = mtk_iommu_domain_finalise(data); 283b17336c5SHonghui Zhang if (ret) { 284b17336c5SHonghui Zhang data->m4u_dom = NULL; 285b17336c5SHonghui Zhang return ret; 286b17336c5SHonghui Zhang } 287b17336c5SHonghui Zhang } 288b17336c5SHonghui Zhang 289b17336c5SHonghui Zhang mtk_iommu_config(data, dev, true); 290b17336c5SHonghui Zhang return 0; 291b17336c5SHonghui Zhang } 292b17336c5SHonghui Zhang 293b17336c5SHonghui Zhang static void mtk_iommu_detach_device(struct iommu_domain *domain, 294b17336c5SHonghui Zhang struct device *dev) 295b17336c5SHonghui Zhang { 29684672f19SRobin Murphy struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; 297b17336c5SHonghui Zhang 29884672f19SRobin Murphy if (!data) 299b17336c5SHonghui Zhang return; 300b17336c5SHonghui Zhang 301b17336c5SHonghui Zhang mtk_iommu_config(data, dev, false); 302b17336c5SHonghui Zhang } 303b17336c5SHonghui Zhang 304b17336c5SHonghui Zhang static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 305b17336c5SHonghui Zhang phys_addr_t paddr, size_t size, int prot) 306b17336c5SHonghui Zhang { 307b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 308b17336c5SHonghui Zhang unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 309b17336c5SHonghui Zhang unsigned long flags; 310b17336c5SHonghui Zhang unsigned int i; 311b17336c5SHonghui Zhang u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 312b17336c5SHonghui Zhang u32 pabase = (u32)paddr; 313b17336c5SHonghui Zhang int map_size = 0; 314b17336c5SHonghui Zhang 315b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags); 316b17336c5SHonghui Zhang for (i = 0; i < page_num; i++) { 317b17336c5SHonghui Zhang if (pgt_base_iova[i]) { 318b17336c5SHonghui Zhang memset(pgt_base_iova, 0, i * sizeof(u32)); 319b17336c5SHonghui Zhang break; 320b17336c5SHonghui Zhang } 321b17336c5SHonghui Zhang pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; 322b17336c5SHonghui Zhang pabase += MT2701_IOMMU_PAGE_SIZE; 323b17336c5SHonghui Zhang map_size += MT2701_IOMMU_PAGE_SIZE; 324b17336c5SHonghui Zhang } 325b17336c5SHonghui Zhang 326b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags); 327b17336c5SHonghui Zhang 328b17336c5SHonghui Zhang mtk_iommu_tlb_flush_range(dom->data, iova, size); 329b17336c5SHonghui Zhang 330b17336c5SHonghui Zhang return map_size == size ? 0 : -EEXIST; 331b17336c5SHonghui Zhang } 332b17336c5SHonghui Zhang 333b17336c5SHonghui Zhang static size_t mtk_iommu_unmap(struct iommu_domain *domain, 334b17336c5SHonghui Zhang unsigned long iova, size_t size) 335b17336c5SHonghui Zhang { 336b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 337b17336c5SHonghui Zhang unsigned long flags; 338b17336c5SHonghui Zhang u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 339b17336c5SHonghui Zhang unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT; 340b17336c5SHonghui Zhang 341b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags); 342b17336c5SHonghui Zhang memset(pgt_base_iova, 0, page_num * sizeof(u32)); 343b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags); 344b17336c5SHonghui Zhang 345b17336c5SHonghui Zhang mtk_iommu_tlb_flush_range(dom->data, iova, size); 346b17336c5SHonghui Zhang 347b17336c5SHonghui Zhang return size; 348b17336c5SHonghui Zhang } 349b17336c5SHonghui Zhang 350b17336c5SHonghui Zhang static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 351b17336c5SHonghui Zhang dma_addr_t iova) 352b17336c5SHonghui Zhang { 353b17336c5SHonghui Zhang struct mtk_iommu_domain *dom = to_mtk_domain(domain); 354b17336c5SHonghui Zhang unsigned long flags; 355b17336c5SHonghui Zhang phys_addr_t pa; 356b17336c5SHonghui Zhang 357b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags); 358b17336c5SHonghui Zhang pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); 359b17336c5SHonghui Zhang pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); 360b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags); 361b17336c5SHonghui Zhang 362b17336c5SHonghui Zhang return pa; 363b17336c5SHonghui Zhang } 364b17336c5SHonghui Zhang 36584672f19SRobin Murphy static struct iommu_ops mtk_iommu_ops; 36684672f19SRobin Murphy 367b17336c5SHonghui Zhang /* 368b17336c5SHonghui Zhang * MTK generation one iommu HW only support one iommu domain, and all the client 369b17336c5SHonghui Zhang * sharing the same iova address space. 370b17336c5SHonghui Zhang */ 371b17336c5SHonghui Zhang static int mtk_iommu_create_mapping(struct device *dev, 372b17336c5SHonghui Zhang struct of_phandle_args *args) 373b17336c5SHonghui Zhang { 37484672f19SRobin Murphy struct mtk_iommu_data *data; 375b17336c5SHonghui Zhang struct platform_device *m4updev; 376b17336c5SHonghui Zhang struct dma_iommu_mapping *mtk_mapping; 377b17336c5SHonghui Zhang struct device *m4udev; 378b17336c5SHonghui Zhang int ret; 379b17336c5SHonghui Zhang 380b17336c5SHonghui Zhang if (args->args_count != 1) { 381b17336c5SHonghui Zhang dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 382b17336c5SHonghui Zhang args->args_count); 383b17336c5SHonghui Zhang return -EINVAL; 384b17336c5SHonghui Zhang } 385b17336c5SHonghui Zhang 38684672f19SRobin Murphy if (!dev->iommu_fwspec) { 38784672f19SRobin Murphy ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops); 38884672f19SRobin Murphy if (ret) 38984672f19SRobin Murphy return ret; 39084672f19SRobin Murphy } else if (dev->iommu_fwspec->ops != &mtk_iommu_ops) { 39184672f19SRobin Murphy return -EINVAL; 39284672f19SRobin Murphy } 39384672f19SRobin Murphy 39484672f19SRobin Murphy if (!dev->iommu_fwspec->iommu_priv) { 395b17336c5SHonghui Zhang /* Get the m4u device */ 396b17336c5SHonghui Zhang m4updev = of_find_device_by_node(args->np); 397b17336c5SHonghui Zhang if (WARN_ON(!m4updev)) 398b17336c5SHonghui Zhang return -EINVAL; 399b17336c5SHonghui Zhang 40084672f19SRobin Murphy dev->iommu_fwspec->iommu_priv = platform_get_drvdata(m4updev); 401b17336c5SHonghui Zhang } 402b17336c5SHonghui Zhang 40384672f19SRobin Murphy ret = iommu_fwspec_add_ids(dev, args->args, 1); 40484672f19SRobin Murphy if (ret) 40584672f19SRobin Murphy return ret; 406b17336c5SHonghui Zhang 40784672f19SRobin Murphy data = dev->iommu_fwspec->iommu_priv; 40884672f19SRobin Murphy m4udev = data->dev; 409b17336c5SHonghui Zhang mtk_mapping = m4udev->archdata.iommu; 410b17336c5SHonghui Zhang if (!mtk_mapping) { 411b17336c5SHonghui Zhang /* MTK iommu support 4GB iova address space. */ 412b17336c5SHonghui Zhang mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, 413b17336c5SHonghui Zhang 0, 1ULL << 32); 41484672f19SRobin Murphy if (IS_ERR(mtk_mapping)) 41584672f19SRobin Murphy return PTR_ERR(mtk_mapping); 41684672f19SRobin Murphy 417b17336c5SHonghui Zhang m4udev->archdata.iommu = mtk_mapping; 418b17336c5SHonghui Zhang } 419b17336c5SHonghui Zhang 420b17336c5SHonghui Zhang return 0; 421b17336c5SHonghui Zhang } 422b17336c5SHonghui Zhang 423b17336c5SHonghui Zhang static int mtk_iommu_add_device(struct device *dev) 424b17336c5SHonghui Zhang { 425f3e827d7SYong Wu struct dma_iommu_mapping *mtk_mapping; 426b17336c5SHonghui Zhang struct of_phandle_args iommu_spec; 427b17336c5SHonghui Zhang struct of_phandle_iterator it; 4286f66ea09SJoerg Roedel struct mtk_iommu_data *data; 4296f66ea09SJoerg Roedel struct iommu_group *group; 430b17336c5SHonghui Zhang int err; 431b17336c5SHonghui Zhang 432b17336c5SHonghui Zhang of_for_each_phandle(&it, err, dev->of_node, "iommus", 433b17336c5SHonghui Zhang "#iommu-cells", 0) { 434b17336c5SHonghui Zhang int count = of_phandle_iterator_args(&it, iommu_spec.args, 435b17336c5SHonghui Zhang MAX_PHANDLE_ARGS); 436b17336c5SHonghui Zhang iommu_spec.np = of_node_get(it.node); 437b17336c5SHonghui Zhang iommu_spec.args_count = count; 438b17336c5SHonghui Zhang 439b17336c5SHonghui Zhang mtk_iommu_create_mapping(dev, &iommu_spec); 440b17336c5SHonghui Zhang of_node_put(iommu_spec.np); 441b17336c5SHonghui Zhang } 442b17336c5SHonghui Zhang 44384672f19SRobin Murphy if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops) 44484672f19SRobin Murphy return -ENODEV; /* Not a iommu client device */ 445b17336c5SHonghui Zhang 446f3e827d7SYong Wu /* 447f3e827d7SYong Wu * This is a short-term bodge because the ARM DMA code doesn't 448f3e827d7SYong Wu * understand multi-device groups, but we have to call into it 449f3e827d7SYong Wu * successfully (and not just rely on a normal IOMMU API attach 450f3e827d7SYong Wu * here) in order to set the correct DMA API ops on @dev. 451f3e827d7SYong Wu */ 452f3e827d7SYong Wu group = iommu_group_alloc(); 453b17336c5SHonghui Zhang if (IS_ERR(group)) 454b17336c5SHonghui Zhang return PTR_ERR(group); 455b17336c5SHonghui Zhang 456f3e827d7SYong Wu err = iommu_group_add_device(group, dev); 457b17336c5SHonghui Zhang iommu_group_put(group); 458f3e827d7SYong Wu if (err) 459f3e827d7SYong Wu return err; 460f3e827d7SYong Wu 461f3e827d7SYong Wu data = dev->iommu_fwspec->iommu_priv; 462f3e827d7SYong Wu mtk_mapping = data->dev->archdata.iommu; 463f3e827d7SYong Wu err = arm_iommu_attach_device(dev, mtk_mapping); 464f3e827d7SYong Wu if (err) { 465f3e827d7SYong Wu iommu_group_remove_device(dev); 466f3e827d7SYong Wu return err; 467f3e827d7SYong Wu } 468f3e827d7SYong Wu 469f3e827d7SYong Wu return iommu_device_link(&data->iommu, dev);; 470b17336c5SHonghui Zhang } 471b17336c5SHonghui Zhang 472b17336c5SHonghui Zhang static void mtk_iommu_remove_device(struct device *dev) 473b17336c5SHonghui Zhang { 4746f66ea09SJoerg Roedel struct mtk_iommu_data *data; 4756f66ea09SJoerg Roedel 47684672f19SRobin Murphy if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops) 477b17336c5SHonghui Zhang return; 478b17336c5SHonghui Zhang 4796f66ea09SJoerg Roedel data = dev->iommu_fwspec->iommu_priv; 4806f66ea09SJoerg Roedel iommu_device_unlink(&data->iommu, dev); 4816f66ea09SJoerg Roedel 482b17336c5SHonghui Zhang iommu_group_remove_device(dev); 48384672f19SRobin Murphy iommu_fwspec_free(dev); 484b17336c5SHonghui Zhang } 485b17336c5SHonghui Zhang 486b17336c5SHonghui Zhang static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 487b17336c5SHonghui Zhang { 488b17336c5SHonghui Zhang u32 regval; 489b17336c5SHonghui Zhang int ret; 490b17336c5SHonghui Zhang 491b17336c5SHonghui Zhang ret = clk_prepare_enable(data->bclk); 492b17336c5SHonghui Zhang if (ret) { 493b17336c5SHonghui Zhang dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 494b17336c5SHonghui Zhang return ret; 495b17336c5SHonghui Zhang } 496b17336c5SHonghui Zhang 497b17336c5SHonghui Zhang regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); 498b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 499b17336c5SHonghui Zhang 500b17336c5SHonghui Zhang regval = F_INT_TRANSLATION_FAULT | 501b17336c5SHonghui Zhang F_INT_MAIN_MULTI_HIT_FAULT | 502b17336c5SHonghui Zhang F_INT_INVALID_PA_FAULT | 503b17336c5SHonghui Zhang F_INT_ENTRY_REPLACEMENT_FAULT | 504b17336c5SHonghui Zhang F_INT_TABLE_WALK_FAULT | 505b17336c5SHonghui Zhang F_INT_TLB_MISS_FAULT | 506b17336c5SHonghui Zhang F_INT_PFH_DMA_FIFO_OVERFLOW | 507b17336c5SHonghui Zhang F_INT_MISS_DMA_FIFO_OVERFLOW; 508b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 509b17336c5SHonghui Zhang 510b17336c5SHonghui Zhang /* protect memory,hw will write here while translation fault */ 511b17336c5SHonghui Zhang writel_relaxed(data->protect_base, 512b17336c5SHonghui Zhang data->base + REG_MMU_IVRP_PADDR); 513b17336c5SHonghui Zhang 514b17336c5SHonghui Zhang writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); 515b17336c5SHonghui Zhang 516b17336c5SHonghui Zhang if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 517b17336c5SHonghui Zhang dev_name(data->dev), (void *)data)) { 518b17336c5SHonghui Zhang writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 519b17336c5SHonghui Zhang clk_disable_unprepare(data->bclk); 520b17336c5SHonghui Zhang dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 521b17336c5SHonghui Zhang return -ENODEV; 522b17336c5SHonghui Zhang } 523b17336c5SHonghui Zhang 524b17336c5SHonghui Zhang return 0; 525b17336c5SHonghui Zhang } 526b17336c5SHonghui Zhang 527b17336c5SHonghui Zhang static struct iommu_ops mtk_iommu_ops = { 528b17336c5SHonghui Zhang .domain_alloc = mtk_iommu_domain_alloc, 529b17336c5SHonghui Zhang .domain_free = mtk_iommu_domain_free, 530b17336c5SHonghui Zhang .attach_dev = mtk_iommu_attach_device, 531b17336c5SHonghui Zhang .detach_dev = mtk_iommu_detach_device, 532b17336c5SHonghui Zhang .map = mtk_iommu_map, 533b17336c5SHonghui Zhang .unmap = mtk_iommu_unmap, 534b17336c5SHonghui Zhang .iova_to_phys = mtk_iommu_iova_to_phys, 535b17336c5SHonghui Zhang .add_device = mtk_iommu_add_device, 536b17336c5SHonghui Zhang .remove_device = mtk_iommu_remove_device, 537b17336c5SHonghui Zhang .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT, 538b17336c5SHonghui Zhang }; 539b17336c5SHonghui Zhang 540b17336c5SHonghui Zhang static const struct of_device_id mtk_iommu_of_ids[] = { 541b17336c5SHonghui Zhang { .compatible = "mediatek,mt2701-m4u", }, 542b17336c5SHonghui Zhang {} 543b17336c5SHonghui Zhang }; 544b17336c5SHonghui Zhang 545b17336c5SHonghui Zhang static const struct component_master_ops mtk_iommu_com_ops = { 546b17336c5SHonghui Zhang .bind = mtk_iommu_bind, 547b17336c5SHonghui Zhang .unbind = mtk_iommu_unbind, 548b17336c5SHonghui Zhang }; 549b17336c5SHonghui Zhang 550b17336c5SHonghui Zhang static int mtk_iommu_probe(struct platform_device *pdev) 551b17336c5SHonghui Zhang { 552b17336c5SHonghui Zhang struct mtk_iommu_data *data; 553b17336c5SHonghui Zhang struct device *dev = &pdev->dev; 554b17336c5SHonghui Zhang struct resource *res; 555b17336c5SHonghui Zhang struct component_match *match = NULL; 556b17336c5SHonghui Zhang struct of_phandle_args larb_spec; 557b17336c5SHonghui Zhang struct of_phandle_iterator it; 558b17336c5SHonghui Zhang void *protect; 559b17336c5SHonghui Zhang int larb_nr, ret, err; 560b17336c5SHonghui Zhang 561b17336c5SHonghui Zhang data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 562b17336c5SHonghui Zhang if (!data) 563b17336c5SHonghui Zhang return -ENOMEM; 564b17336c5SHonghui Zhang 565b17336c5SHonghui Zhang data->dev = dev; 566b17336c5SHonghui Zhang 567b17336c5SHonghui Zhang /* Protect memory. HW will access here while translation fault.*/ 568b17336c5SHonghui Zhang protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, 569b17336c5SHonghui Zhang GFP_KERNEL | GFP_DMA); 570b17336c5SHonghui Zhang if (!protect) 571b17336c5SHonghui Zhang return -ENOMEM; 572b17336c5SHonghui Zhang data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 573b17336c5SHonghui Zhang 574b17336c5SHonghui Zhang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 575b17336c5SHonghui Zhang data->base = devm_ioremap_resource(dev, res); 576b17336c5SHonghui Zhang if (IS_ERR(data->base)) 577b17336c5SHonghui Zhang return PTR_ERR(data->base); 578b17336c5SHonghui Zhang 579b17336c5SHonghui Zhang data->irq = platform_get_irq(pdev, 0); 580b17336c5SHonghui Zhang if (data->irq < 0) 581b17336c5SHonghui Zhang return data->irq; 582b17336c5SHonghui Zhang 583b17336c5SHonghui Zhang data->bclk = devm_clk_get(dev, "bclk"); 584b17336c5SHonghui Zhang if (IS_ERR(data->bclk)) 585b17336c5SHonghui Zhang return PTR_ERR(data->bclk); 586b17336c5SHonghui Zhang 587b17336c5SHonghui Zhang larb_nr = 0; 588b17336c5SHonghui Zhang of_for_each_phandle(&it, err, dev->of_node, 589b17336c5SHonghui Zhang "mediatek,larbs", NULL, 0) { 590b17336c5SHonghui Zhang struct platform_device *plarbdev; 591b17336c5SHonghui Zhang int count = of_phandle_iterator_args(&it, larb_spec.args, 592b17336c5SHonghui Zhang MAX_PHANDLE_ARGS); 593b17336c5SHonghui Zhang 594b17336c5SHonghui Zhang if (count) 595b17336c5SHonghui Zhang continue; 596b17336c5SHonghui Zhang 597b17336c5SHonghui Zhang larb_spec.np = of_node_get(it.node); 598b17336c5SHonghui Zhang if (!of_device_is_available(larb_spec.np)) 599b17336c5SHonghui Zhang continue; 600b17336c5SHonghui Zhang 601b17336c5SHonghui Zhang plarbdev = of_find_device_by_node(larb_spec.np); 602b17336c5SHonghui Zhang if (!plarbdev) { 603b17336c5SHonghui Zhang plarbdev = of_platform_device_create( 604b17336c5SHonghui Zhang larb_spec.np, NULL, 605b17336c5SHonghui Zhang platform_bus_type.dev_root); 60600c7c81fSRussell King if (!plarbdev) { 60700c7c81fSRussell King of_node_put(larb_spec.np); 608b17336c5SHonghui Zhang return -EPROBE_DEFER; 609b17336c5SHonghui Zhang } 61000c7c81fSRussell King } 611b17336c5SHonghui Zhang 612b17336c5SHonghui Zhang data->smi_imu.larb_imu[larb_nr].dev = &plarbdev->dev; 61300c7c81fSRussell King component_match_add_release(dev, &match, release_of, 61400c7c81fSRussell King compare_of, larb_spec.np); 615b17336c5SHonghui Zhang larb_nr++; 616b17336c5SHonghui Zhang } 617b17336c5SHonghui Zhang 618b17336c5SHonghui Zhang data->smi_imu.larb_nr = larb_nr; 619b17336c5SHonghui Zhang 620b17336c5SHonghui Zhang platform_set_drvdata(pdev, data); 621b17336c5SHonghui Zhang 622b17336c5SHonghui Zhang ret = mtk_iommu_hw_init(data); 623b17336c5SHonghui Zhang if (ret) 624b17336c5SHonghui Zhang return ret; 625b17336c5SHonghui Zhang 6266f66ea09SJoerg Roedel ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 6276f66ea09SJoerg Roedel dev_name(&pdev->dev)); 6286f66ea09SJoerg Roedel if (ret) 6296f66ea09SJoerg Roedel return ret; 6306f66ea09SJoerg Roedel 6316f66ea09SJoerg Roedel iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); 6326f66ea09SJoerg Roedel 6336f66ea09SJoerg Roedel ret = iommu_device_register(&data->iommu); 6346f66ea09SJoerg Roedel if (ret) 6356f66ea09SJoerg Roedel return ret; 6366f66ea09SJoerg Roedel 637b17336c5SHonghui Zhang if (!iommu_present(&platform_bus_type)) 638b17336c5SHonghui Zhang bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 639b17336c5SHonghui Zhang 640b17336c5SHonghui Zhang return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 641b17336c5SHonghui Zhang } 642b17336c5SHonghui Zhang 643b17336c5SHonghui Zhang static int mtk_iommu_remove(struct platform_device *pdev) 644b17336c5SHonghui Zhang { 645b17336c5SHonghui Zhang struct mtk_iommu_data *data = platform_get_drvdata(pdev); 646b17336c5SHonghui Zhang 6476f66ea09SJoerg Roedel iommu_device_sysfs_remove(&data->iommu); 6486f66ea09SJoerg Roedel iommu_device_unregister(&data->iommu); 6496f66ea09SJoerg Roedel 650b17336c5SHonghui Zhang if (iommu_present(&platform_bus_type)) 651b17336c5SHonghui Zhang bus_set_iommu(&platform_bus_type, NULL); 652b17336c5SHonghui Zhang 653b17336c5SHonghui Zhang clk_disable_unprepare(data->bclk); 654b17336c5SHonghui Zhang devm_free_irq(&pdev->dev, data->irq, data); 655b17336c5SHonghui Zhang component_master_del(&pdev->dev, &mtk_iommu_com_ops); 656b17336c5SHonghui Zhang return 0; 657b17336c5SHonghui Zhang } 658b17336c5SHonghui Zhang 659b17336c5SHonghui Zhang static int __maybe_unused mtk_iommu_suspend(struct device *dev) 660b17336c5SHonghui Zhang { 661b17336c5SHonghui Zhang struct mtk_iommu_data *data = dev_get_drvdata(dev); 662b17336c5SHonghui Zhang struct mtk_iommu_suspend_reg *reg = &data->reg; 663b17336c5SHonghui Zhang void __iomem *base = data->base; 664b17336c5SHonghui Zhang 665b17336c5SHonghui Zhang reg->standard_axi_mode = readl_relaxed(base + 666b17336c5SHonghui Zhang REG_MMU_STANDARD_AXI_MODE); 667b17336c5SHonghui Zhang reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); 668b17336c5SHonghui Zhang reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 669b17336c5SHonghui Zhang reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); 670b17336c5SHonghui Zhang return 0; 671b17336c5SHonghui Zhang } 672b17336c5SHonghui Zhang 673b17336c5SHonghui Zhang static int __maybe_unused mtk_iommu_resume(struct device *dev) 674b17336c5SHonghui Zhang { 675b17336c5SHonghui Zhang struct mtk_iommu_data *data = dev_get_drvdata(dev); 676b17336c5SHonghui Zhang struct mtk_iommu_suspend_reg *reg = &data->reg; 677b17336c5SHonghui Zhang void __iomem *base = data->base; 678b17336c5SHonghui Zhang 679b17336c5SHonghui Zhang writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); 680b17336c5SHonghui Zhang writel_relaxed(reg->standard_axi_mode, 681b17336c5SHonghui Zhang base + REG_MMU_STANDARD_AXI_MODE); 682b17336c5SHonghui Zhang writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); 683b17336c5SHonghui Zhang writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 684b17336c5SHonghui Zhang writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); 685b17336c5SHonghui Zhang writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); 686b17336c5SHonghui Zhang return 0; 687b17336c5SHonghui Zhang } 688b17336c5SHonghui Zhang 689131bc8ebSJoerg Roedel static const struct dev_pm_ops mtk_iommu_pm_ops = { 690b17336c5SHonghui Zhang SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) 691b17336c5SHonghui Zhang }; 692b17336c5SHonghui Zhang 693b17336c5SHonghui Zhang static struct platform_driver mtk_iommu_driver = { 694b17336c5SHonghui Zhang .probe = mtk_iommu_probe, 695b17336c5SHonghui Zhang .remove = mtk_iommu_remove, 696b17336c5SHonghui Zhang .driver = { 697395df08dSMatthias Brugger .name = "mtk-iommu-v1", 698b17336c5SHonghui Zhang .of_match_table = mtk_iommu_of_ids, 699b17336c5SHonghui Zhang .pm = &mtk_iommu_pm_ops, 700b17336c5SHonghui Zhang } 701b17336c5SHonghui Zhang }; 702b17336c5SHonghui Zhang 703b17336c5SHonghui Zhang static int __init m4u_init(void) 704b17336c5SHonghui Zhang { 705b17336c5SHonghui Zhang return platform_driver_register(&mtk_iommu_driver); 706b17336c5SHonghui Zhang } 707b17336c5SHonghui Zhang 708b17336c5SHonghui Zhang static void __exit m4u_exit(void) 709b17336c5SHonghui Zhang { 710b17336c5SHonghui Zhang return platform_driver_unregister(&mtk_iommu_driver); 711b17336c5SHonghui Zhang } 712b17336c5SHonghui Zhang 713b17336c5SHonghui Zhang subsys_initcall(m4u_init); 714b17336c5SHonghui Zhang module_exit(m4u_exit); 715b17336c5SHonghui Zhang 716b17336c5SHonghui Zhang MODULE_DESCRIPTION("IOMMU API for MTK architected m4u v1 implementations"); 717b17336c5SHonghui Zhang MODULE_AUTHOR("Honghui Zhang <honghui.zhang@mediatek.com>"); 718b17336c5SHonghui Zhang MODULE_LICENSE("GPL v2"); 719