11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2b17336c5SHonghui Zhang /*
3d4cf5bbdSPaul Gortmaker * IOMMU API for MTK architected m4u v1 implementations
4d4cf5bbdSPaul Gortmaker *
5b17336c5SHonghui Zhang * Copyright (c) 2015-2016 MediaTek Inc.
6b17336c5SHonghui Zhang * Author: Honghui Zhang <honghui.zhang@mediatek.com>
7b17336c5SHonghui Zhang *
8b17336c5SHonghui Zhang * Based on driver/iommu/mtk_iommu.c
9b17336c5SHonghui Zhang */
10b17336c5SHonghui Zhang #include <linux/bug.h>
11b17336c5SHonghui Zhang #include <linux/clk.h>
12b17336c5SHonghui Zhang #include <linux/component.h>
13b17336c5SHonghui Zhang #include <linux/device.h>
14745b6e74SArnd Bergmann #include <linux/dma-mapping.h>
15b17336c5SHonghui Zhang #include <linux/err.h>
16b17336c5SHonghui Zhang #include <linux/interrupt.h>
17b17336c5SHonghui Zhang #include <linux/io.h>
18b17336c5SHonghui Zhang #include <linux/iommu.h>
19b17336c5SHonghui Zhang #include <linux/iopoll.h>
20b17336c5SHonghui Zhang #include <linux/list.h>
218de000cfSYong Wu #include <linux/module.h>
22b17336c5SHonghui Zhang #include <linux/of_address.h>
23b17336c5SHonghui Zhang #include <linux/of_irq.h>
24b17336c5SHonghui Zhang #include <linux/of_platform.h>
25b17336c5SHonghui Zhang #include <linux/platform_device.h>
26b17336c5SHonghui Zhang #include <linux/slab.h>
27b17336c5SHonghui Zhang #include <linux/spinlock.h>
28b17336c5SHonghui Zhang #include <asm/barrier.h>
29b17336c5SHonghui Zhang #include <asm/dma-iommu.h>
306a513de3SYong Wu #include <dt-bindings/memory/mtk-memory-port.h>
31b17336c5SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h>
32b17336c5SHonghui Zhang #include <soc/mediatek/smi.h>
33b17336c5SHonghui Zhang
34b17336c5SHonghui Zhang #define REG_MMU_PT_BASE_ADDR 0x000
35b17336c5SHonghui Zhang
36b17336c5SHonghui Zhang #define F_ALL_INVLD 0x2
37b17336c5SHonghui Zhang #define F_MMU_INV_RANGE 0x1
38b17336c5SHonghui Zhang #define F_INVLD_EN0 BIT(0)
39b17336c5SHonghui Zhang #define F_INVLD_EN1 BIT(1)
40b17336c5SHonghui Zhang
41b17336c5SHonghui Zhang #define F_MMU_FAULT_VA_MSK 0xfffff000
42b17336c5SHonghui Zhang #define MTK_PROTECT_PA_ALIGN 128
43b17336c5SHonghui Zhang
44b17336c5SHonghui Zhang #define REG_MMU_CTRL_REG 0x210
45b17336c5SHonghui Zhang #define F_MMU_CTRL_COHERENT_EN BIT(8)
46b17336c5SHonghui Zhang #define REG_MMU_IVRP_PADDR 0x214
47b17336c5SHonghui Zhang #define REG_MMU_INT_CONTROL 0x220
48b17336c5SHonghui Zhang #define F_INT_TRANSLATION_FAULT BIT(0)
49b17336c5SHonghui Zhang #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
50b17336c5SHonghui Zhang #define F_INT_INVALID_PA_FAULT BIT(2)
51b17336c5SHonghui Zhang #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
52b17336c5SHonghui Zhang #define F_INT_TABLE_WALK_FAULT BIT(4)
53b17336c5SHonghui Zhang #define F_INT_TLB_MISS_FAULT BIT(5)
54b17336c5SHonghui Zhang #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6)
55b17336c5SHonghui Zhang #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7)
56b17336c5SHonghui Zhang
57b17336c5SHonghui Zhang #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
58b17336c5SHonghui Zhang #define F_INT_CLR_BIT BIT(12)
59b17336c5SHonghui Zhang
60b17336c5SHonghui Zhang #define REG_MMU_FAULT_ST 0x224
61b17336c5SHonghui Zhang #define REG_MMU_FAULT_VA 0x228
62b17336c5SHonghui Zhang #define REG_MMU_INVLD_PA 0x22C
63b17336c5SHonghui Zhang #define REG_MMU_INT_ID 0x388
64b17336c5SHonghui Zhang #define REG_MMU_INVALIDATE 0x5c0
65b17336c5SHonghui Zhang #define REG_MMU_INVLD_START_A 0x5c4
66b17336c5SHonghui Zhang #define REG_MMU_INVLD_END_A 0x5c8
67b17336c5SHonghui Zhang
68b17336c5SHonghui Zhang #define REG_MMU_INV_SEL 0x5d8
69b17336c5SHonghui Zhang #define REG_MMU_STANDARD_AXI_MODE 0x5e8
70b17336c5SHonghui Zhang
71b17336c5SHonghui Zhang #define REG_MMU_DCM 0x5f0
72b17336c5SHonghui Zhang #define F_MMU_DCM_ON BIT(1)
73b17336c5SHonghui Zhang #define REG_MMU_CPE_DONE 0x60c
74b17336c5SHonghui Zhang #define F_DESC_VALID 0x2
75b17336c5SHonghui Zhang #define F_DESC_NONSEC BIT(3)
76b17336c5SHonghui Zhang #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
77b17336c5SHonghui Zhang #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF)
78b17336c5SHonghui Zhang /* MTK generation one iommu HW only support 4K size mapping */
79b17336c5SHonghui Zhang #define MT2701_IOMMU_PAGE_SHIFT 12
80b17336c5SHonghui Zhang #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT)
81de78657eSMiles Chen #define MT2701_LARB_NR_MAX 3
82b17336c5SHonghui Zhang
83b17336c5SHonghui Zhang /*
84b17336c5SHonghui Zhang * MTK m4u support 4GB iova address space, and only support 4K page
85b17336c5SHonghui Zhang * mapping. So the pagetable size should be exactly as 4M.
86b17336c5SHonghui Zhang */
87b17336c5SHonghui Zhang #define M2701_IOMMU_PGT_SIZE SZ_4M
88b17336c5SHonghui Zhang
89ad9b10e5SYong Wu struct mtk_iommu_v1_suspend_reg {
906a513de3SYong Wu u32 standard_axi_mode;
916a513de3SYong Wu u32 dcm_dis;
926a513de3SYong Wu u32 ctrl_reg;
936a513de3SYong Wu u32 int_control0;
946a513de3SYong Wu };
956a513de3SYong Wu
96ad9b10e5SYong Wu struct mtk_iommu_v1_data {
979485a04aSYong Wu void __iomem *base;
989485a04aSYong Wu int irq;
999485a04aSYong Wu struct device *dev;
1009485a04aSYong Wu struct clk *bclk;
1019485a04aSYong Wu phys_addr_t protect_base; /* protect memory base */
102ad9b10e5SYong Wu struct mtk_iommu_v1_domain *m4u_dom;
1039485a04aSYong Wu
1049485a04aSYong Wu struct iommu_device iommu;
1059485a04aSYong Wu struct dma_iommu_mapping *mapping;
1069485a04aSYong Wu struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
1079485a04aSYong Wu
108ad9b10e5SYong Wu struct mtk_iommu_v1_suspend_reg reg;
1099485a04aSYong Wu };
1109485a04aSYong Wu
111ad9b10e5SYong Wu struct mtk_iommu_v1_domain {
112b17336c5SHonghui Zhang spinlock_t pgtlock; /* lock for page table */
113b17336c5SHonghui Zhang struct iommu_domain domain;
114b17336c5SHonghui Zhang u32 *pgt_va;
115b17336c5SHonghui Zhang dma_addr_t pgt_pa;
116ad9b10e5SYong Wu struct mtk_iommu_v1_data *data;
117b17336c5SHonghui Zhang };
118b17336c5SHonghui Zhang
mtk_iommu_v1_bind(struct device * dev)119ad9b10e5SYong Wu static int mtk_iommu_v1_bind(struct device *dev)
1209485a04aSYong Wu {
121ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
1229485a04aSYong Wu
1239485a04aSYong Wu return component_bind_all(dev, &data->larb_imu);
1249485a04aSYong Wu }
1259485a04aSYong Wu
mtk_iommu_v1_unbind(struct device * dev)126ad9b10e5SYong Wu static void mtk_iommu_v1_unbind(struct device *dev)
1279485a04aSYong Wu {
128ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
1299485a04aSYong Wu
1309485a04aSYong Wu component_unbind_all(dev, &data->larb_imu);
1319485a04aSYong Wu }
1329485a04aSYong Wu
to_mtk_domain(struct iommu_domain * dom)133ad9b10e5SYong Wu static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom)
134b17336c5SHonghui Zhang {
135ad9b10e5SYong Wu return container_of(dom, struct mtk_iommu_v1_domain, domain);
136b17336c5SHonghui Zhang }
137b17336c5SHonghui Zhang
138b17336c5SHonghui Zhang static const int mt2701_m4u_in_larb[] = {
139b17336c5SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
140b17336c5SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
141b17336c5SHonghui Zhang };
142b17336c5SHonghui Zhang
mt2701_m4u_to_larb(int id)143b17336c5SHonghui Zhang static inline int mt2701_m4u_to_larb(int id)
144b17336c5SHonghui Zhang {
145b17336c5SHonghui Zhang int i;
146b17336c5SHonghui Zhang
147b17336c5SHonghui Zhang for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
148b17336c5SHonghui Zhang if ((id) >= mt2701_m4u_in_larb[i])
149b17336c5SHonghui Zhang return i;
150b17336c5SHonghui Zhang
151b17336c5SHonghui Zhang return 0;
152b17336c5SHonghui Zhang }
153b17336c5SHonghui Zhang
mt2701_m4u_to_port(int id)154b17336c5SHonghui Zhang static inline int mt2701_m4u_to_port(int id)
155b17336c5SHonghui Zhang {
156b17336c5SHonghui Zhang int larb = mt2701_m4u_to_larb(id);
157b17336c5SHonghui Zhang
158b17336c5SHonghui Zhang return id - mt2701_m4u_in_larb[larb];
159b17336c5SHonghui Zhang }
160b17336c5SHonghui Zhang
mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data * data)161ad9b10e5SYong Wu static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data)
162b17336c5SHonghui Zhang {
163b17336c5SHonghui Zhang writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
164b17336c5SHonghui Zhang data->base + REG_MMU_INV_SEL);
165b17336c5SHonghui Zhang writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
166b17336c5SHonghui Zhang wmb(); /* Make sure the tlb flush all done */
167b17336c5SHonghui Zhang }
168b17336c5SHonghui Zhang
mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data * data,unsigned long iova,size_t size)169ad9b10e5SYong Wu static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data,
170b17336c5SHonghui Zhang unsigned long iova, size_t size)
171b17336c5SHonghui Zhang {
172b17336c5SHonghui Zhang int ret;
173b17336c5SHonghui Zhang u32 tmp;
174b17336c5SHonghui Zhang
175b17336c5SHonghui Zhang writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
176b17336c5SHonghui Zhang data->base + REG_MMU_INV_SEL);
177b17336c5SHonghui Zhang writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
178b17336c5SHonghui Zhang data->base + REG_MMU_INVLD_START_A);
179b17336c5SHonghui Zhang writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
180b17336c5SHonghui Zhang data->base + REG_MMU_INVLD_END_A);
181b17336c5SHonghui Zhang writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
182b17336c5SHonghui Zhang
183b17336c5SHonghui Zhang ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
184b17336c5SHonghui Zhang tmp, tmp != 0, 10, 100000);
185b17336c5SHonghui Zhang if (ret) {
186b17336c5SHonghui Zhang dev_warn(data->dev,
187b17336c5SHonghui Zhang "Partial TLB flush timed out, falling back to full flush\n");
188ad9b10e5SYong Wu mtk_iommu_v1_tlb_flush_all(data);
189b17336c5SHonghui Zhang }
190b17336c5SHonghui Zhang /* Clear the CPE status */
191b17336c5SHonghui Zhang writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
192b17336c5SHonghui Zhang }
193b17336c5SHonghui Zhang
mtk_iommu_v1_isr(int irq,void * dev_id)194ad9b10e5SYong Wu static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id)
195b17336c5SHonghui Zhang {
196ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = dev_id;
197ad9b10e5SYong Wu struct mtk_iommu_v1_domain *dom = data->m4u_dom;
198b17336c5SHonghui Zhang u32 int_state, regval, fault_iova, fault_pa;
199b17336c5SHonghui Zhang unsigned int fault_larb, fault_port;
200b17336c5SHonghui Zhang
201b17336c5SHonghui Zhang /* Read error information from registers */
202b17336c5SHonghui Zhang int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
203b17336c5SHonghui Zhang fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
204b17336c5SHonghui Zhang
205b17336c5SHonghui Zhang fault_iova &= F_MMU_FAULT_VA_MSK;
206b17336c5SHonghui Zhang fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
207b17336c5SHonghui Zhang regval = readl_relaxed(data->base + REG_MMU_INT_ID);
208b17336c5SHonghui Zhang fault_larb = MT2701_M4U_TF_LARB(regval);
209b17336c5SHonghui Zhang fault_port = MT2701_M4U_TF_PORT(regval);
210b17336c5SHonghui Zhang
211b17336c5SHonghui Zhang /*
212b17336c5SHonghui Zhang * MTK v1 iommu HW could not determine whether the fault is read or
213b17336c5SHonghui Zhang * write fault, report as read fault.
214b17336c5SHonghui Zhang */
215b17336c5SHonghui Zhang if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
216b17336c5SHonghui Zhang IOMMU_FAULT_READ))
217b17336c5SHonghui Zhang dev_err_ratelimited(data->dev,
218b17336c5SHonghui Zhang "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
219b17336c5SHonghui Zhang int_state, fault_iova, fault_pa,
220b17336c5SHonghui Zhang fault_larb, fault_port);
221b17336c5SHonghui Zhang
222b17336c5SHonghui Zhang /* Interrupt clear */
223b17336c5SHonghui Zhang regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
224b17336c5SHonghui Zhang regval |= F_INT_CLR_BIT;
225b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
226b17336c5SHonghui Zhang
227ad9b10e5SYong Wu mtk_iommu_v1_tlb_flush_all(data);
228b17336c5SHonghui Zhang
229b17336c5SHonghui Zhang return IRQ_HANDLED;
230b17336c5SHonghui Zhang }
231b17336c5SHonghui Zhang
mtk_iommu_v1_config(struct mtk_iommu_v1_data * data,struct device * dev,bool enable)232ad9b10e5SYong Wu static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data,
233b17336c5SHonghui Zhang struct device *dev, bool enable)
234b17336c5SHonghui Zhang {
235b17336c5SHonghui Zhang struct mtk_smi_larb_iommu *larb_mmu;
236b17336c5SHonghui Zhang unsigned int larbid, portid;
237a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
23884672f19SRobin Murphy int i;
239b17336c5SHonghui Zhang
24084672f19SRobin Murphy for (i = 0; i < fwspec->num_ids; ++i) {
24184672f19SRobin Murphy larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
24284672f19SRobin Murphy portid = mt2701_m4u_to_port(fwspec->ids[i]);
2431ee9feb2SYong Wu larb_mmu = &data->larb_imu[larbid];
244b17336c5SHonghui Zhang
245b17336c5SHonghui Zhang dev_dbg(dev, "%s iommu port: %d\n",
246b17336c5SHonghui Zhang enable ? "enable" : "disable", portid);
247b17336c5SHonghui Zhang
248b17336c5SHonghui Zhang if (enable)
249b17336c5SHonghui Zhang larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
250b17336c5SHonghui Zhang else
251b17336c5SHonghui Zhang larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
252b17336c5SHonghui Zhang }
253b17336c5SHonghui Zhang }
254b17336c5SHonghui Zhang
mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data * data)255ad9b10e5SYong Wu static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data)
256b17336c5SHonghui Zhang {
257ad9b10e5SYong Wu struct mtk_iommu_v1_domain *dom = data->m4u_dom;
258b17336c5SHonghui Zhang
259b17336c5SHonghui Zhang spin_lock_init(&dom->pgtlock);
260b17336c5SHonghui Zhang
261750afb08SLuis Chamberlain dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
262b17336c5SHonghui Zhang &dom->pgt_pa, GFP_KERNEL);
263b17336c5SHonghui Zhang if (!dom->pgt_va)
264b17336c5SHonghui Zhang return -ENOMEM;
265b17336c5SHonghui Zhang
266b17336c5SHonghui Zhang writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
267b17336c5SHonghui Zhang
268b17336c5SHonghui Zhang dom->data = data;
269b17336c5SHonghui Zhang
270b17336c5SHonghui Zhang return 0;
271b17336c5SHonghui Zhang }
272b17336c5SHonghui Zhang
mtk_iommu_v1_domain_alloc(unsigned type)273ad9b10e5SYong Wu static struct iommu_domain *mtk_iommu_v1_domain_alloc(unsigned type)
274b17336c5SHonghui Zhang {
275ad9b10e5SYong Wu struct mtk_iommu_v1_domain *dom;
276b17336c5SHonghui Zhang
277b17336c5SHonghui Zhang if (type != IOMMU_DOMAIN_UNMANAGED)
278b17336c5SHonghui Zhang return NULL;
279b17336c5SHonghui Zhang
280b17336c5SHonghui Zhang dom = kzalloc(sizeof(*dom), GFP_KERNEL);
281b17336c5SHonghui Zhang if (!dom)
282b17336c5SHonghui Zhang return NULL;
283b17336c5SHonghui Zhang
284b17336c5SHonghui Zhang return &dom->domain;
285b17336c5SHonghui Zhang }
286b17336c5SHonghui Zhang
mtk_iommu_v1_domain_free(struct iommu_domain * domain)287ad9b10e5SYong Wu static void mtk_iommu_v1_domain_free(struct iommu_domain *domain)
288b17336c5SHonghui Zhang {
289ad9b10e5SYong Wu struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
290ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = dom->data;
291b17336c5SHonghui Zhang
292b17336c5SHonghui Zhang dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
293b17336c5SHonghui Zhang dom->pgt_va, dom->pgt_pa);
294b17336c5SHonghui Zhang kfree(to_mtk_domain(domain));
295b17336c5SHonghui Zhang }
296b17336c5SHonghui Zhang
mtk_iommu_v1_attach_device(struct iommu_domain * domain,struct device * dev)297ad9b10e5SYong Wu static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev)
298b17336c5SHonghui Zhang {
299ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
300ad9b10e5SYong Wu struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
3018bbe13f5SYong Wu struct dma_iommu_mapping *mtk_mapping;
302b17336c5SHonghui Zhang int ret;
303b17336c5SHonghui Zhang
3048bbe13f5SYong Wu /* Only allow the domain created internally. */
30558960172SJoerg Roedel mtk_mapping = data->mapping;
3068bbe13f5SYong Wu if (mtk_mapping->domain != domain)
3078bbe13f5SYong Wu return 0;
308b17336c5SHonghui Zhang
309b17336c5SHonghui Zhang if (!data->m4u_dom) {
310b17336c5SHonghui Zhang data->m4u_dom = dom;
311ad9b10e5SYong Wu ret = mtk_iommu_v1_domain_finalise(data);
312b17336c5SHonghui Zhang if (ret) {
313b17336c5SHonghui Zhang data->m4u_dom = NULL;
314b17336c5SHonghui Zhang return ret;
315b17336c5SHonghui Zhang }
316b17336c5SHonghui Zhang }
317b17336c5SHonghui Zhang
318ad9b10e5SYong Wu mtk_iommu_v1_config(data, dev, true);
319b17336c5SHonghui Zhang return 0;
320b17336c5SHonghui Zhang }
321b17336c5SHonghui Zhang
mtk_iommu_v1_set_platform_dma(struct device * dev)322c1fe9119SLu Baolu static void mtk_iommu_v1_set_platform_dma(struct device *dev)
323b17336c5SHonghui Zhang {
324ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
325b17336c5SHonghui Zhang
326ad9b10e5SYong Wu mtk_iommu_v1_config(data, dev, false);
327b17336c5SHonghui Zhang }
328b17336c5SHonghui Zhang
mtk_iommu_v1_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int prot,gfp_t gfp,size_t * mapped)329ad9b10e5SYong Wu static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova,
330b577f7e6SRobin Murphy phys_addr_t paddr, size_t pgsize, size_t pgcount,
331b577f7e6SRobin Murphy int prot, gfp_t gfp, size_t *mapped)
332b17336c5SHonghui Zhang {
333ad9b10e5SYong Wu struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
334b17336c5SHonghui Zhang unsigned long flags;
335b17336c5SHonghui Zhang unsigned int i;
336b17336c5SHonghui Zhang u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
337b17336c5SHonghui Zhang u32 pabase = (u32)paddr;
338b17336c5SHonghui Zhang
339b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags);
340b577f7e6SRobin Murphy for (i = 0; i < pgcount; i++) {
341b577f7e6SRobin Murphy if (pgt_base_iova[i])
342b17336c5SHonghui Zhang break;
343b17336c5SHonghui Zhang pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
344b17336c5SHonghui Zhang pabase += MT2701_IOMMU_PAGE_SIZE;
345b17336c5SHonghui Zhang }
346b17336c5SHonghui Zhang
347b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags);
348b17336c5SHonghui Zhang
349b577f7e6SRobin Murphy *mapped = i * MT2701_IOMMU_PAGE_SIZE;
350b577f7e6SRobin Murphy mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped);
351b17336c5SHonghui Zhang
352b577f7e6SRobin Murphy return i == pgcount ? 0 : -EEXIST;
353b17336c5SHonghui Zhang }
354b17336c5SHonghui Zhang
mtk_iommu_v1_unmap(struct iommu_domain * domain,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)355ad9b10e5SYong Wu static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova,
356b577f7e6SRobin Murphy size_t pgsize, size_t pgcount,
357b577f7e6SRobin Murphy struct iommu_iotlb_gather *gather)
358b17336c5SHonghui Zhang {
359ad9b10e5SYong Wu struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
360b17336c5SHonghui Zhang unsigned long flags;
361b17336c5SHonghui Zhang u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
362b577f7e6SRobin Murphy size_t size = pgcount * MT2701_IOMMU_PAGE_SIZE;
363b17336c5SHonghui Zhang
364b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags);
365b577f7e6SRobin Murphy memset(pgt_base_iova, 0, pgcount * sizeof(u32));
366b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags);
367b17336c5SHonghui Zhang
368ad9b10e5SYong Wu mtk_iommu_v1_tlb_flush_range(dom->data, iova, size);
369b17336c5SHonghui Zhang
370b17336c5SHonghui Zhang return size;
371b17336c5SHonghui Zhang }
372b17336c5SHonghui Zhang
mtk_iommu_v1_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)373ad9b10e5SYong Wu static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
374b17336c5SHonghui Zhang {
375ad9b10e5SYong Wu struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
376b17336c5SHonghui Zhang unsigned long flags;
377b17336c5SHonghui Zhang phys_addr_t pa;
378b17336c5SHonghui Zhang
379b17336c5SHonghui Zhang spin_lock_irqsave(&dom->pgtlock, flags);
380b17336c5SHonghui Zhang pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
381b17336c5SHonghui Zhang pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
382b17336c5SHonghui Zhang spin_unlock_irqrestore(&dom->pgtlock, flags);
383b17336c5SHonghui Zhang
384b17336c5SHonghui Zhang return pa;
385b17336c5SHonghui Zhang }
386b17336c5SHonghui Zhang
387ad9b10e5SYong Wu static const struct iommu_ops mtk_iommu_v1_ops;
38884672f19SRobin Murphy
389b17336c5SHonghui Zhang /*
390b17336c5SHonghui Zhang * MTK generation one iommu HW only support one iommu domain, and all the client
391b17336c5SHonghui Zhang * sharing the same iova address space.
392b17336c5SHonghui Zhang */
mtk_iommu_v1_create_mapping(struct device * dev,struct of_phandle_args * args)393ad9b10e5SYong Wu static int mtk_iommu_v1_create_mapping(struct device *dev, struct of_phandle_args *args)
394b17336c5SHonghui Zhang {
395a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
396ad9b10e5SYong Wu struct mtk_iommu_v1_data *data;
397b17336c5SHonghui Zhang struct platform_device *m4updev;
398b17336c5SHonghui Zhang struct dma_iommu_mapping *mtk_mapping;
399b17336c5SHonghui Zhang int ret;
400b17336c5SHonghui Zhang
401b17336c5SHonghui Zhang if (args->args_count != 1) {
402b17336c5SHonghui Zhang dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
403b17336c5SHonghui Zhang args->args_count);
404b17336c5SHonghui Zhang return -EINVAL;
405b17336c5SHonghui Zhang }
406b17336c5SHonghui Zhang
407a9bf2eecSJoerg Roedel if (!fwspec) {
408ad9b10e5SYong Wu ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_v1_ops);
40984672f19SRobin Murphy if (ret)
41084672f19SRobin Murphy return ret;
411a9bf2eecSJoerg Roedel fwspec = dev_iommu_fwspec_get(dev);
412ad9b10e5SYong Wu } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_v1_ops) {
41384672f19SRobin Murphy return -EINVAL;
41484672f19SRobin Murphy }
41584672f19SRobin Murphy
4163524b559SJoerg Roedel if (!dev_iommu_priv_get(dev)) {
417b17336c5SHonghui Zhang /* Get the m4u device */
418b17336c5SHonghui Zhang m4updev = of_find_device_by_node(args->np);
419b17336c5SHonghui Zhang if (WARN_ON(!m4updev))
420b17336c5SHonghui Zhang return -EINVAL;
421b17336c5SHonghui Zhang
4223524b559SJoerg Roedel dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
423b17336c5SHonghui Zhang }
424b17336c5SHonghui Zhang
42584672f19SRobin Murphy ret = iommu_fwspec_add_ids(dev, args->args, 1);
42684672f19SRobin Murphy if (ret)
42784672f19SRobin Murphy return ret;
428b17336c5SHonghui Zhang
4293524b559SJoerg Roedel data = dev_iommu_priv_get(dev);
43058960172SJoerg Roedel mtk_mapping = data->mapping;
431b17336c5SHonghui Zhang if (!mtk_mapping) {
432b17336c5SHonghui Zhang /* MTK iommu support 4GB iova address space. */
433b17336c5SHonghui Zhang mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
434b17336c5SHonghui Zhang 0, 1ULL << 32);
43584672f19SRobin Murphy if (IS_ERR(mtk_mapping))
43684672f19SRobin Murphy return PTR_ERR(mtk_mapping);
43784672f19SRobin Murphy
43858960172SJoerg Roedel data->mapping = mtk_mapping;
439b17336c5SHonghui Zhang }
440b17336c5SHonghui Zhang
441b17336c5SHonghui Zhang return 0;
442b17336c5SHonghui Zhang }
443b17336c5SHonghui Zhang
mtk_iommu_v1_def_domain_type(struct device * dev)444ad9b10e5SYong Wu static int mtk_iommu_v1_def_domain_type(struct device *dev)
4458bbe13f5SYong Wu {
4468bbe13f5SYong Wu return IOMMU_DOMAIN_UNMANAGED;
4478bbe13f5SYong Wu }
4488bbe13f5SYong Wu
mtk_iommu_v1_probe_device(struct device * dev)449ad9b10e5SYong Wu static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev)
450b17336c5SHonghui Zhang {
451a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
452b17336c5SHonghui Zhang struct of_phandle_args iommu_spec;
453ad9b10e5SYong Wu struct mtk_iommu_v1_data *data;
454635319a4SYong Wu int err, idx = 0, larbid, larbidx;
455635319a4SYong Wu struct device_link *link;
456635319a4SYong Wu struct device *larbdev;
457b17336c5SHonghui Zhang
458822a2ed8SYong Wu /*
459822a2ed8SYong Wu * In the deferred case, free the existed fwspec.
460822a2ed8SYong Wu * Always initialize the fwspec internally.
461822a2ed8SYong Wu */
462822a2ed8SYong Wu if (fwspec) {
463822a2ed8SYong Wu iommu_fwspec_free(dev);
464822a2ed8SYong Wu fwspec = dev_iommu_fwspec_get(dev);
465822a2ed8SYong Wu }
466822a2ed8SYong Wu
467f90a9a85SYong Wu while (!of_parse_phandle_with_args(dev->of_node, "iommus",
468f90a9a85SYong Wu "#iommu-cells",
469f90a9a85SYong Wu idx, &iommu_spec)) {
470b17336c5SHonghui Zhang
471ad9b10e5SYong Wu err = mtk_iommu_v1_create_mapping(dev, &iommu_spec);
472f90a9a85SYong Wu of_node_put(iommu_spec.np);
473f90a9a85SYong Wu if (err)
474f90a9a85SYong Wu return ERR_PTR(err);
475da5d2748SJoerg Roedel
476da5d2748SJoerg Roedel /* dev->iommu_fwspec might have changed */
477da5d2748SJoerg Roedel fwspec = dev_iommu_fwspec_get(dev);
478f90a9a85SYong Wu idx++;
479b17336c5SHonghui Zhang }
480b17336c5SHonghui Zhang
481ad9b10e5SYong Wu if (!fwspec || fwspec->ops != &mtk_iommu_v1_ops)
48257dbf81fSJoerg Roedel return ERR_PTR(-ENODEV); /* Not a iommu client device */
483b17336c5SHonghui Zhang
48457dbf81fSJoerg Roedel data = dev_iommu_priv_get(dev);
485b17336c5SHonghui Zhang
486635319a4SYong Wu /* Link the consumer device with the smi-larb device(supplier) */
487635319a4SYong Wu larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
488de78657eSMiles Chen if (larbid >= MT2701_LARB_NR_MAX)
489de78657eSMiles Chen return ERR_PTR(-EINVAL);
490de78657eSMiles Chen
491635319a4SYong Wu for (idx = 1; idx < fwspec->num_ids; idx++) {
492635319a4SYong Wu larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]);
493635319a4SYong Wu if (larbid != larbidx) {
494635319a4SYong Wu dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
495635319a4SYong Wu larbid, larbidx);
496635319a4SYong Wu return ERR_PTR(-EINVAL);
497635319a4SYong Wu }
498635319a4SYong Wu }
499635319a4SYong Wu
500635319a4SYong Wu larbdev = data->larb_imu[larbid].dev;
501de78657eSMiles Chen if (!larbdev)
502de78657eSMiles Chen return ERR_PTR(-EINVAL);
503de78657eSMiles Chen
504635319a4SYong Wu link = device_link_add(dev, larbdev,
505635319a4SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
506635319a4SYong Wu if (!link)
507635319a4SYong Wu dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
508635319a4SYong Wu
50957dbf81fSJoerg Roedel return &data->iommu;
51057dbf81fSJoerg Roedel }
51157dbf81fSJoerg Roedel
mtk_iommu_v1_probe_finalize(struct device * dev)512ad9b10e5SYong Wu static void mtk_iommu_v1_probe_finalize(struct device *dev)
51357dbf81fSJoerg Roedel {
51457dbf81fSJoerg Roedel struct dma_iommu_mapping *mtk_mapping;
515ad9b10e5SYong Wu struct mtk_iommu_v1_data *data;
51657dbf81fSJoerg Roedel int err;
517f3e827d7SYong Wu
5183524b559SJoerg Roedel data = dev_iommu_priv_get(dev);
51958960172SJoerg Roedel mtk_mapping = data->mapping;
52057dbf81fSJoerg Roedel
521f3e827d7SYong Wu err = arm_iommu_attach_device(dev, mtk_mapping);
52257dbf81fSJoerg Roedel if (err)
52357dbf81fSJoerg Roedel dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
524f3e827d7SYong Wu }
525f3e827d7SYong Wu
mtk_iommu_v1_release_device(struct device * dev)526ad9b10e5SYong Wu static void mtk_iommu_v1_release_device(struct device *dev)
527b17336c5SHonghui Zhang {
528a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
529ad9b10e5SYong Wu struct mtk_iommu_v1_data *data;
530635319a4SYong Wu struct device *larbdev;
531635319a4SYong Wu unsigned int larbid;
5326f66ea09SJoerg Roedel
533635319a4SYong Wu data = dev_iommu_priv_get(dev);
534635319a4SYong Wu larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
535635319a4SYong Wu larbdev = data->larb_imu[larbid].dev;
536635319a4SYong Wu device_link_remove(dev, larbdev);
537b17336c5SHonghui Zhang }
538b17336c5SHonghui Zhang
mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data * data)539ad9b10e5SYong Wu static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data)
540b17336c5SHonghui Zhang {
541b17336c5SHonghui Zhang u32 regval;
542b17336c5SHonghui Zhang int ret;
543b17336c5SHonghui Zhang
544b17336c5SHonghui Zhang ret = clk_prepare_enable(data->bclk);
545b17336c5SHonghui Zhang if (ret) {
546b17336c5SHonghui Zhang dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
547b17336c5SHonghui Zhang return ret;
548b17336c5SHonghui Zhang }
549b17336c5SHonghui Zhang
550b17336c5SHonghui Zhang regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
551b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
552b17336c5SHonghui Zhang
553b17336c5SHonghui Zhang regval = F_INT_TRANSLATION_FAULT |
554b17336c5SHonghui Zhang F_INT_MAIN_MULTI_HIT_FAULT |
555b17336c5SHonghui Zhang F_INT_INVALID_PA_FAULT |
556b17336c5SHonghui Zhang F_INT_ENTRY_REPLACEMENT_FAULT |
557b17336c5SHonghui Zhang F_INT_TABLE_WALK_FAULT |
558b17336c5SHonghui Zhang F_INT_TLB_MISS_FAULT |
559b17336c5SHonghui Zhang F_INT_PFH_DMA_FIFO_OVERFLOW |
560b17336c5SHonghui Zhang F_INT_MISS_DMA_FIFO_OVERFLOW;
561b17336c5SHonghui Zhang writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
562b17336c5SHonghui Zhang
563b17336c5SHonghui Zhang /* protect memory,hw will write here while translation fault */
564b17336c5SHonghui Zhang writel_relaxed(data->protect_base,
565b17336c5SHonghui Zhang data->base + REG_MMU_IVRP_PADDR);
566b17336c5SHonghui Zhang
567b17336c5SHonghui Zhang writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
568b17336c5SHonghui Zhang
569ad9b10e5SYong Wu if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0,
570b17336c5SHonghui Zhang dev_name(data->dev), (void *)data)) {
571b17336c5SHonghui Zhang writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
572b17336c5SHonghui Zhang clk_disable_unprepare(data->bclk);
573b17336c5SHonghui Zhang dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
574b17336c5SHonghui Zhang return -ENODEV;
575b17336c5SHonghui Zhang }
576b17336c5SHonghui Zhang
577b17336c5SHonghui Zhang return 0;
578b17336c5SHonghui Zhang }
579b17336c5SHonghui Zhang
580ad9b10e5SYong Wu static const struct iommu_ops mtk_iommu_v1_ops = {
581ad9b10e5SYong Wu .domain_alloc = mtk_iommu_v1_domain_alloc,
582ad9b10e5SYong Wu .probe_device = mtk_iommu_v1_probe_device,
583ad9b10e5SYong Wu .probe_finalize = mtk_iommu_v1_probe_finalize,
584ad9b10e5SYong Wu .release_device = mtk_iommu_v1_release_device,
585ad9b10e5SYong Wu .def_domain_type = mtk_iommu_v1_def_domain_type,
58657dbf81fSJoerg Roedel .device_group = generic_device_group,
587b577f7e6SRobin Murphy .pgsize_bitmap = MT2701_IOMMU_PAGE_SIZE,
588c1fe9119SLu Baolu .set_platform_dma_ops = mtk_iommu_v1_set_platform_dma,
5898de000cfSYong Wu .owner = THIS_MODULE,
5909a630a4bSLu Baolu .default_domain_ops = &(const struct iommu_domain_ops) {
591ad9b10e5SYong Wu .attach_dev = mtk_iommu_v1_attach_device,
592b577f7e6SRobin Murphy .map_pages = mtk_iommu_v1_map,
593b577f7e6SRobin Murphy .unmap_pages = mtk_iommu_v1_unmap,
594ad9b10e5SYong Wu .iova_to_phys = mtk_iommu_v1_iova_to_phys,
595ad9b10e5SYong Wu .free = mtk_iommu_v1_domain_free,
5969a630a4bSLu Baolu }
597b17336c5SHonghui Zhang };
598b17336c5SHonghui Zhang
599ad9b10e5SYong Wu static const struct of_device_id mtk_iommu_v1_of_ids[] = {
600b17336c5SHonghui Zhang { .compatible = "mediatek,mt2701-m4u", },
601b17336c5SHonghui Zhang {}
602b17336c5SHonghui Zhang };
603055ea438SKrzysztof Kozlowski MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids);
604b17336c5SHonghui Zhang
605ad9b10e5SYong Wu static const struct component_master_ops mtk_iommu_v1_com_ops = {
606ad9b10e5SYong Wu .bind = mtk_iommu_v1_bind,
607ad9b10e5SYong Wu .unbind = mtk_iommu_v1_unbind,
608b17336c5SHonghui Zhang };
609b17336c5SHonghui Zhang
mtk_iommu_v1_probe(struct platform_device * pdev)610ad9b10e5SYong Wu static int mtk_iommu_v1_probe(struct platform_device *pdev)
611b17336c5SHonghui Zhang {
612b17336c5SHonghui Zhang struct device *dev = &pdev->dev;
613ad9b10e5SYong Wu struct mtk_iommu_v1_data *data;
614b17336c5SHonghui Zhang struct resource *res;
615b17336c5SHonghui Zhang struct component_match *match = NULL;
616b17336c5SHonghui Zhang void *protect;
617f90a9a85SYong Wu int larb_nr, ret, i;
618b17336c5SHonghui Zhang
619b17336c5SHonghui Zhang data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
620b17336c5SHonghui Zhang if (!data)
621b17336c5SHonghui Zhang return -ENOMEM;
622b17336c5SHonghui Zhang
623b17336c5SHonghui Zhang data->dev = dev;
624b17336c5SHonghui Zhang
625b17336c5SHonghui Zhang /* Protect memory. HW will access here while translation fault.*/
626b17336c5SHonghui Zhang protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
627b17336c5SHonghui Zhang GFP_KERNEL | GFP_DMA);
628b17336c5SHonghui Zhang if (!protect)
629b17336c5SHonghui Zhang return -ENOMEM;
630b17336c5SHonghui Zhang data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
631b17336c5SHonghui Zhang
632b17336c5SHonghui Zhang res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
633b17336c5SHonghui Zhang data->base = devm_ioremap_resource(dev, res);
634b17336c5SHonghui Zhang if (IS_ERR(data->base))
635b17336c5SHonghui Zhang return PTR_ERR(data->base);
636b17336c5SHonghui Zhang
637b17336c5SHonghui Zhang data->irq = platform_get_irq(pdev, 0);
638b17336c5SHonghui Zhang if (data->irq < 0)
639b17336c5SHonghui Zhang return data->irq;
640b17336c5SHonghui Zhang
641b17336c5SHonghui Zhang data->bclk = devm_clk_get(dev, "bclk");
642b17336c5SHonghui Zhang if (IS_ERR(data->bclk))
643b17336c5SHonghui Zhang return PTR_ERR(data->bclk);
644b17336c5SHonghui Zhang
645f90a9a85SYong Wu larb_nr = of_count_phandle_with_args(dev->of_node,
646f90a9a85SYong Wu "mediatek,larbs", NULL);
647f90a9a85SYong Wu if (larb_nr < 0)
648f90a9a85SYong Wu return larb_nr;
649f90a9a85SYong Wu
650f90a9a85SYong Wu for (i = 0; i < larb_nr; i++) {
651f90a9a85SYong Wu struct device_node *larbnode;
652b17336c5SHonghui Zhang struct platform_device *plarbdev;
653b17336c5SHonghui Zhang
654f90a9a85SYong Wu larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
655f90a9a85SYong Wu if (!larbnode)
656f90a9a85SYong Wu return -EINVAL;
657f90a9a85SYong Wu
658f90a9a85SYong Wu if (!of_device_is_available(larbnode)) {
659f90a9a85SYong Wu of_node_put(larbnode);
660b17336c5SHonghui Zhang continue;
661f90a9a85SYong Wu }
662b17336c5SHonghui Zhang
663f90a9a85SYong Wu plarbdev = of_find_device_by_node(larbnode);
664b17336c5SHonghui Zhang if (!plarbdev) {
665f90a9a85SYong Wu of_node_put(larbnode);
6662fb0feedSYong Wu return -ENODEV;
667b17336c5SHonghui Zhang }
6687d09aaf8SYong Wu if (!plarbdev->dev.driver) {
6697d09aaf8SYong Wu of_node_put(larbnode);
6707d09aaf8SYong Wu return -EPROBE_DEFER;
6717d09aaf8SYong Wu }
672f90a9a85SYong Wu data->larb_imu[i].dev = &plarbdev->dev;
673b17336c5SHonghui Zhang
6744811a485SYong Wu component_match_add_release(dev, &match, component_release_of,
6754811a485SYong Wu component_compare_of, larbnode);
676b17336c5SHonghui Zhang }
677b17336c5SHonghui Zhang
678b17336c5SHonghui Zhang platform_set_drvdata(pdev, data);
679b17336c5SHonghui Zhang
680ad9b10e5SYong Wu ret = mtk_iommu_v1_hw_init(data);
681b17336c5SHonghui Zhang if (ret)
682b17336c5SHonghui Zhang return ret;
683b17336c5SHonghui Zhang
6846f66ea09SJoerg Roedel ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
6856f66ea09SJoerg Roedel dev_name(&pdev->dev));
6866f66ea09SJoerg Roedel if (ret)
687142e821fSChristophe JAILLET goto out_clk_unprepare;
6886f66ea09SJoerg Roedel
689ad9b10e5SYong Wu ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev);
6906f66ea09SJoerg Roedel if (ret)
691ac304c07SYong Wu goto out_sysfs_remove;
692ac304c07SYong Wu
693ad9b10e5SYong Wu ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match);
694ac304c07SYong Wu if (ret)
6957341c365SRobin Murphy goto out_dev_unreg;
6966f66ea09SJoerg Roedel return ret;
6976f66ea09SJoerg Roedel
698ac304c07SYong Wu out_dev_unreg:
699ac304c07SYong Wu iommu_device_unregister(&data->iommu);
700ac304c07SYong Wu out_sysfs_remove:
701ac304c07SYong Wu iommu_device_sysfs_remove(&data->iommu);
702142e821fSChristophe JAILLET out_clk_unprepare:
703142e821fSChristophe JAILLET clk_disable_unprepare(data->bclk);
704ac304c07SYong Wu return ret;
705b17336c5SHonghui Zhang }
706b17336c5SHonghui Zhang
mtk_iommu_v1_remove(struct platform_device * pdev)70785e1049eSUwe Kleine-König static void mtk_iommu_v1_remove(struct platform_device *pdev)
708b17336c5SHonghui Zhang {
709ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev);
710b17336c5SHonghui Zhang
7116f66ea09SJoerg Roedel iommu_device_sysfs_remove(&data->iommu);
7126f66ea09SJoerg Roedel iommu_device_unregister(&data->iommu);
7136f66ea09SJoerg Roedel
714b17336c5SHonghui Zhang clk_disable_unprepare(data->bclk);
715b17336c5SHonghui Zhang devm_free_irq(&pdev->dev, data->irq, data);
716ad9b10e5SYong Wu component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops);
717b17336c5SHonghui Zhang }
718b17336c5SHonghui Zhang
mtk_iommu_v1_suspend(struct device * dev)719ad9b10e5SYong Wu static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev)
720b17336c5SHonghui Zhang {
721ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
722ad9b10e5SYong Wu struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
723b17336c5SHonghui Zhang void __iomem *base = data->base;
724b17336c5SHonghui Zhang
725b17336c5SHonghui Zhang reg->standard_axi_mode = readl_relaxed(base +
726b17336c5SHonghui Zhang REG_MMU_STANDARD_AXI_MODE);
727b17336c5SHonghui Zhang reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
728b17336c5SHonghui Zhang reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
729b17336c5SHonghui Zhang reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
730b17336c5SHonghui Zhang return 0;
731b17336c5SHonghui Zhang }
732b17336c5SHonghui Zhang
mtk_iommu_v1_resume(struct device * dev)733ad9b10e5SYong Wu static int __maybe_unused mtk_iommu_v1_resume(struct device *dev)
734b17336c5SHonghui Zhang {
735ad9b10e5SYong Wu struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
736ad9b10e5SYong Wu struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
737b17336c5SHonghui Zhang void __iomem *base = data->base;
738b17336c5SHonghui Zhang
739b17336c5SHonghui Zhang writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
740b17336c5SHonghui Zhang writel_relaxed(reg->standard_axi_mode,
741b17336c5SHonghui Zhang base + REG_MMU_STANDARD_AXI_MODE);
742b17336c5SHonghui Zhang writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
743b17336c5SHonghui Zhang writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
744b17336c5SHonghui Zhang writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
745b17336c5SHonghui Zhang writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
746b17336c5SHonghui Zhang return 0;
747b17336c5SHonghui Zhang }
748b17336c5SHonghui Zhang
749ad9b10e5SYong Wu static const struct dev_pm_ops mtk_iommu_v1_pm_ops = {
750ad9b10e5SYong Wu SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume)
751b17336c5SHonghui Zhang };
752b17336c5SHonghui Zhang
753ad9b10e5SYong Wu static struct platform_driver mtk_iommu_v1_driver = {
754ad9b10e5SYong Wu .probe = mtk_iommu_v1_probe,
75585e1049eSUwe Kleine-König .remove_new = mtk_iommu_v1_remove,
756b17336c5SHonghui Zhang .driver = {
757395df08dSMatthias Brugger .name = "mtk-iommu-v1",
758ad9b10e5SYong Wu .of_match_table = mtk_iommu_v1_of_ids,
759ad9b10e5SYong Wu .pm = &mtk_iommu_v1_pm_ops,
760b17336c5SHonghui Zhang }
761b17336c5SHonghui Zhang };
762ad9b10e5SYong Wu module_platform_driver(mtk_iommu_v1_driver);
763b17336c5SHonghui Zhang
7648de000cfSYong Wu MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");
7658de000cfSYong Wu MODULE_LICENSE("GPL v2");
766