1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/bug.h> 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/device.h> 11 #include <linux/dma-direct.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iommu.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/regmap.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 #include <linux/soc/mediatek/infracfg.h> 29 #include <asm/barrier.h> 30 #include <soc/mediatek/smi.h> 31 32 #include "mtk_iommu.h" 33 34 #define REG_MMU_PT_BASE_ADDR 0x000 35 #define MMU_PT_ADDR_MASK GENMASK(31, 7) 36 37 #define REG_MMU_INVALIDATE 0x020 38 #define F_ALL_INVLD 0x2 39 #define F_MMU_INV_RANGE 0x1 40 41 #define REG_MMU_INVLD_START_A 0x024 42 #define REG_MMU_INVLD_END_A 0x028 43 44 #define REG_MMU_INV_SEL_GEN2 0x02c 45 #define REG_MMU_INV_SEL_GEN1 0x038 46 #define F_INVLD_EN0 BIT(0) 47 #define F_INVLD_EN1 BIT(1) 48 49 #define REG_MMU_MISC_CTRL 0x048 50 #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 51 #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 52 53 #define REG_MMU_DCM_DIS 0x050 54 #define REG_MMU_WR_LEN_CTRL 0x054 55 #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 56 57 #define REG_MMU_CTRL_REG 0x110 58 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 59 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 60 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 61 62 #define REG_MMU_IVRP_PADDR 0x114 63 64 #define REG_MMU_VLD_PA_RNG 0x118 65 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 66 67 #define REG_MMU_INT_CONTROL0 0x120 68 #define F_L2_MULIT_HIT_EN BIT(0) 69 #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 70 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 71 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 72 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 73 #define F_MISS_FIFO_ERR_INT_EN BIT(6) 74 #define F_INT_CLR_BIT BIT(12) 75 76 #define REG_MMU_INT_MAIN_CONTROL 0x124 77 /* mmu0 | mmu1 */ 78 #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 79 #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 80 #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 81 #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 82 #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 83 #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 84 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 85 86 #define REG_MMU_CPE_DONE 0x12C 87 88 #define REG_MMU_FAULT_ST1 0x134 89 #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 90 #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 91 92 #define REG_MMU0_FAULT_VA 0x13c 93 #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 94 #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 95 #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 96 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 97 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 98 99 #define REG_MMU0_INVLD_PA 0x140 100 #define REG_MMU1_FAULT_VA 0x144 101 #define REG_MMU1_INVLD_PA 0x148 102 #define REG_MMU0_INT_ID 0x150 103 #define REG_MMU1_INT_ID 0x154 104 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 105 #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 106 #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 107 #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 108 109 #define MTK_PROTECT_PA_ALIGN 256 110 111 #define HAS_4GB_MODE BIT(0) 112 /* HW will use the EMI clock if there isn't the "bclk". */ 113 #define HAS_BCLK BIT(1) 114 #define HAS_VLD_PA_RNG BIT(2) 115 #define RESET_AXI BIT(3) 116 #define OUT_ORDER_WR_EN BIT(4) 117 #define HAS_SUB_COMM BIT(5) 118 #define WR_THROT_EN BIT(6) 119 #define HAS_LEGACY_IVRP_PADDR BIT(7) 120 #define IOVA_34_EN BIT(8) 121 122 #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ 123 ((((pdata)->flags) & (_x)) == (_x)) 124 125 struct mtk_iommu_domain { 126 struct io_pgtable_cfg cfg; 127 struct io_pgtable_ops *iop; 128 129 struct mtk_iommu_data *data; 130 struct iommu_domain domain; 131 }; 132 133 static const struct iommu_ops mtk_iommu_ops; 134 135 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data); 136 137 #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 138 dma_addr_t _addr = iova; \ 139 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 140 }) 141 142 /* 143 * In M4U 4GB mode, the physical address is remapped as below: 144 * 145 * CPU Physical address: 146 * ==================== 147 * 148 * 0 1G 2G 3G 4G 5G 149 * |---A---|---B---|---C---|---D---|---E---| 150 * +--I/O--+------------Memory-------------+ 151 * 152 * IOMMU output physical address: 153 * ============================= 154 * 155 * 4G 5G 6G 7G 8G 156 * |---E---|---B---|---C---|---D---| 157 * +------------Memory-------------+ 158 * 159 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 160 * bit32 of the CPU physical address always is needed to set, and for Region 161 * 'E', the CPU physical address keep as is. 162 * Additionally, The iommu consumers always use the CPU phyiscal address. 163 */ 164 #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 165 166 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 167 168 #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) 169 170 struct mtk_iommu_iova_region { 171 dma_addr_t iova_base; 172 unsigned long long size; 173 }; 174 175 static const struct mtk_iommu_iova_region single_domain[] = { 176 {.iova_base = 0, .size = SZ_4G}, 177 }; 178 179 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { 180 { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */ 181 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 182 { .iova_base = SZ_4G, .size = SZ_4G}, /* vdec: 4G ~ 8G */ 183 { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* CAM/MDP: 8G ~ 12G */ 184 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 185 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 186 #endif 187 }; 188 189 /* 190 * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain 191 * for the performance. 192 * 193 * Here always return the mtk_iommu_data of the first probed M4U where the 194 * iommu domain information is recorded. 195 */ 196 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) 197 { 198 struct mtk_iommu_data *data; 199 200 for_each_m4u(data) 201 return data; 202 203 return NULL; 204 } 205 206 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 207 { 208 return container_of(dom, struct mtk_iommu_domain, domain); 209 } 210 211 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 212 { 213 unsigned long flags; 214 215 spin_lock_irqsave(&data->tlb_lock, flags); 216 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 217 data->base + data->plat_data->inv_sel_reg); 218 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 219 wmb(); /* Make sure the tlb flush all done */ 220 spin_unlock_irqrestore(&data->tlb_lock, flags); 221 } 222 223 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 224 size_t granule, 225 struct mtk_iommu_data *data) 226 { 227 unsigned long flags; 228 int ret; 229 u32 tmp; 230 231 for_each_m4u(data) { 232 if (pm_runtime_get_if_in_use(data->dev) <= 0) 233 continue; 234 235 spin_lock_irqsave(&data->tlb_lock, flags); 236 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 237 data->base + data->plat_data->inv_sel_reg); 238 239 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), 240 data->base + REG_MMU_INVLD_START_A); 241 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 242 data->base + REG_MMU_INVLD_END_A); 243 writel_relaxed(F_MMU_INV_RANGE, 244 data->base + REG_MMU_INVALIDATE); 245 246 /* tlb sync */ 247 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 248 tmp, tmp != 0, 10, 1000); 249 250 /* Clear the CPE status */ 251 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 252 spin_unlock_irqrestore(&data->tlb_lock, flags); 253 254 if (ret) { 255 dev_warn(data->dev, 256 "Partial TLB flush timed out, falling back to full flush\n"); 257 mtk_iommu_tlb_flush_all(data); 258 } 259 260 pm_runtime_put(data->dev); 261 } 262 } 263 264 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 265 { 266 struct mtk_iommu_data *data = dev_id; 267 struct mtk_iommu_domain *dom = data->m4u_dom; 268 unsigned int fault_larb, fault_port, sub_comm = 0; 269 u32 int_state, regval, va34_32, pa34_32; 270 u64 fault_iova, fault_pa; 271 bool layer, write; 272 273 /* Read error info from registers */ 274 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); 275 if (int_state & F_REG_MMU0_FAULT_MASK) { 276 regval = readl_relaxed(data->base + REG_MMU0_INT_ID); 277 fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); 278 fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); 279 } else { 280 regval = readl_relaxed(data->base + REG_MMU1_INT_ID); 281 fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); 282 fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); 283 } 284 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 285 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 286 if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) { 287 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 288 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 289 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 290 fault_iova |= (u64)va34_32 << 32; 291 fault_pa |= (u64)pa34_32 << 32; 292 } 293 294 fault_port = F_MMU_INT_ID_PORT_ID(regval); 295 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { 296 fault_larb = F_MMU_INT_ID_COMM_ID(regval); 297 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 298 } else { 299 fault_larb = F_MMU_INT_ID_LARB_ID(regval); 300 } 301 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 302 303 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 304 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 305 dev_err_ratelimited( 306 data->dev, 307 "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n", 308 int_state, fault_iova, fault_pa, fault_larb, fault_port, 309 layer, write ? "write" : "read"); 310 } 311 312 /* Interrupt clear */ 313 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); 314 regval |= F_INT_CLR_BIT; 315 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 316 317 mtk_iommu_tlb_flush_all(data); 318 319 return IRQ_HANDLED; 320 } 321 322 static int mtk_iommu_get_domain_id(struct device *dev, 323 const struct mtk_iommu_plat_data *plat_data) 324 { 325 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; 326 const struct bus_dma_region *dma_rgn = dev->dma_range_map; 327 int i, candidate = -1; 328 dma_addr_t dma_end; 329 330 if (!dma_rgn || plat_data->iova_region_nr == 1) 331 return 0; 332 333 dma_end = dma_rgn->dma_start + dma_rgn->size - 1; 334 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { 335 /* Best fit. */ 336 if (dma_rgn->dma_start == rgn->iova_base && 337 dma_end == rgn->iova_base + rgn->size - 1) 338 return i; 339 /* ok if it is inside this region. */ 340 if (dma_rgn->dma_start >= rgn->iova_base && 341 dma_end < rgn->iova_base + rgn->size) 342 candidate = i; 343 } 344 345 if (candidate >= 0) 346 return candidate; 347 dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n", 348 &dma_rgn->dma_start, dma_rgn->size); 349 return -EINVAL; 350 } 351 352 static void mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 353 bool enable, unsigned int domid) 354 { 355 struct mtk_smi_larb_iommu *larb_mmu; 356 unsigned int larbid, portid; 357 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 358 const struct mtk_iommu_iova_region *region; 359 int i; 360 361 for (i = 0; i < fwspec->num_ids; ++i) { 362 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 363 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 364 365 larb_mmu = &data->larb_imu[larbid]; 366 367 region = data->plat_data->iova_region + domid; 368 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 369 370 dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n", 371 enable ? "enable" : "disable", dev_name(larb_mmu->dev), 372 portid, domid, larb_mmu->bank[portid]); 373 374 if (enable) 375 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 376 else 377 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 378 } 379 } 380 381 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 382 struct mtk_iommu_data *data, 383 unsigned int domid) 384 { 385 const struct mtk_iommu_iova_region *region; 386 387 /* Use the exist domain as there is only one pgtable here. */ 388 if (data->m4u_dom) { 389 dom->iop = data->m4u_dom->iop; 390 dom->cfg = data->m4u_dom->cfg; 391 dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap; 392 goto update_iova_region; 393 } 394 395 dom->cfg = (struct io_pgtable_cfg) { 396 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 397 IO_PGTABLE_QUIRK_NO_PERMS | 398 IO_PGTABLE_QUIRK_ARM_MTK_EXT, 399 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 400 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 401 .iommu_dev = data->dev, 402 }; 403 404 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 405 dom->cfg.oas = data->enable_4GB ? 33 : 32; 406 else 407 dom->cfg.oas = 35; 408 409 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 410 if (!dom->iop) { 411 dev_err(data->dev, "Failed to alloc io pgtable\n"); 412 return -EINVAL; 413 } 414 415 /* Update our support page sizes bitmap */ 416 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 417 418 update_iova_region: 419 /* Update the iova region for this domain */ 420 region = data->plat_data->iova_region + domid; 421 dom->domain.geometry.aperture_start = region->iova_base; 422 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 423 dom->domain.geometry.force_aperture = true; 424 return 0; 425 } 426 427 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 428 { 429 struct mtk_iommu_domain *dom; 430 431 if (type != IOMMU_DOMAIN_DMA) 432 return NULL; 433 434 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 435 if (!dom) 436 return NULL; 437 438 return &dom->domain; 439 } 440 441 static void mtk_iommu_domain_free(struct iommu_domain *domain) 442 { 443 kfree(to_mtk_domain(domain)); 444 } 445 446 static int mtk_iommu_attach_device(struct iommu_domain *domain, 447 struct device *dev) 448 { 449 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 450 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 451 struct device *m4udev = data->dev; 452 int ret, domid; 453 454 domid = mtk_iommu_get_domain_id(dev, data->plat_data); 455 if (domid < 0) 456 return domid; 457 458 if (!dom->data) { 459 if (mtk_iommu_domain_finalise(dom, data, domid)) 460 return -ENODEV; 461 dom->data = data; 462 } 463 464 if (!data->m4u_dom) { /* Initialize the M4U HW */ 465 ret = pm_runtime_resume_and_get(m4udev); 466 if (ret < 0) 467 return ret; 468 469 ret = mtk_iommu_hw_init(data); 470 if (ret) { 471 pm_runtime_put(m4udev); 472 return ret; 473 } 474 data->m4u_dom = dom; 475 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, 476 data->base + REG_MMU_PT_BASE_ADDR); 477 478 pm_runtime_put(m4udev); 479 } 480 481 mtk_iommu_config(data, dev, true, domid); 482 return 0; 483 } 484 485 static void mtk_iommu_detach_device(struct iommu_domain *domain, 486 struct device *dev) 487 { 488 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 489 490 mtk_iommu_config(data, dev, false, 0); 491 } 492 493 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 494 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 495 { 496 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 497 498 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 499 if (dom->data->enable_4GB) 500 paddr |= BIT_ULL(32); 501 502 /* Synchronize with the tlb_lock */ 503 return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); 504 } 505 506 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 507 unsigned long iova, size_t size, 508 struct iommu_iotlb_gather *gather) 509 { 510 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 511 512 iommu_iotlb_gather_add_range(gather, iova, size); 513 return dom->iop->unmap(dom->iop, iova, size, gather); 514 } 515 516 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 517 { 518 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 519 520 mtk_iommu_tlb_flush_all(dom->data); 521 } 522 523 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 524 struct iommu_iotlb_gather *gather) 525 { 526 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 527 size_t length = gather->end - gather->start + 1; 528 529 mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, 530 dom->data); 531 } 532 533 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 534 size_t size) 535 { 536 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 537 538 mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data); 539 } 540 541 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 542 dma_addr_t iova) 543 { 544 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 545 phys_addr_t pa; 546 547 pa = dom->iop->iova_to_phys(dom->iop, iova); 548 if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 549 dom->data->enable_4GB && 550 pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 551 pa &= ~BIT_ULL(32); 552 553 return pa; 554 } 555 556 static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 557 { 558 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 559 struct mtk_iommu_data *data; 560 struct device_link *link; 561 struct device *larbdev; 562 unsigned int larbid, larbidx, i; 563 564 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 565 return ERR_PTR(-ENODEV); /* Not a iommu client device */ 566 567 data = dev_iommu_priv_get(dev); 568 569 /* 570 * Link the consumer device with the smi-larb device(supplier). 571 * The device that connects with each a larb is a independent HW. 572 * All the ports in each a device should be in the same larbs. 573 */ 574 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 575 for (i = 1; i < fwspec->num_ids; i++) { 576 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); 577 if (larbid != larbidx) { 578 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 579 larbid, larbidx); 580 return ERR_PTR(-EINVAL); 581 } 582 } 583 larbdev = data->larb_imu[larbid].dev; 584 link = device_link_add(dev, larbdev, 585 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 586 if (!link) 587 dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 588 return &data->iommu; 589 } 590 591 static void mtk_iommu_release_device(struct device *dev) 592 { 593 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 594 struct mtk_iommu_data *data; 595 struct device *larbdev; 596 unsigned int larbid; 597 598 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 599 return; 600 601 data = dev_iommu_priv_get(dev); 602 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 603 larbdev = data->larb_imu[larbid].dev; 604 device_link_remove(dev, larbdev); 605 606 iommu_fwspec_free(dev); 607 } 608 609 static struct iommu_group *mtk_iommu_device_group(struct device *dev) 610 { 611 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 612 struct iommu_group *group; 613 int domid; 614 615 if (!data) 616 return ERR_PTR(-ENODEV); 617 618 domid = mtk_iommu_get_domain_id(dev, data->plat_data); 619 if (domid < 0) 620 return ERR_PTR(domid); 621 622 group = data->m4u_group[domid]; 623 if (!group) { 624 group = iommu_group_alloc(); 625 if (!IS_ERR(group)) 626 data->m4u_group[domid] = group; 627 } else { 628 iommu_group_ref_get(group); 629 } 630 return group; 631 } 632 633 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 634 { 635 struct platform_device *m4updev; 636 637 if (args->args_count != 1) { 638 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 639 args->args_count); 640 return -EINVAL; 641 } 642 643 if (!dev_iommu_priv_get(dev)) { 644 /* Get the m4u device */ 645 m4updev = of_find_device_by_node(args->np); 646 if (WARN_ON(!m4updev)) 647 return -EINVAL; 648 649 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 650 } 651 652 return iommu_fwspec_add_ids(dev, args->args, 1); 653 } 654 655 static void mtk_iommu_get_resv_regions(struct device *dev, 656 struct list_head *head) 657 { 658 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 659 unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i; 660 const struct mtk_iommu_iova_region *resv, *curdom; 661 struct iommu_resv_region *region; 662 int prot = IOMMU_WRITE | IOMMU_READ; 663 664 if ((int)domid < 0) 665 return; 666 curdom = data->plat_data->iova_region + domid; 667 for (i = 0; i < data->plat_data->iova_region_nr; i++) { 668 resv = data->plat_data->iova_region + i; 669 670 /* Only reserve when the region is inside the current domain */ 671 if (resv->iova_base <= curdom->iova_base || 672 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 673 continue; 674 675 region = iommu_alloc_resv_region(resv->iova_base, resv->size, 676 prot, IOMMU_RESV_RESERVED); 677 if (!region) 678 return; 679 680 list_add_tail(®ion->list, head); 681 } 682 } 683 684 static const struct iommu_ops mtk_iommu_ops = { 685 .domain_alloc = mtk_iommu_domain_alloc, 686 .probe_device = mtk_iommu_probe_device, 687 .release_device = mtk_iommu_release_device, 688 .device_group = mtk_iommu_device_group, 689 .of_xlate = mtk_iommu_of_xlate, 690 .get_resv_regions = mtk_iommu_get_resv_regions, 691 .put_resv_regions = generic_iommu_put_resv_regions, 692 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 693 .owner = THIS_MODULE, 694 .default_domain_ops = &(const struct iommu_domain_ops) { 695 .attach_dev = mtk_iommu_attach_device, 696 .detach_dev = mtk_iommu_detach_device, 697 .map = mtk_iommu_map, 698 .unmap = mtk_iommu_unmap, 699 .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 700 .iotlb_sync = mtk_iommu_iotlb_sync, 701 .iotlb_sync_map = mtk_iommu_sync_map, 702 .iova_to_phys = mtk_iommu_iova_to_phys, 703 .free = mtk_iommu_domain_free, 704 } 705 }; 706 707 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 708 { 709 u32 regval; 710 711 if (data->plat_data->m4u_plat == M4U_MT8173) { 712 regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 713 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 714 } else { 715 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); 716 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 717 } 718 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 719 720 regval = F_L2_MULIT_HIT_EN | 721 F_TABLE_WALK_FAULT_INT_EN | 722 F_PREETCH_FIFO_OVERFLOW_INT_EN | 723 F_MISS_FIFO_OVERFLOW_INT_EN | 724 F_PREFETCH_FIFO_ERR_INT_EN | 725 F_MISS_FIFO_ERR_INT_EN; 726 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 727 728 regval = F_INT_TRANSLATION_FAULT | 729 F_INT_MAIN_MULTI_HIT_FAULT | 730 F_INT_INVALID_PA_FAULT | 731 F_INT_ENTRY_REPLACEMENT_FAULT | 732 F_INT_TLB_MISS_FAULT | 733 F_INT_MISS_TRANSACTION_FIFO_FAULT | 734 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 735 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); 736 737 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 738 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 739 else 740 regval = lower_32_bits(data->protect_base) | 741 upper_32_bits(data->protect_base); 742 writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); 743 744 if (data->enable_4GB && 745 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 746 /* 747 * If 4GB mode is enabled, the validate PA range is from 748 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 749 */ 750 regval = F_MMU_VLD_PA_RNG(7, 4); 751 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); 752 } 753 writel_relaxed(0, data->base + REG_MMU_DCM_DIS); 754 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 755 /* write command throttling mode */ 756 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); 757 regval &= ~F_MMU_WR_THROT_DIS_MASK; 758 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); 759 } 760 761 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 762 /* The register is called STANDARD_AXI_MODE in this case */ 763 regval = 0; 764 } else { 765 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); 766 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 767 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 768 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 769 } 770 writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); 771 772 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 773 dev_name(data->dev), (void *)data)) { 774 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 775 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 776 return -ENODEV; 777 } 778 779 return 0; 780 } 781 782 static const struct component_master_ops mtk_iommu_com_ops = { 783 .bind = mtk_iommu_bind, 784 .unbind = mtk_iommu_unbind, 785 }; 786 787 static int mtk_iommu_probe(struct platform_device *pdev) 788 { 789 struct mtk_iommu_data *data; 790 struct device *dev = &pdev->dev; 791 struct device_node *larbnode, *smicomm_node; 792 struct platform_device *plarbdev; 793 struct device_link *link; 794 struct resource *res; 795 resource_size_t ioaddr; 796 struct component_match *match = NULL; 797 struct regmap *infracfg; 798 void *protect; 799 int i, larb_nr, ret; 800 u32 val; 801 char *p; 802 803 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 804 if (!data) 805 return -ENOMEM; 806 data->dev = dev; 807 data->plat_data = of_device_get_match_data(dev); 808 809 /* Protect memory. HW will access here while translation fault.*/ 810 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 811 if (!protect) 812 return -ENOMEM; 813 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 814 815 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 816 switch (data->plat_data->m4u_plat) { 817 case M4U_MT2712: 818 p = "mediatek,mt2712-infracfg"; 819 break; 820 case M4U_MT8173: 821 p = "mediatek,mt8173-infracfg"; 822 break; 823 default: 824 p = NULL; 825 } 826 827 infracfg = syscon_regmap_lookup_by_compatible(p); 828 829 if (IS_ERR(infracfg)) 830 return PTR_ERR(infracfg); 831 832 ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 833 if (ret) 834 return ret; 835 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 836 } 837 838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 839 data->base = devm_ioremap_resource(dev, res); 840 if (IS_ERR(data->base)) 841 return PTR_ERR(data->base); 842 ioaddr = res->start; 843 844 data->irq = platform_get_irq(pdev, 0); 845 if (data->irq < 0) 846 return data->irq; 847 848 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 849 data->bclk = devm_clk_get(dev, "bclk"); 850 if (IS_ERR(data->bclk)) 851 return PTR_ERR(data->bclk); 852 } 853 854 larb_nr = of_count_phandle_with_args(dev->of_node, 855 "mediatek,larbs", NULL); 856 if (larb_nr < 0) 857 return larb_nr; 858 859 for (i = 0; i < larb_nr; i++) { 860 u32 id; 861 862 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 863 if (!larbnode) 864 return -EINVAL; 865 866 if (!of_device_is_available(larbnode)) { 867 of_node_put(larbnode); 868 continue; 869 } 870 871 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 872 if (ret)/* The id is consecutive if there is no this property */ 873 id = i; 874 875 plarbdev = of_find_device_by_node(larbnode); 876 if (!plarbdev) { 877 of_node_put(larbnode); 878 return -ENODEV; 879 } 880 if (!plarbdev->dev.driver) { 881 of_node_put(larbnode); 882 return -EPROBE_DEFER; 883 } 884 data->larb_imu[id].dev = &plarbdev->dev; 885 886 component_match_add_release(dev, &match, component_release_of, 887 component_compare_of, larbnode); 888 } 889 890 /* Get smi-common dev from the last larb. */ 891 smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 892 if (!smicomm_node) 893 return -EINVAL; 894 895 plarbdev = of_find_device_by_node(smicomm_node); 896 of_node_put(smicomm_node); 897 data->smicomm_dev = &plarbdev->dev; 898 899 pm_runtime_enable(dev); 900 901 link = device_link_add(data->smicomm_dev, dev, 902 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 903 if (!link) { 904 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 905 ret = -EINVAL; 906 goto out_runtime_disable; 907 } 908 909 platform_set_drvdata(pdev, data); 910 911 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 912 "mtk-iommu.%pa", &ioaddr); 913 if (ret) 914 goto out_link_remove; 915 916 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 917 if (ret) 918 goto out_sysfs_remove; 919 920 spin_lock_init(&data->tlb_lock); 921 list_add_tail(&data->list, &m4ulist); 922 923 if (!iommu_present(&platform_bus_type)) { 924 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 925 if (ret) 926 goto out_list_del; 927 } 928 929 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 930 if (ret) 931 goto out_bus_set_null; 932 return ret; 933 934 out_bus_set_null: 935 bus_set_iommu(&platform_bus_type, NULL); 936 out_list_del: 937 list_del(&data->list); 938 iommu_device_unregister(&data->iommu); 939 out_sysfs_remove: 940 iommu_device_sysfs_remove(&data->iommu); 941 out_link_remove: 942 device_link_remove(data->smicomm_dev, dev); 943 out_runtime_disable: 944 pm_runtime_disable(dev); 945 return ret; 946 } 947 948 static int mtk_iommu_remove(struct platform_device *pdev) 949 { 950 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 951 952 iommu_device_sysfs_remove(&data->iommu); 953 iommu_device_unregister(&data->iommu); 954 955 if (iommu_present(&platform_bus_type)) 956 bus_set_iommu(&platform_bus_type, NULL); 957 958 clk_disable_unprepare(data->bclk); 959 device_link_remove(data->smicomm_dev, &pdev->dev); 960 pm_runtime_disable(&pdev->dev); 961 devm_free_irq(&pdev->dev, data->irq, data); 962 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 963 return 0; 964 } 965 966 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 967 { 968 struct mtk_iommu_data *data = dev_get_drvdata(dev); 969 struct mtk_iommu_suspend_reg *reg = &data->reg; 970 void __iomem *base = data->base; 971 972 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 973 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 974 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 975 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 976 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); 977 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 978 reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); 979 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 980 clk_disable_unprepare(data->bclk); 981 return 0; 982 } 983 984 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 985 { 986 struct mtk_iommu_data *data = dev_get_drvdata(dev); 987 struct mtk_iommu_suspend_reg *reg = &data->reg; 988 struct mtk_iommu_domain *m4u_dom = data->m4u_dom; 989 void __iomem *base = data->base; 990 int ret; 991 992 ret = clk_prepare_enable(data->bclk); 993 if (ret) { 994 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 995 return ret; 996 } 997 998 /* 999 * Uppon first resume, only enable the clk and return, since the values of the 1000 * registers are not yet set. 1001 */ 1002 if (!m4u_dom) 1003 return 0; 1004 1005 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 1006 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 1007 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 1008 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 1009 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); 1010 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); 1011 writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); 1012 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 1013 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); 1014 1015 /* 1016 * Users may allocate dma buffer before they call pm_runtime_get, 1017 * in which case it will lack the necessary tlb flush. 1018 * Thus, make sure to update the tlb after each PM resume. 1019 */ 1020 mtk_iommu_tlb_flush_all(data); 1021 return 0; 1022 } 1023 1024 static const struct dev_pm_ops mtk_iommu_pm_ops = { 1025 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 1026 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1027 pm_runtime_force_resume) 1028 }; 1029 1030 static const struct mtk_iommu_plat_data mt2712_data = { 1031 .m4u_plat = M4U_MT2712, 1032 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG, 1033 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1034 .iova_region = single_domain, 1035 .iova_region_nr = ARRAY_SIZE(single_domain), 1036 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1037 }; 1038 1039 static const struct mtk_iommu_plat_data mt6779_data = { 1040 .m4u_plat = M4U_MT6779, 1041 .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, 1042 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1043 .iova_region = single_domain, 1044 .iova_region_nr = ARRAY_SIZE(single_domain), 1045 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1046 }; 1047 1048 static const struct mtk_iommu_plat_data mt8167_data = { 1049 .m4u_plat = M4U_MT8167, 1050 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR, 1051 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1052 .iova_region = single_domain, 1053 .iova_region_nr = ARRAY_SIZE(single_domain), 1054 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 1055 }; 1056 1057 static const struct mtk_iommu_plat_data mt8173_data = { 1058 .m4u_plat = M4U_MT8173, 1059 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1060 HAS_LEGACY_IVRP_PADDR, 1061 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1062 .iova_region = single_domain, 1063 .iova_region_nr = ARRAY_SIZE(single_domain), 1064 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1065 }; 1066 1067 static const struct mtk_iommu_plat_data mt8183_data = { 1068 .m4u_plat = M4U_MT8183, 1069 .flags = RESET_AXI, 1070 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1071 .iova_region = single_domain, 1072 .iova_region_nr = ARRAY_SIZE(single_domain), 1073 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1074 }; 1075 1076 static const struct mtk_iommu_plat_data mt8192_data = { 1077 .m4u_plat = M4U_MT8192, 1078 .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN | 1079 WR_THROT_EN | IOVA_34_EN, 1080 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1081 .iova_region = mt8192_multi_dom, 1082 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1083 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 1084 {0, 14, 16}, {0, 13, 18, 17}}, 1085 }; 1086 1087 static const struct of_device_id mtk_iommu_of_ids[] = { 1088 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1089 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 1090 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1091 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1092 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 1093 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1094 {} 1095 }; 1096 1097 static struct platform_driver mtk_iommu_driver = { 1098 .probe = mtk_iommu_probe, 1099 .remove = mtk_iommu_remove, 1100 .driver = { 1101 .name = "mtk-iommu", 1102 .of_match_table = mtk_iommu_of_ids, 1103 .pm = &mtk_iommu_pm_ops, 1104 } 1105 }; 1106 module_platform_driver(mtk_iommu_driver); 1107 1108 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 1109 MODULE_LICENSE("GPL v2"); 1110