1 /* 2 * Copyright (c) 2015-2016 MediaTek Inc. 3 * Author: Yong Wu <yong.wu@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #include <linux/bootmem.h> 15 #include <linux/bug.h> 16 #include <linux/clk.h> 17 #include <linux/component.h> 18 #include <linux/device.h> 19 #include <linux/dma-iommu.h> 20 #include <linux/err.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/iommu.h> 24 #include <linux/iopoll.h> 25 #include <linux/list.h> 26 #include <linux/of_address.h> 27 #include <linux/of_iommu.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/slab.h> 32 #include <linux/spinlock.h> 33 #include <asm/barrier.h> 34 #include <soc/mediatek/smi.h> 35 36 #include "mtk_iommu.h" 37 38 #define REG_MMU_PT_BASE_ADDR 0x000 39 40 #define REG_MMU_INVALIDATE 0x020 41 #define F_ALL_INVLD 0x2 42 #define F_MMU_INV_RANGE 0x1 43 44 #define REG_MMU_INVLD_START_A 0x024 45 #define REG_MMU_INVLD_END_A 0x028 46 47 #define REG_MMU_INV_SEL 0x038 48 #define F_INVLD_EN0 BIT(0) 49 #define F_INVLD_EN1 BIT(1) 50 51 #define REG_MMU_STANDARD_AXI_MODE 0x048 52 #define REG_MMU_DCM_DIS 0x050 53 54 #define REG_MMU_CTRL_REG 0x110 55 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 56 #define F_MMU_TF_PROTECT_SEL_SHIFT(data) \ 57 ((data)->m4u_plat == M4U_MT2712 ? 4 : 5) 58 /* It's named by F_MMU_TF_PROT_SEL in mt2712. */ 59 #define F_MMU_TF_PROTECT_SEL(prot, data) \ 60 (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data)) 61 62 #define REG_MMU_IVRP_PADDR 0x114 63 #define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31)) 64 #define REG_MMU_VLD_PA_RNG 0x118 65 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 66 67 #define REG_MMU_INT_CONTROL0 0x120 68 #define F_L2_MULIT_HIT_EN BIT(0) 69 #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 70 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 71 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 72 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 73 #define F_MISS_FIFO_ERR_INT_EN BIT(6) 74 #define F_INT_CLR_BIT BIT(12) 75 76 #define REG_MMU_INT_MAIN_CONTROL 0x124 77 #define F_INT_TRANSLATION_FAULT BIT(0) 78 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 79 #define F_INT_INVALID_PA_FAULT BIT(2) 80 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 81 #define F_INT_TLB_MISS_FAULT BIT(4) 82 #define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) 83 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) 84 85 #define REG_MMU_CPE_DONE 0x12C 86 87 #define REG_MMU_FAULT_ST1 0x134 88 89 #define REG_MMU_FAULT_VA 0x13c 90 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 91 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 92 93 #define REG_MMU_INVLD_PA 0x140 94 #define REG_MMU_INT_ID 0x150 95 #define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 96 #define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 97 98 #define MTK_PROTECT_PA_ALIGN 128 99 100 /* 101 * Get the local arbiter ID and the portid within the larb arbiter 102 * from mtk_m4u_id which is defined by MTK_M4U_ID. 103 */ 104 #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) 105 #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) 106 107 struct mtk_iommu_domain { 108 spinlock_t pgtlock; /* lock for page table */ 109 110 struct io_pgtable_cfg cfg; 111 struct io_pgtable_ops *iop; 112 113 struct iommu_domain domain; 114 }; 115 116 static struct iommu_ops mtk_iommu_ops; 117 118 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 119 120 #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) 121 122 /* 123 * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain 124 * for the performance. 125 * 126 * Here always return the mtk_iommu_data of the first probed M4U where the 127 * iommu domain information is recorded. 128 */ 129 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) 130 { 131 struct mtk_iommu_data *data; 132 133 for_each_m4u(data) 134 return data; 135 136 return NULL; 137 } 138 139 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 140 { 141 return container_of(dom, struct mtk_iommu_domain, domain); 142 } 143 144 static void mtk_iommu_tlb_flush_all(void *cookie) 145 { 146 struct mtk_iommu_data *data = cookie; 147 148 for_each_m4u(data) { 149 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 150 data->base + REG_MMU_INV_SEL); 151 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 152 wmb(); /* Make sure the tlb flush all done */ 153 } 154 } 155 156 static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size, 157 size_t granule, bool leaf, 158 void *cookie) 159 { 160 struct mtk_iommu_data *data = cookie; 161 162 for_each_m4u(data) { 163 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 164 data->base + REG_MMU_INV_SEL); 165 166 writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); 167 writel_relaxed(iova + size - 1, 168 data->base + REG_MMU_INVLD_END_A); 169 writel_relaxed(F_MMU_INV_RANGE, 170 data->base + REG_MMU_INVALIDATE); 171 data->tlb_flush_active = true; 172 } 173 } 174 175 static void mtk_iommu_tlb_sync(void *cookie) 176 { 177 struct mtk_iommu_data *data = cookie; 178 int ret; 179 u32 tmp; 180 181 for_each_m4u(data) { 182 /* Avoid timing out if there's nothing to wait for */ 183 if (!data->tlb_flush_active) 184 return; 185 186 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 187 tmp, tmp != 0, 10, 100000); 188 if (ret) { 189 dev_warn(data->dev, 190 "Partial TLB flush timed out, falling back to full flush\n"); 191 mtk_iommu_tlb_flush_all(cookie); 192 } 193 /* Clear the CPE status */ 194 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 195 data->tlb_flush_active = false; 196 } 197 } 198 199 static const struct iommu_gather_ops mtk_iommu_gather_ops = { 200 .tlb_flush_all = mtk_iommu_tlb_flush_all, 201 .tlb_add_flush = mtk_iommu_tlb_add_flush_nosync, 202 .tlb_sync = mtk_iommu_tlb_sync, 203 }; 204 205 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 206 { 207 struct mtk_iommu_data *data = dev_id; 208 struct mtk_iommu_domain *dom = data->m4u_dom; 209 u32 int_state, regval, fault_iova, fault_pa; 210 unsigned int fault_larb, fault_port; 211 bool layer, write; 212 213 /* Read error info from registers */ 214 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); 215 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 216 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 217 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 218 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 219 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 220 fault_larb = F_MMU0_INT_ID_LARB_ID(regval); 221 fault_port = F_MMU0_INT_ID_PORT_ID(regval); 222 223 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 224 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 225 dev_err_ratelimited( 226 data->dev, 227 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n", 228 int_state, fault_iova, fault_pa, fault_larb, fault_port, 229 layer, write ? "write" : "read"); 230 } 231 232 /* Interrupt clear */ 233 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); 234 regval |= F_INT_CLR_BIT; 235 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 236 237 mtk_iommu_tlb_flush_all(data); 238 239 return IRQ_HANDLED; 240 } 241 242 static void mtk_iommu_config(struct mtk_iommu_data *data, 243 struct device *dev, bool enable) 244 { 245 struct mtk_smi_larb_iommu *larb_mmu; 246 unsigned int larbid, portid; 247 struct iommu_fwspec *fwspec = dev->iommu_fwspec; 248 int i; 249 250 for (i = 0; i < fwspec->num_ids; ++i) { 251 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 252 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 253 larb_mmu = &data->smi_imu.larb_imu[larbid]; 254 255 dev_dbg(dev, "%s iommu port: %d\n", 256 enable ? "enable" : "disable", portid); 257 258 if (enable) 259 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 260 else 261 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 262 } 263 } 264 265 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) 266 { 267 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 268 269 spin_lock_init(&dom->pgtlock); 270 271 dom->cfg = (struct io_pgtable_cfg) { 272 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 273 IO_PGTABLE_QUIRK_NO_PERMS | 274 IO_PGTABLE_QUIRK_TLBI_ON_MAP, 275 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 276 .ias = 32, 277 .oas = 32, 278 .tlb = &mtk_iommu_gather_ops, 279 .iommu_dev = data->dev, 280 }; 281 282 if (data->enable_4GB) 283 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB; 284 285 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 286 if (!dom->iop) { 287 dev_err(data->dev, "Failed to alloc io pgtable\n"); 288 return -EINVAL; 289 } 290 291 /* Update our support page sizes bitmap */ 292 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 293 return 0; 294 } 295 296 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 297 { 298 struct mtk_iommu_domain *dom; 299 300 if (type != IOMMU_DOMAIN_DMA) 301 return NULL; 302 303 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 304 if (!dom) 305 return NULL; 306 307 if (iommu_get_dma_cookie(&dom->domain)) 308 goto free_dom; 309 310 if (mtk_iommu_domain_finalise(dom)) 311 goto put_dma_cookie; 312 313 dom->domain.geometry.aperture_start = 0; 314 dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); 315 dom->domain.geometry.force_aperture = true; 316 317 return &dom->domain; 318 319 put_dma_cookie: 320 iommu_put_dma_cookie(&dom->domain); 321 free_dom: 322 kfree(dom); 323 return NULL; 324 } 325 326 static void mtk_iommu_domain_free(struct iommu_domain *domain) 327 { 328 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 329 330 free_io_pgtable_ops(dom->iop); 331 iommu_put_dma_cookie(domain); 332 kfree(to_mtk_domain(domain)); 333 } 334 335 static int mtk_iommu_attach_device(struct iommu_domain *domain, 336 struct device *dev) 337 { 338 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 339 struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; 340 341 if (!data) 342 return -ENODEV; 343 344 /* Update the pgtable base address register of the M4U HW */ 345 if (!data->m4u_dom) { 346 data->m4u_dom = dom; 347 writel(dom->cfg.arm_v7s_cfg.ttbr[0], 348 data->base + REG_MMU_PT_BASE_ADDR); 349 } 350 351 mtk_iommu_config(data, dev, true); 352 return 0; 353 } 354 355 static void mtk_iommu_detach_device(struct iommu_domain *domain, 356 struct device *dev) 357 { 358 struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; 359 360 if (!data) 361 return; 362 363 mtk_iommu_config(data, dev, false); 364 } 365 366 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 367 phys_addr_t paddr, size_t size, int prot) 368 { 369 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 370 unsigned long flags; 371 int ret; 372 373 spin_lock_irqsave(&dom->pgtlock, flags); 374 ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32), 375 size, prot); 376 spin_unlock_irqrestore(&dom->pgtlock, flags); 377 378 return ret; 379 } 380 381 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 382 unsigned long iova, size_t size) 383 { 384 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 385 unsigned long flags; 386 size_t unmapsz; 387 388 spin_lock_irqsave(&dom->pgtlock, flags); 389 unmapsz = dom->iop->unmap(dom->iop, iova, size); 390 spin_unlock_irqrestore(&dom->pgtlock, flags); 391 392 return unmapsz; 393 } 394 395 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain) 396 { 397 mtk_iommu_tlb_sync(mtk_iommu_get_m4u_data()); 398 } 399 400 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 401 dma_addr_t iova) 402 { 403 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 404 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 405 unsigned long flags; 406 phys_addr_t pa; 407 408 spin_lock_irqsave(&dom->pgtlock, flags); 409 pa = dom->iop->iova_to_phys(dom->iop, iova); 410 spin_unlock_irqrestore(&dom->pgtlock, flags); 411 412 if (data->enable_4GB) 413 pa |= BIT_ULL(32); 414 415 return pa; 416 } 417 418 static int mtk_iommu_add_device(struct device *dev) 419 { 420 struct mtk_iommu_data *data; 421 struct iommu_group *group; 422 423 if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops) 424 return -ENODEV; /* Not a iommu client device */ 425 426 data = dev->iommu_fwspec->iommu_priv; 427 iommu_device_link(&data->iommu, dev); 428 429 group = iommu_group_get_for_dev(dev); 430 if (IS_ERR(group)) 431 return PTR_ERR(group); 432 433 iommu_group_put(group); 434 return 0; 435 } 436 437 static void mtk_iommu_remove_device(struct device *dev) 438 { 439 struct mtk_iommu_data *data; 440 441 if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops) 442 return; 443 444 data = dev->iommu_fwspec->iommu_priv; 445 iommu_device_unlink(&data->iommu, dev); 446 447 iommu_group_remove_device(dev); 448 iommu_fwspec_free(dev); 449 } 450 451 static struct iommu_group *mtk_iommu_device_group(struct device *dev) 452 { 453 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 454 455 if (!data) 456 return ERR_PTR(-ENODEV); 457 458 /* All the client devices are in the same m4u iommu-group */ 459 if (!data->m4u_group) { 460 data->m4u_group = iommu_group_alloc(); 461 if (IS_ERR(data->m4u_group)) 462 dev_err(dev, "Failed to allocate M4U IOMMU group\n"); 463 } else { 464 iommu_group_ref_get(data->m4u_group); 465 } 466 return data->m4u_group; 467 } 468 469 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 470 { 471 struct platform_device *m4updev; 472 473 if (args->args_count != 1) { 474 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 475 args->args_count); 476 return -EINVAL; 477 } 478 479 if (!dev->iommu_fwspec->iommu_priv) { 480 /* Get the m4u device */ 481 m4updev = of_find_device_by_node(args->np); 482 if (WARN_ON(!m4updev)) 483 return -EINVAL; 484 485 dev->iommu_fwspec->iommu_priv = platform_get_drvdata(m4updev); 486 } 487 488 return iommu_fwspec_add_ids(dev, args->args, 1); 489 } 490 491 static struct iommu_ops mtk_iommu_ops = { 492 .domain_alloc = mtk_iommu_domain_alloc, 493 .domain_free = mtk_iommu_domain_free, 494 .attach_dev = mtk_iommu_attach_device, 495 .detach_dev = mtk_iommu_detach_device, 496 .map = mtk_iommu_map, 497 .unmap = mtk_iommu_unmap, 498 .map_sg = default_iommu_map_sg, 499 .flush_iotlb_all = mtk_iommu_iotlb_sync, 500 .iotlb_sync = mtk_iommu_iotlb_sync, 501 .iova_to_phys = mtk_iommu_iova_to_phys, 502 .add_device = mtk_iommu_add_device, 503 .remove_device = mtk_iommu_remove_device, 504 .device_group = mtk_iommu_device_group, 505 .of_xlate = mtk_iommu_of_xlate, 506 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 507 }; 508 509 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 510 { 511 u32 regval; 512 int ret; 513 514 ret = clk_prepare_enable(data->bclk); 515 if (ret) { 516 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 517 return ret; 518 } 519 520 regval = F_MMU_TF_PROTECT_SEL(2, data); 521 if (data->m4u_plat == M4U_MT8173) 522 regval |= F_MMU_PREFETCH_RT_REPLACE_MOD; 523 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 524 525 regval = F_L2_MULIT_HIT_EN | 526 F_TABLE_WALK_FAULT_INT_EN | 527 F_PREETCH_FIFO_OVERFLOW_INT_EN | 528 F_MISS_FIFO_OVERFLOW_INT_EN | 529 F_PREFETCH_FIFO_ERR_INT_EN | 530 F_MISS_FIFO_ERR_INT_EN; 531 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 532 533 regval = F_INT_TRANSLATION_FAULT | 534 F_INT_MAIN_MULTI_HIT_FAULT | 535 F_INT_INVALID_PA_FAULT | 536 F_INT_ENTRY_REPLACEMENT_FAULT | 537 F_INT_TLB_MISS_FAULT | 538 F_INT_MISS_TRANSACTION_FIFO_FAULT | 539 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 540 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); 541 542 writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB), 543 data->base + REG_MMU_IVRP_PADDR); 544 if (data->enable_4GB && data->m4u_plat != M4U_MT8173) { 545 /* 546 * If 4GB mode is enabled, the validate PA range is from 547 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 548 */ 549 regval = F_MMU_VLD_PA_RNG(7, 4); 550 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); 551 } 552 writel_relaxed(0, data->base + REG_MMU_DCM_DIS); 553 554 /* It's MISC control register whose default value is ok except mt8173.*/ 555 if (data->m4u_plat == M4U_MT8173) 556 writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); 557 558 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 559 dev_name(data->dev), (void *)data)) { 560 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 561 clk_disable_unprepare(data->bclk); 562 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 563 return -ENODEV; 564 } 565 566 return 0; 567 } 568 569 static const struct component_master_ops mtk_iommu_com_ops = { 570 .bind = mtk_iommu_bind, 571 .unbind = mtk_iommu_unbind, 572 }; 573 574 static int mtk_iommu_probe(struct platform_device *pdev) 575 { 576 struct mtk_iommu_data *data; 577 struct device *dev = &pdev->dev; 578 struct resource *res; 579 resource_size_t ioaddr; 580 struct component_match *match = NULL; 581 void *protect; 582 int i, larb_nr, ret; 583 584 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 585 if (!data) 586 return -ENOMEM; 587 data->dev = dev; 588 data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev); 589 590 /* Protect memory. HW will access here while translation fault.*/ 591 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 592 if (!protect) 593 return -ENOMEM; 594 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 595 596 /* Whether the current dram is over 4GB */ 597 data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT)); 598 599 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 600 data->base = devm_ioremap_resource(dev, res); 601 if (IS_ERR(data->base)) 602 return PTR_ERR(data->base); 603 ioaddr = res->start; 604 605 data->irq = platform_get_irq(pdev, 0); 606 if (data->irq < 0) 607 return data->irq; 608 609 data->bclk = devm_clk_get(dev, "bclk"); 610 if (IS_ERR(data->bclk)) 611 return PTR_ERR(data->bclk); 612 613 larb_nr = of_count_phandle_with_args(dev->of_node, 614 "mediatek,larbs", NULL); 615 if (larb_nr < 0) 616 return larb_nr; 617 data->smi_imu.larb_nr = larb_nr; 618 619 for (i = 0; i < larb_nr; i++) { 620 struct device_node *larbnode; 621 struct platform_device *plarbdev; 622 u32 id; 623 624 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 625 if (!larbnode) 626 return -EINVAL; 627 628 if (!of_device_is_available(larbnode)) 629 continue; 630 631 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 632 if (ret)/* The id is consecutive if there is no this property */ 633 id = i; 634 635 plarbdev = of_find_device_by_node(larbnode); 636 if (!plarbdev) 637 return -EPROBE_DEFER; 638 data->smi_imu.larb_imu[id].dev = &plarbdev->dev; 639 640 component_match_add_release(dev, &match, release_of, 641 compare_of, larbnode); 642 } 643 644 platform_set_drvdata(pdev, data); 645 646 ret = mtk_iommu_hw_init(data); 647 if (ret) 648 return ret; 649 650 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 651 "mtk-iommu.%pa", &ioaddr); 652 if (ret) 653 return ret; 654 655 iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); 656 iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); 657 658 ret = iommu_device_register(&data->iommu); 659 if (ret) 660 return ret; 661 662 list_add_tail(&data->list, &m4ulist); 663 664 if (!iommu_present(&platform_bus_type)) 665 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 666 667 return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 668 } 669 670 static int mtk_iommu_remove(struct platform_device *pdev) 671 { 672 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 673 674 iommu_device_sysfs_remove(&data->iommu); 675 iommu_device_unregister(&data->iommu); 676 677 if (iommu_present(&platform_bus_type)) 678 bus_set_iommu(&platform_bus_type, NULL); 679 680 clk_disable_unprepare(data->bclk); 681 devm_free_irq(&pdev->dev, data->irq, data); 682 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 683 return 0; 684 } 685 686 static int __maybe_unused mtk_iommu_suspend(struct device *dev) 687 { 688 struct mtk_iommu_data *data = dev_get_drvdata(dev); 689 struct mtk_iommu_suspend_reg *reg = &data->reg; 690 void __iomem *base = data->base; 691 692 reg->standard_axi_mode = readl_relaxed(base + 693 REG_MMU_STANDARD_AXI_MODE); 694 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 695 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 696 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); 697 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 698 clk_disable_unprepare(data->bclk); 699 return 0; 700 } 701 702 static int __maybe_unused mtk_iommu_resume(struct device *dev) 703 { 704 struct mtk_iommu_data *data = dev_get_drvdata(dev); 705 struct mtk_iommu_suspend_reg *reg = &data->reg; 706 void __iomem *base = data->base; 707 int ret; 708 709 ret = clk_prepare_enable(data->bclk); 710 if (ret) { 711 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 712 return ret; 713 } 714 writel_relaxed(reg->standard_axi_mode, 715 base + REG_MMU_STANDARD_AXI_MODE); 716 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 717 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 718 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); 719 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); 720 writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB), 721 base + REG_MMU_IVRP_PADDR); 722 if (data->m4u_dom) 723 writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0], 724 base + REG_MMU_PT_BASE_ADDR); 725 return 0; 726 } 727 728 static const struct dev_pm_ops mtk_iommu_pm_ops = { 729 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) 730 }; 731 732 static const struct of_device_id mtk_iommu_of_ids[] = { 733 { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712}, 734 { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173}, 735 {} 736 }; 737 738 static struct platform_driver mtk_iommu_driver = { 739 .probe = mtk_iommu_probe, 740 .remove = mtk_iommu_remove, 741 .driver = { 742 .name = "mtk-iommu", 743 .of_match_table = of_match_ptr(mtk_iommu_of_ids), 744 .pm = &mtk_iommu_pm_ops, 745 } 746 }; 747 748 static int __init mtk_iommu_init(void) 749 { 750 int ret; 751 752 ret = platform_driver_register(&mtk_iommu_driver); 753 if (ret != 0) 754 pr_err("Failed to register MTK IOMMU driver\n"); 755 756 return ret; 757 } 758 759 subsys_initcall(mtk_iommu_init) 760