1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/bug.h> 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/device.h> 11 #include <linux/dma-direct.h> 12 #include <linux/dma-iommu.h> 13 #include <linux/err.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/iommu.h> 17 #include <linux/iopoll.h> 18 #include <linux/list.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/soc/mediatek/infracfg.h> 30 #include <asm/barrier.h> 31 #include <soc/mediatek/smi.h> 32 33 #include "mtk_iommu.h" 34 35 #define REG_MMU_PT_BASE_ADDR 0x000 36 #define MMU_PT_ADDR_MASK GENMASK(31, 7) 37 38 #define REG_MMU_INVALIDATE 0x020 39 #define F_ALL_INVLD 0x2 40 #define F_MMU_INV_RANGE 0x1 41 42 #define REG_MMU_INVLD_START_A 0x024 43 #define REG_MMU_INVLD_END_A 0x028 44 45 #define REG_MMU_INV_SEL_GEN2 0x02c 46 #define REG_MMU_INV_SEL_GEN1 0x038 47 #define F_INVLD_EN0 BIT(0) 48 #define F_INVLD_EN1 BIT(1) 49 50 #define REG_MMU_MISC_CTRL 0x048 51 #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 52 #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 53 54 #define REG_MMU_DCM_DIS 0x050 55 #define REG_MMU_WR_LEN_CTRL 0x054 56 #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 57 58 #define REG_MMU_CTRL_REG 0x110 59 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 60 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 61 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 62 63 #define REG_MMU_IVRP_PADDR 0x114 64 65 #define REG_MMU_VLD_PA_RNG 0x118 66 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 67 68 #define REG_MMU_INT_CONTROL0 0x120 69 #define F_L2_MULIT_HIT_EN BIT(0) 70 #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 71 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 72 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 73 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 74 #define F_MISS_FIFO_ERR_INT_EN BIT(6) 75 #define F_INT_CLR_BIT BIT(12) 76 77 #define REG_MMU_INT_MAIN_CONTROL 0x124 78 /* mmu0 | mmu1 */ 79 #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 80 #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 81 #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 82 #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 83 #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 84 #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 85 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 86 87 #define REG_MMU_CPE_DONE 0x12C 88 89 #define REG_MMU_FAULT_ST1 0x134 90 #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 91 #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 92 93 #define REG_MMU0_FAULT_VA 0x13c 94 #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 95 #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 96 #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 97 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 98 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 99 100 #define REG_MMU0_INVLD_PA 0x140 101 #define REG_MMU1_FAULT_VA 0x144 102 #define REG_MMU1_INVLD_PA 0x148 103 #define REG_MMU0_INT_ID 0x150 104 #define REG_MMU1_INT_ID 0x154 105 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 106 #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 107 #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 108 #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 109 110 #define MTK_PROTECT_PA_ALIGN 256 111 112 #define HAS_4GB_MODE BIT(0) 113 /* HW will use the EMI clock if there isn't the "bclk". */ 114 #define HAS_BCLK BIT(1) 115 #define HAS_VLD_PA_RNG BIT(2) 116 #define RESET_AXI BIT(3) 117 #define OUT_ORDER_WR_EN BIT(4) 118 #define HAS_SUB_COMM BIT(5) 119 #define WR_THROT_EN BIT(6) 120 #define HAS_LEGACY_IVRP_PADDR BIT(7) 121 #define IOVA_34_EN BIT(8) 122 123 #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ 124 ((((pdata)->flags) & (_x)) == (_x)) 125 126 struct mtk_iommu_domain { 127 struct io_pgtable_cfg cfg; 128 struct io_pgtable_ops *iop; 129 130 struct mtk_iommu_data *data; 131 struct iommu_domain domain; 132 }; 133 134 static const struct iommu_ops mtk_iommu_ops; 135 136 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data); 137 138 #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 139 dma_addr_t _addr = iova; \ 140 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 141 }) 142 143 /* 144 * In M4U 4GB mode, the physical address is remapped as below: 145 * 146 * CPU Physical address: 147 * ==================== 148 * 149 * 0 1G 2G 3G 4G 5G 150 * |---A---|---B---|---C---|---D---|---E---| 151 * +--I/O--+------------Memory-------------+ 152 * 153 * IOMMU output physical address: 154 * ============================= 155 * 156 * 4G 5G 6G 7G 8G 157 * |---E---|---B---|---C---|---D---| 158 * +------------Memory-------------+ 159 * 160 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 161 * bit32 of the CPU physical address always is needed to set, and for Region 162 * 'E', the CPU physical address keep as is. 163 * Additionally, The iommu consumers always use the CPU phyiscal address. 164 */ 165 #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 166 167 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 168 169 #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) 170 171 struct mtk_iommu_iova_region { 172 dma_addr_t iova_base; 173 unsigned long long size; 174 }; 175 176 static const struct mtk_iommu_iova_region single_domain[] = { 177 {.iova_base = 0, .size = SZ_4G}, 178 }; 179 180 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { 181 { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */ 182 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 183 { .iova_base = SZ_4G, .size = SZ_4G}, /* vdec: 4G ~ 8G */ 184 { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* CAM/MDP: 8G ~ 12G */ 185 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 186 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 187 #endif 188 }; 189 190 /* 191 * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain 192 * for the performance. 193 * 194 * Here always return the mtk_iommu_data of the first probed M4U where the 195 * iommu domain information is recorded. 196 */ 197 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) 198 { 199 struct mtk_iommu_data *data; 200 201 for_each_m4u(data) 202 return data; 203 204 return NULL; 205 } 206 207 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 208 { 209 return container_of(dom, struct mtk_iommu_domain, domain); 210 } 211 212 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 213 { 214 for_each_m4u(data) { 215 if (pm_runtime_get_if_in_use(data->dev) <= 0) 216 continue; 217 218 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 219 data->base + data->plat_data->inv_sel_reg); 220 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 221 wmb(); /* Make sure the tlb flush all done */ 222 223 pm_runtime_put(data->dev); 224 } 225 } 226 227 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 228 size_t granule, 229 struct mtk_iommu_data *data) 230 { 231 bool has_pm = !!data->dev->pm_domain; 232 unsigned long flags; 233 int ret; 234 u32 tmp; 235 236 for_each_m4u(data) { 237 if (has_pm) { 238 if (pm_runtime_get_if_in_use(data->dev) <= 0) 239 continue; 240 } 241 242 spin_lock_irqsave(&data->tlb_lock, flags); 243 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 244 data->base + data->plat_data->inv_sel_reg); 245 246 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), 247 data->base + REG_MMU_INVLD_START_A); 248 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 249 data->base + REG_MMU_INVLD_END_A); 250 writel_relaxed(F_MMU_INV_RANGE, 251 data->base + REG_MMU_INVALIDATE); 252 253 /* tlb sync */ 254 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 255 tmp, tmp != 0, 10, 1000); 256 if (ret) { 257 dev_warn(data->dev, 258 "Partial TLB flush timed out, falling back to full flush\n"); 259 mtk_iommu_tlb_flush_all(data); 260 } 261 /* Clear the CPE status */ 262 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 263 spin_unlock_irqrestore(&data->tlb_lock, flags); 264 265 if (has_pm) 266 pm_runtime_put(data->dev); 267 } 268 } 269 270 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 271 { 272 struct mtk_iommu_data *data = dev_id; 273 struct mtk_iommu_domain *dom = data->m4u_dom; 274 unsigned int fault_larb, fault_port, sub_comm = 0; 275 u32 int_state, regval, va34_32, pa34_32; 276 u64 fault_iova, fault_pa; 277 bool layer, write; 278 279 /* Read error info from registers */ 280 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); 281 if (int_state & F_REG_MMU0_FAULT_MASK) { 282 regval = readl_relaxed(data->base + REG_MMU0_INT_ID); 283 fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); 284 fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); 285 } else { 286 regval = readl_relaxed(data->base + REG_MMU1_INT_ID); 287 fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); 288 fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); 289 } 290 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 291 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 292 if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) { 293 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 294 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 295 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 296 fault_iova |= (u64)va34_32 << 32; 297 fault_pa |= (u64)pa34_32 << 32; 298 } 299 300 fault_port = F_MMU_INT_ID_PORT_ID(regval); 301 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { 302 fault_larb = F_MMU_INT_ID_COMM_ID(regval); 303 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 304 } else { 305 fault_larb = F_MMU_INT_ID_LARB_ID(regval); 306 } 307 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 308 309 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 310 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 311 dev_err_ratelimited( 312 data->dev, 313 "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n", 314 int_state, fault_iova, fault_pa, fault_larb, fault_port, 315 layer, write ? "write" : "read"); 316 } 317 318 /* Interrupt clear */ 319 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); 320 regval |= F_INT_CLR_BIT; 321 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 322 323 mtk_iommu_tlb_flush_all(data); 324 325 return IRQ_HANDLED; 326 } 327 328 static int mtk_iommu_get_domain_id(struct device *dev, 329 const struct mtk_iommu_plat_data *plat_data) 330 { 331 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; 332 const struct bus_dma_region *dma_rgn = dev->dma_range_map; 333 int i, candidate = -1; 334 dma_addr_t dma_end; 335 336 if (!dma_rgn || plat_data->iova_region_nr == 1) 337 return 0; 338 339 dma_end = dma_rgn->dma_start + dma_rgn->size - 1; 340 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { 341 /* Best fit. */ 342 if (dma_rgn->dma_start == rgn->iova_base && 343 dma_end == rgn->iova_base + rgn->size - 1) 344 return i; 345 /* ok if it is inside this region. */ 346 if (dma_rgn->dma_start >= rgn->iova_base && 347 dma_end < rgn->iova_base + rgn->size) 348 candidate = i; 349 } 350 351 if (candidate >= 0) 352 return candidate; 353 dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n", 354 &dma_rgn->dma_start, dma_rgn->size); 355 return -EINVAL; 356 } 357 358 static void mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 359 bool enable, unsigned int domid) 360 { 361 struct mtk_smi_larb_iommu *larb_mmu; 362 unsigned int larbid, portid; 363 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 364 const struct mtk_iommu_iova_region *region; 365 int i; 366 367 for (i = 0; i < fwspec->num_ids; ++i) { 368 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 369 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 370 371 larb_mmu = &data->larb_imu[larbid]; 372 373 region = data->plat_data->iova_region + domid; 374 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 375 376 dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n", 377 enable ? "enable" : "disable", dev_name(larb_mmu->dev), 378 portid, domid, larb_mmu->bank[portid]); 379 380 if (enable) 381 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 382 else 383 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 384 } 385 } 386 387 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 388 struct mtk_iommu_data *data, 389 unsigned int domid) 390 { 391 const struct mtk_iommu_iova_region *region; 392 393 /* Use the exist domain as there is only one pgtable here. */ 394 if (data->m4u_dom) { 395 dom->iop = data->m4u_dom->iop; 396 dom->cfg = data->m4u_dom->cfg; 397 dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap; 398 goto update_iova_region; 399 } 400 401 dom->cfg = (struct io_pgtable_cfg) { 402 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 403 IO_PGTABLE_QUIRK_NO_PERMS | 404 IO_PGTABLE_QUIRK_ARM_MTK_EXT, 405 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 406 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 407 .iommu_dev = data->dev, 408 }; 409 410 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 411 dom->cfg.oas = data->enable_4GB ? 33 : 32; 412 else 413 dom->cfg.oas = 35; 414 415 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 416 if (!dom->iop) { 417 dev_err(data->dev, "Failed to alloc io pgtable\n"); 418 return -EINVAL; 419 } 420 421 /* Update our support page sizes bitmap */ 422 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 423 424 update_iova_region: 425 /* Update the iova region for this domain */ 426 region = data->plat_data->iova_region + domid; 427 dom->domain.geometry.aperture_start = region->iova_base; 428 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 429 dom->domain.geometry.force_aperture = true; 430 return 0; 431 } 432 433 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 434 { 435 struct mtk_iommu_domain *dom; 436 437 if (type != IOMMU_DOMAIN_DMA) 438 return NULL; 439 440 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 441 if (!dom) 442 return NULL; 443 444 if (iommu_get_dma_cookie(&dom->domain)) { 445 kfree(dom); 446 return NULL; 447 } 448 449 return &dom->domain; 450 } 451 452 static void mtk_iommu_domain_free(struct iommu_domain *domain) 453 { 454 iommu_put_dma_cookie(domain); 455 kfree(to_mtk_domain(domain)); 456 } 457 458 static int mtk_iommu_attach_device(struct iommu_domain *domain, 459 struct device *dev) 460 { 461 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 462 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 463 struct device *m4udev = data->dev; 464 int ret, domid; 465 466 domid = mtk_iommu_get_domain_id(dev, data->plat_data); 467 if (domid < 0) 468 return domid; 469 470 if (!dom->data) { 471 if (mtk_iommu_domain_finalise(dom, data, domid)) 472 return -ENODEV; 473 dom->data = data; 474 } 475 476 if (!data->m4u_dom) { /* Initialize the M4U HW */ 477 ret = pm_runtime_resume_and_get(m4udev); 478 if (ret < 0) 479 return ret; 480 481 ret = mtk_iommu_hw_init(data); 482 if (ret) { 483 pm_runtime_put(m4udev); 484 return ret; 485 } 486 data->m4u_dom = dom; 487 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, 488 data->base + REG_MMU_PT_BASE_ADDR); 489 490 pm_runtime_put(m4udev); 491 } 492 493 mtk_iommu_config(data, dev, true, domid); 494 return 0; 495 } 496 497 static void mtk_iommu_detach_device(struct iommu_domain *domain, 498 struct device *dev) 499 { 500 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 501 502 mtk_iommu_config(data, dev, false, 0); 503 } 504 505 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 506 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 507 { 508 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 509 510 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 511 if (dom->data->enable_4GB) 512 paddr |= BIT_ULL(32); 513 514 /* Synchronize with the tlb_lock */ 515 return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); 516 } 517 518 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 519 unsigned long iova, size_t size, 520 struct iommu_iotlb_gather *gather) 521 { 522 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 523 unsigned long end = iova + size - 1; 524 525 if (gather->start > iova) 526 gather->start = iova; 527 if (gather->end < end) 528 gather->end = end; 529 return dom->iop->unmap(dom->iop, iova, size, gather); 530 } 531 532 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 533 { 534 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 535 536 mtk_iommu_tlb_flush_all(dom->data); 537 } 538 539 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 540 struct iommu_iotlb_gather *gather) 541 { 542 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 543 size_t length = gather->end - gather->start + 1; 544 545 mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, 546 dom->data); 547 } 548 549 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 550 size_t size) 551 { 552 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 553 554 mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data); 555 } 556 557 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 558 dma_addr_t iova) 559 { 560 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 561 phys_addr_t pa; 562 563 pa = dom->iop->iova_to_phys(dom->iop, iova); 564 if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 565 pa &= ~BIT_ULL(32); 566 567 return pa; 568 } 569 570 static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 571 { 572 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 573 struct mtk_iommu_data *data; 574 575 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 576 return ERR_PTR(-ENODEV); /* Not a iommu client device */ 577 578 data = dev_iommu_priv_get(dev); 579 580 return &data->iommu; 581 } 582 583 static void mtk_iommu_release_device(struct device *dev) 584 { 585 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 586 587 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 588 return; 589 590 iommu_fwspec_free(dev); 591 } 592 593 static struct iommu_group *mtk_iommu_device_group(struct device *dev) 594 { 595 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 596 struct iommu_group *group; 597 int domid; 598 599 if (!data) 600 return ERR_PTR(-ENODEV); 601 602 domid = mtk_iommu_get_domain_id(dev, data->plat_data); 603 if (domid < 0) 604 return ERR_PTR(domid); 605 606 group = data->m4u_group[domid]; 607 if (!group) { 608 group = iommu_group_alloc(); 609 if (!IS_ERR(group)) 610 data->m4u_group[domid] = group; 611 } else { 612 iommu_group_ref_get(group); 613 } 614 return group; 615 } 616 617 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 618 { 619 struct platform_device *m4updev; 620 621 if (args->args_count != 1) { 622 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 623 args->args_count); 624 return -EINVAL; 625 } 626 627 if (!dev_iommu_priv_get(dev)) { 628 /* Get the m4u device */ 629 m4updev = of_find_device_by_node(args->np); 630 if (WARN_ON(!m4updev)) 631 return -EINVAL; 632 633 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 634 } 635 636 return iommu_fwspec_add_ids(dev, args->args, 1); 637 } 638 639 static void mtk_iommu_get_resv_regions(struct device *dev, 640 struct list_head *head) 641 { 642 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 643 unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i; 644 const struct mtk_iommu_iova_region *resv, *curdom; 645 struct iommu_resv_region *region; 646 int prot = IOMMU_WRITE | IOMMU_READ; 647 648 if ((int)domid < 0) 649 return; 650 curdom = data->plat_data->iova_region + domid; 651 for (i = 0; i < data->plat_data->iova_region_nr; i++) { 652 resv = data->plat_data->iova_region + i; 653 654 /* Only reserve when the region is inside the current domain */ 655 if (resv->iova_base <= curdom->iova_base || 656 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 657 continue; 658 659 region = iommu_alloc_resv_region(resv->iova_base, resv->size, 660 prot, IOMMU_RESV_RESERVED); 661 if (!region) 662 return; 663 664 list_add_tail(®ion->list, head); 665 } 666 } 667 668 static const struct iommu_ops mtk_iommu_ops = { 669 .domain_alloc = mtk_iommu_domain_alloc, 670 .domain_free = mtk_iommu_domain_free, 671 .attach_dev = mtk_iommu_attach_device, 672 .detach_dev = mtk_iommu_detach_device, 673 .map = mtk_iommu_map, 674 .unmap = mtk_iommu_unmap, 675 .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 676 .iotlb_sync = mtk_iommu_iotlb_sync, 677 .iotlb_sync_map = mtk_iommu_sync_map, 678 .iova_to_phys = mtk_iommu_iova_to_phys, 679 .probe_device = mtk_iommu_probe_device, 680 .release_device = mtk_iommu_release_device, 681 .device_group = mtk_iommu_device_group, 682 .of_xlate = mtk_iommu_of_xlate, 683 .get_resv_regions = mtk_iommu_get_resv_regions, 684 .put_resv_regions = generic_iommu_put_resv_regions, 685 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 686 .owner = THIS_MODULE, 687 }; 688 689 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 690 { 691 u32 regval; 692 693 if (data->plat_data->m4u_plat == M4U_MT8173) { 694 regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 695 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 696 } else { 697 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); 698 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 699 } 700 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 701 702 regval = F_L2_MULIT_HIT_EN | 703 F_TABLE_WALK_FAULT_INT_EN | 704 F_PREETCH_FIFO_OVERFLOW_INT_EN | 705 F_MISS_FIFO_OVERFLOW_INT_EN | 706 F_PREFETCH_FIFO_ERR_INT_EN | 707 F_MISS_FIFO_ERR_INT_EN; 708 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 709 710 regval = F_INT_TRANSLATION_FAULT | 711 F_INT_MAIN_MULTI_HIT_FAULT | 712 F_INT_INVALID_PA_FAULT | 713 F_INT_ENTRY_REPLACEMENT_FAULT | 714 F_INT_TLB_MISS_FAULT | 715 F_INT_MISS_TRANSACTION_FIFO_FAULT | 716 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 717 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); 718 719 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 720 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 721 else 722 regval = lower_32_bits(data->protect_base) | 723 upper_32_bits(data->protect_base); 724 writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); 725 726 if (data->enable_4GB && 727 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 728 /* 729 * If 4GB mode is enabled, the validate PA range is from 730 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 731 */ 732 regval = F_MMU_VLD_PA_RNG(7, 4); 733 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); 734 } 735 writel_relaxed(0, data->base + REG_MMU_DCM_DIS); 736 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 737 /* write command throttling mode */ 738 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); 739 regval &= ~F_MMU_WR_THROT_DIS_MASK; 740 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); 741 } 742 743 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 744 /* The register is called STANDARD_AXI_MODE in this case */ 745 regval = 0; 746 } else { 747 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); 748 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 749 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 750 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 751 } 752 writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); 753 754 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 755 dev_name(data->dev), (void *)data)) { 756 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 757 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 758 return -ENODEV; 759 } 760 761 return 0; 762 } 763 764 static const struct component_master_ops mtk_iommu_com_ops = { 765 .bind = mtk_iommu_bind, 766 .unbind = mtk_iommu_unbind, 767 }; 768 769 static int mtk_iommu_probe(struct platform_device *pdev) 770 { 771 struct mtk_iommu_data *data; 772 struct device *dev = &pdev->dev; 773 struct device_node *larbnode, *smicomm_node; 774 struct platform_device *plarbdev; 775 struct device_link *link; 776 struct resource *res; 777 resource_size_t ioaddr; 778 struct component_match *match = NULL; 779 struct regmap *infracfg; 780 void *protect; 781 int i, larb_nr, ret; 782 u32 val; 783 char *p; 784 785 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 786 if (!data) 787 return -ENOMEM; 788 data->dev = dev; 789 data->plat_data = of_device_get_match_data(dev); 790 791 /* Protect memory. HW will access here while translation fault.*/ 792 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 793 if (!protect) 794 return -ENOMEM; 795 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 796 797 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 798 switch (data->plat_data->m4u_plat) { 799 case M4U_MT2712: 800 p = "mediatek,mt2712-infracfg"; 801 break; 802 case M4U_MT8173: 803 p = "mediatek,mt8173-infracfg"; 804 break; 805 default: 806 p = NULL; 807 } 808 809 infracfg = syscon_regmap_lookup_by_compatible(p); 810 811 if (IS_ERR(infracfg)) 812 return PTR_ERR(infracfg); 813 814 ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 815 if (ret) 816 return ret; 817 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 818 } 819 820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 821 data->base = devm_ioremap_resource(dev, res); 822 if (IS_ERR(data->base)) 823 return PTR_ERR(data->base); 824 ioaddr = res->start; 825 826 data->irq = platform_get_irq(pdev, 0); 827 if (data->irq < 0) 828 return data->irq; 829 830 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 831 data->bclk = devm_clk_get(dev, "bclk"); 832 if (IS_ERR(data->bclk)) 833 return PTR_ERR(data->bclk); 834 } 835 836 larb_nr = of_count_phandle_with_args(dev->of_node, 837 "mediatek,larbs", NULL); 838 if (larb_nr < 0) 839 return larb_nr; 840 841 for (i = 0; i < larb_nr; i++) { 842 u32 id; 843 844 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 845 if (!larbnode) 846 return -EINVAL; 847 848 if (!of_device_is_available(larbnode)) { 849 of_node_put(larbnode); 850 continue; 851 } 852 853 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 854 if (ret)/* The id is consecutive if there is no this property */ 855 id = i; 856 857 plarbdev = of_find_device_by_node(larbnode); 858 if (!plarbdev) { 859 of_node_put(larbnode); 860 return -EPROBE_DEFER; 861 } 862 data->larb_imu[id].dev = &plarbdev->dev; 863 864 component_match_add_release(dev, &match, release_of, 865 compare_of, larbnode); 866 } 867 868 /* Get smi-common dev from the last larb. */ 869 smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 870 if (!smicomm_node) 871 return -EINVAL; 872 873 plarbdev = of_find_device_by_node(smicomm_node); 874 of_node_put(smicomm_node); 875 data->smicomm_dev = &plarbdev->dev; 876 877 pm_runtime_enable(dev); 878 879 link = device_link_add(data->smicomm_dev, dev, 880 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 881 if (!link) { 882 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 883 ret = -EINVAL; 884 goto out_runtime_disable; 885 } 886 887 platform_set_drvdata(pdev, data); 888 889 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 890 "mtk-iommu.%pa", &ioaddr); 891 if (ret) 892 goto out_link_remove; 893 894 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 895 if (ret) 896 goto out_sysfs_remove; 897 898 spin_lock_init(&data->tlb_lock); 899 list_add_tail(&data->list, &m4ulist); 900 901 if (!iommu_present(&platform_bus_type)) { 902 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 903 if (ret) 904 goto out_list_del; 905 } 906 907 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 908 if (ret) 909 goto out_bus_set_null; 910 return ret; 911 912 out_bus_set_null: 913 bus_set_iommu(&platform_bus_type, NULL); 914 out_list_del: 915 list_del(&data->list); 916 iommu_device_unregister(&data->iommu); 917 out_sysfs_remove: 918 iommu_device_sysfs_remove(&data->iommu); 919 out_link_remove: 920 device_link_remove(data->smicomm_dev, dev); 921 out_runtime_disable: 922 pm_runtime_disable(dev); 923 return ret; 924 } 925 926 static int mtk_iommu_remove(struct platform_device *pdev) 927 { 928 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 929 930 iommu_device_sysfs_remove(&data->iommu); 931 iommu_device_unregister(&data->iommu); 932 933 if (iommu_present(&platform_bus_type)) 934 bus_set_iommu(&platform_bus_type, NULL); 935 936 clk_disable_unprepare(data->bclk); 937 device_link_remove(data->smicomm_dev, &pdev->dev); 938 pm_runtime_disable(&pdev->dev); 939 devm_free_irq(&pdev->dev, data->irq, data); 940 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 941 return 0; 942 } 943 944 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 945 { 946 struct mtk_iommu_data *data = dev_get_drvdata(dev); 947 struct mtk_iommu_suspend_reg *reg = &data->reg; 948 void __iomem *base = data->base; 949 950 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 951 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 952 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 953 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 954 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); 955 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 956 reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); 957 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 958 clk_disable_unprepare(data->bclk); 959 return 0; 960 } 961 962 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 963 { 964 struct mtk_iommu_data *data = dev_get_drvdata(dev); 965 struct mtk_iommu_suspend_reg *reg = &data->reg; 966 struct mtk_iommu_domain *m4u_dom = data->m4u_dom; 967 void __iomem *base = data->base; 968 int ret; 969 970 ret = clk_prepare_enable(data->bclk); 971 if (ret) { 972 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 973 return ret; 974 } 975 976 /* 977 * Uppon first resume, only enable the clk and return, since the values of the 978 * registers are not yet set. 979 */ 980 if (!m4u_dom) 981 return 0; 982 983 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 984 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 985 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 986 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 987 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); 988 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); 989 writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); 990 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 991 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); 992 return 0; 993 } 994 995 static const struct dev_pm_ops mtk_iommu_pm_ops = { 996 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 997 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 998 pm_runtime_force_resume) 999 }; 1000 1001 static const struct mtk_iommu_plat_data mt2712_data = { 1002 .m4u_plat = M4U_MT2712, 1003 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG, 1004 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1005 .iova_region = single_domain, 1006 .iova_region_nr = ARRAY_SIZE(single_domain), 1007 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1008 }; 1009 1010 static const struct mtk_iommu_plat_data mt6779_data = { 1011 .m4u_plat = M4U_MT6779, 1012 .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, 1013 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1014 .iova_region = single_domain, 1015 .iova_region_nr = ARRAY_SIZE(single_domain), 1016 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1017 }; 1018 1019 static const struct mtk_iommu_plat_data mt8167_data = { 1020 .m4u_plat = M4U_MT8167, 1021 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR, 1022 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1023 .iova_region = single_domain, 1024 .iova_region_nr = ARRAY_SIZE(single_domain), 1025 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 1026 }; 1027 1028 static const struct mtk_iommu_plat_data mt8173_data = { 1029 .m4u_plat = M4U_MT8173, 1030 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1031 HAS_LEGACY_IVRP_PADDR, 1032 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1033 .iova_region = single_domain, 1034 .iova_region_nr = ARRAY_SIZE(single_domain), 1035 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1036 }; 1037 1038 static const struct mtk_iommu_plat_data mt8183_data = { 1039 .m4u_plat = M4U_MT8183, 1040 .flags = RESET_AXI, 1041 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1042 .iova_region = single_domain, 1043 .iova_region_nr = ARRAY_SIZE(single_domain), 1044 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1045 }; 1046 1047 static const struct mtk_iommu_plat_data mt8192_data = { 1048 .m4u_plat = M4U_MT8192, 1049 .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN | 1050 WR_THROT_EN | IOVA_34_EN, 1051 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1052 .iova_region = mt8192_multi_dom, 1053 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1054 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 1055 {0, 14, 16}, {0, 13, 18, 17}}, 1056 }; 1057 1058 static const struct of_device_id mtk_iommu_of_ids[] = { 1059 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1060 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 1061 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1062 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1063 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 1064 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1065 {} 1066 }; 1067 1068 static struct platform_driver mtk_iommu_driver = { 1069 .probe = mtk_iommu_probe, 1070 .remove = mtk_iommu_remove, 1071 .driver = { 1072 .name = "mtk-iommu", 1073 .of_match_table = mtk_iommu_of_ids, 1074 .pm = &mtk_iommu_pm_ops, 1075 } 1076 }; 1077 module_platform_driver(mtk_iommu_driver); 1078 1079 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 1080 MODULE_LICENSE("GPL v2"); 1081