1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/bug.h> 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/device.h> 11 #include <linux/dma-direct.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iommu.h> 16 #include <linux/iopoll.h> 17 #include <linux/io-pgtable.h> 18 #include <linux/list.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/pci.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regmap.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/soc/mediatek/infracfg.h> 31 #include <asm/barrier.h> 32 #include <soc/mediatek/smi.h> 33 34 #include <dt-bindings/memory/mtk-memory-port.h> 35 36 #define REG_MMU_PT_BASE_ADDR 0x000 37 38 #define REG_MMU_INVALIDATE 0x020 39 #define F_ALL_INVLD 0x2 40 #define F_MMU_INV_RANGE 0x1 41 42 #define REG_MMU_INVLD_START_A 0x024 43 #define REG_MMU_INVLD_END_A 0x028 44 45 #define REG_MMU_INV_SEL_GEN2 0x02c 46 #define REG_MMU_INV_SEL_GEN1 0x038 47 #define F_INVLD_EN0 BIT(0) 48 #define F_INVLD_EN1 BIT(1) 49 50 #define REG_MMU_MISC_CTRL 0x048 51 #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 52 #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 53 54 #define REG_MMU_DCM_DIS 0x050 55 #define F_MMU_DCM BIT(8) 56 57 #define REG_MMU_WR_LEN_CTRL 0x054 58 #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 59 60 #define REG_MMU_CTRL_REG 0x110 61 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 62 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 63 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 64 65 #define REG_MMU_IVRP_PADDR 0x114 66 67 #define REG_MMU_VLD_PA_RNG 0x118 68 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 69 70 #define REG_MMU_INT_CONTROL0 0x120 71 #define F_L2_MULIT_HIT_EN BIT(0) 72 #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 73 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 74 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 75 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 76 #define F_MISS_FIFO_ERR_INT_EN BIT(6) 77 #define F_INT_CLR_BIT BIT(12) 78 79 #define REG_MMU_INT_MAIN_CONTROL 0x124 80 /* mmu0 | mmu1 */ 81 #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 82 #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 83 #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 84 #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 85 #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 86 #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 87 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 88 89 #define REG_MMU_CPE_DONE 0x12C 90 91 #define REG_MMU_FAULT_ST1 0x134 92 #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 93 #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 94 95 #define REG_MMU0_FAULT_VA 0x13c 96 #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 97 #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 98 #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 99 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 100 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 101 102 #define REG_MMU0_INVLD_PA 0x140 103 #define REG_MMU1_FAULT_VA 0x144 104 #define REG_MMU1_INVLD_PA 0x148 105 #define REG_MMU0_INT_ID 0x150 106 #define REG_MMU1_INT_ID 0x154 107 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 108 #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 109 #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) 110 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) 111 #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 112 #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 113 114 #define MTK_PROTECT_PA_ALIGN 256 115 #define MTK_IOMMU_BANK_SZ 0x1000 116 117 #define PERICFG_IOMMU_1 0x714 118 119 #define HAS_4GB_MODE BIT(0) 120 /* HW will use the EMI clock if there isn't the "bclk". */ 121 #define HAS_BCLK BIT(1) 122 #define HAS_VLD_PA_RNG BIT(2) 123 #define RESET_AXI BIT(3) 124 #define OUT_ORDER_WR_EN BIT(4) 125 #define HAS_SUB_COMM_2BITS BIT(5) 126 #define HAS_SUB_COMM_3BITS BIT(6) 127 #define WR_THROT_EN BIT(7) 128 #define HAS_LEGACY_IVRP_PADDR BIT(8) 129 #define IOVA_34_EN BIT(9) 130 #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */ 131 #define DCM_DISABLE BIT(11) 132 #define STD_AXI_MODE BIT(12) /* For non MM iommu */ 133 /* 2 bits: iommu type */ 134 #define MTK_IOMMU_TYPE_MM (0x0 << 13) 135 #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) 136 #define MTK_IOMMU_TYPE_MASK (0x3 << 13) 137 /* PM and clock always on. e.g. infra iommu */ 138 #define PM_CLK_AO BIT(15) 139 #define IFA_IOMMU_PCIE_SUPPORT BIT(16) 140 #define PGTABLE_PA_35_EN BIT(17) 141 #define TF_PORT_TO_ADDR_MT8173 BIT(18) 142 143 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ 144 ((((pdata)->flags) & (mask)) == (_x)) 145 146 #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x) 147 #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\ 148 MTK_IOMMU_TYPE_MASK) 149 150 #define MTK_INVALID_LARBID MTK_LARB_NR_MAX 151 152 #define MTK_LARB_COM_MAX 8 153 #define MTK_LARB_SUBCOM_MAX 8 154 155 #define MTK_IOMMU_GROUP_MAX 8 156 #define MTK_IOMMU_BANK_MAX 5 157 158 enum mtk_iommu_plat { 159 M4U_MT2712, 160 M4U_MT6779, 161 M4U_MT6795, 162 M4U_MT8167, 163 M4U_MT8173, 164 M4U_MT8183, 165 M4U_MT8186, 166 M4U_MT8192, 167 M4U_MT8195, 168 }; 169 170 struct mtk_iommu_iova_region { 171 dma_addr_t iova_base; 172 unsigned long long size; 173 }; 174 175 struct mtk_iommu_suspend_reg { 176 u32 misc_ctrl; 177 u32 dcm_dis; 178 u32 ctrl_reg; 179 u32 vld_pa_rng; 180 u32 wr_len_ctrl; 181 182 u32 int_control[MTK_IOMMU_BANK_MAX]; 183 u32 int_main_control[MTK_IOMMU_BANK_MAX]; 184 u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; 185 }; 186 187 struct mtk_iommu_plat_data { 188 enum mtk_iommu_plat m4u_plat; 189 u32 flags; 190 u32 inv_sel_reg; 191 192 char *pericfg_comp_str; 193 struct list_head *hw_list; 194 unsigned int iova_region_nr; 195 const struct mtk_iommu_iova_region *iova_region; 196 197 u8 banks_num; 198 bool banks_enable[MTK_IOMMU_BANK_MAX]; 199 unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX]; 200 unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; 201 }; 202 203 struct mtk_iommu_bank_data { 204 void __iomem *base; 205 int irq; 206 u8 id; 207 struct device *parent_dev; 208 struct mtk_iommu_data *parent_data; 209 spinlock_t tlb_lock; /* lock for tlb range flush */ 210 struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ 211 }; 212 213 struct mtk_iommu_data { 214 struct device *dev; 215 struct clk *bclk; 216 phys_addr_t protect_base; /* protect memory base */ 217 struct mtk_iommu_suspend_reg reg; 218 struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; 219 bool enable_4GB; 220 221 struct iommu_device iommu; 222 const struct mtk_iommu_plat_data *plat_data; 223 struct device *smicomm_dev; 224 225 struct mtk_iommu_bank_data *bank; 226 227 struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */ 228 struct regmap *pericfg; 229 230 struct mutex mutex; /* Protect m4u_group/m4u_dom above */ 231 232 /* 233 * In the sharing pgtable case, list data->list to the global list like m4ulist. 234 * In the non-sharing pgtable case, list data->list to the itself hw_list_head. 235 */ 236 struct list_head *hw_list; 237 struct list_head hw_list_head; 238 struct list_head list; 239 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 240 }; 241 242 struct mtk_iommu_domain { 243 struct io_pgtable_cfg cfg; 244 struct io_pgtable_ops *iop; 245 246 struct mtk_iommu_bank_data *bank; 247 struct iommu_domain domain; 248 249 struct mutex mutex; /* Protect "data" in this structure */ 250 }; 251 252 static int mtk_iommu_bind(struct device *dev) 253 { 254 struct mtk_iommu_data *data = dev_get_drvdata(dev); 255 256 return component_bind_all(dev, &data->larb_imu); 257 } 258 259 static void mtk_iommu_unbind(struct device *dev) 260 { 261 struct mtk_iommu_data *data = dev_get_drvdata(dev); 262 263 component_unbind_all(dev, &data->larb_imu); 264 } 265 266 static const struct iommu_ops mtk_iommu_ops; 267 268 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid); 269 270 #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 271 dma_addr_t _addr = iova; \ 272 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 273 }) 274 275 /* 276 * In M4U 4GB mode, the physical address is remapped as below: 277 * 278 * CPU Physical address: 279 * ==================== 280 * 281 * 0 1G 2G 3G 4G 5G 282 * |---A---|---B---|---C---|---D---|---E---| 283 * +--I/O--+------------Memory-------------+ 284 * 285 * IOMMU output physical address: 286 * ============================= 287 * 288 * 4G 5G 6G 7G 8G 289 * |---E---|---B---|---C---|---D---| 290 * +------------Memory-------------+ 291 * 292 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 293 * bit32 of the CPU physical address always is needed to set, and for Region 294 * 'E', the CPU physical address keep as is. 295 * Additionally, The iommu consumers always use the CPU phyiscal address. 296 */ 297 #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 298 299 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 300 301 #define for_each_m4u(data, head) list_for_each_entry(data, head, list) 302 303 static const struct mtk_iommu_iova_region single_domain[] = { 304 {.iova_base = 0, .size = SZ_4G}, 305 }; 306 307 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { 308 { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */ 309 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 310 { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */ 311 { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */ 312 { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */ 313 314 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 315 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 316 #endif 317 }; 318 319 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/ 320 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist) 321 { 322 return list_first_entry(hwlist, struct mtk_iommu_data, list); 323 } 324 325 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 326 { 327 return container_of(dom, struct mtk_iommu_domain, domain); 328 } 329 330 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 331 { 332 /* Tlb flush all always is in bank0. */ 333 struct mtk_iommu_bank_data *bank = &data->bank[0]; 334 void __iomem *base = bank->base; 335 unsigned long flags; 336 337 spin_lock_irqsave(&bank->tlb_lock, flags); 338 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); 339 writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); 340 wmb(); /* Make sure the tlb flush all done */ 341 spin_unlock_irqrestore(&bank->tlb_lock, flags); 342 } 343 344 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 345 struct mtk_iommu_bank_data *bank) 346 { 347 struct list_head *head = bank->parent_data->hw_list; 348 struct mtk_iommu_bank_data *curbank; 349 struct mtk_iommu_data *data; 350 bool check_pm_status; 351 unsigned long flags; 352 void __iomem *base; 353 int ret; 354 u32 tmp; 355 356 for_each_m4u(data, head) { 357 /* 358 * To avoid resume the iommu device frequently when the iommu device 359 * is not active, it doesn't always call pm_runtime_get here, then tlb 360 * flush depends on the tlb flush all in the runtime resume. 361 * 362 * There are 2 special cases: 363 * 364 * Case1: The iommu dev doesn't have power domain but has bclk. This case 365 * should also avoid the tlb flush while the dev is not active to mute 366 * the tlb timeout log. like mt8173. 367 * 368 * Case2: The power/clock of infra iommu is always on, and it doesn't 369 * have the device link with the master devices. This case should avoid 370 * the PM status check. 371 */ 372 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); 373 374 if (check_pm_status) { 375 if (pm_runtime_get_if_in_use(data->dev) <= 0) 376 continue; 377 } 378 379 curbank = &data->bank[bank->id]; 380 base = curbank->base; 381 382 spin_lock_irqsave(&curbank->tlb_lock, flags); 383 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 384 base + data->plat_data->inv_sel_reg); 385 386 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); 387 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 388 base + REG_MMU_INVLD_END_A); 389 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); 390 391 /* tlb sync */ 392 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, 393 tmp, tmp != 0, 10, 1000); 394 395 /* Clear the CPE status */ 396 writel_relaxed(0, base + REG_MMU_CPE_DONE); 397 spin_unlock_irqrestore(&curbank->tlb_lock, flags); 398 399 if (ret) { 400 dev_warn(data->dev, 401 "Partial TLB flush timed out, falling back to full flush\n"); 402 mtk_iommu_tlb_flush_all(data); 403 } 404 405 if (check_pm_status) 406 pm_runtime_put(data->dev); 407 } 408 } 409 410 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 411 { 412 struct mtk_iommu_bank_data *bank = dev_id; 413 struct mtk_iommu_data *data = bank->parent_data; 414 struct mtk_iommu_domain *dom = bank->m4u_dom; 415 unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; 416 u32 int_state, regval, va34_32, pa34_32; 417 const struct mtk_iommu_plat_data *plat_data = data->plat_data; 418 void __iomem *base = bank->base; 419 u64 fault_iova, fault_pa; 420 bool layer, write; 421 422 /* Read error info from registers */ 423 int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); 424 if (int_state & F_REG_MMU0_FAULT_MASK) { 425 regval = readl_relaxed(base + REG_MMU0_INT_ID); 426 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); 427 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); 428 } else { 429 regval = readl_relaxed(base + REG_MMU1_INT_ID); 430 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); 431 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); 432 } 433 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 434 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 435 if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { 436 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 437 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 438 fault_iova |= (u64)va34_32 << 32; 439 } 440 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 441 fault_pa |= (u64)pa34_32 << 32; 442 443 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { 444 fault_port = F_MMU_INT_ID_PORT_ID(regval); 445 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { 446 fault_larb = F_MMU_INT_ID_COMM_ID(regval); 447 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 448 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { 449 fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); 450 sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); 451 } else { 452 fault_larb = F_MMU_INT_ID_LARB_ID(regval); 453 } 454 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 455 } 456 457 if (report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, 458 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 459 dev_err_ratelimited( 460 bank->parent_dev, 461 "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", 462 int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, 463 layer, write ? "write" : "read"); 464 } 465 466 /* Interrupt clear */ 467 regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); 468 regval |= F_INT_CLR_BIT; 469 writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); 470 471 mtk_iommu_tlb_flush_all(data); 472 473 return IRQ_HANDLED; 474 } 475 476 static unsigned int mtk_iommu_get_bank_id(struct device *dev, 477 const struct mtk_iommu_plat_data *plat_data) 478 { 479 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 480 unsigned int i, portmsk = 0, bankid = 0; 481 482 if (plat_data->banks_num == 1) 483 return bankid; 484 485 for (i = 0; i < fwspec->num_ids; i++) 486 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 487 488 for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { 489 if (!plat_data->banks_enable[i]) 490 continue; 491 492 if (portmsk & plat_data->banks_portmsk[i]) { 493 bankid = i; 494 break; 495 } 496 } 497 return bankid; /* default is 0 */ 498 } 499 500 static int mtk_iommu_get_iova_region_id(struct device *dev, 501 const struct mtk_iommu_plat_data *plat_data) 502 { 503 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; 504 const struct bus_dma_region *dma_rgn = dev->dma_range_map; 505 int i, candidate = -1; 506 dma_addr_t dma_end; 507 508 if (!dma_rgn || plat_data->iova_region_nr == 1) 509 return 0; 510 511 dma_end = dma_rgn->dma_start + dma_rgn->size - 1; 512 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { 513 /* Best fit. */ 514 if (dma_rgn->dma_start == rgn->iova_base && 515 dma_end == rgn->iova_base + rgn->size - 1) 516 return i; 517 /* ok if it is inside this region. */ 518 if (dma_rgn->dma_start >= rgn->iova_base && 519 dma_end < rgn->iova_base + rgn->size) 520 candidate = i; 521 } 522 523 if (candidate >= 0) 524 return candidate; 525 dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n", 526 &dma_rgn->dma_start, dma_rgn->size); 527 return -EINVAL; 528 } 529 530 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 531 bool enable, unsigned int regionid) 532 { 533 struct mtk_smi_larb_iommu *larb_mmu; 534 unsigned int larbid, portid; 535 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 536 const struct mtk_iommu_iova_region *region; 537 u32 peri_mmuen, peri_mmuen_msk; 538 int i, ret = 0; 539 540 for (i = 0; i < fwspec->num_ids; ++i) { 541 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 542 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 543 544 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 545 larb_mmu = &data->larb_imu[larbid]; 546 547 region = data->plat_data->iova_region + regionid; 548 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 549 550 dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n", 551 enable ? "enable" : "disable", dev_name(larb_mmu->dev), 552 portid, regionid, larb_mmu->bank[portid]); 553 554 if (enable) 555 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 556 else 557 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 558 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 559 peri_mmuen_msk = BIT(portid); 560 /* PCI dev has only one output id, enable the next writing bit for PCIe */ 561 if (dev_is_pci(dev)) 562 peri_mmuen_msk |= BIT(portid + 1); 563 564 peri_mmuen = enable ? peri_mmuen_msk : 0; 565 ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, 566 peri_mmuen_msk, peri_mmuen); 567 if (ret) 568 dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n", 569 enable ? "enable" : "disable", 570 dev_name(data->dev), peri_mmuen_msk, ret); 571 } 572 } 573 return ret; 574 } 575 576 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 577 struct mtk_iommu_data *data, 578 unsigned int region_id) 579 { 580 const struct mtk_iommu_iova_region *region; 581 struct mtk_iommu_domain *m4u_dom; 582 583 /* Always use bank0 in sharing pgtable case */ 584 m4u_dom = data->bank[0].m4u_dom; 585 if (m4u_dom) { 586 dom->iop = m4u_dom->iop; 587 dom->cfg = m4u_dom->cfg; 588 dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap; 589 goto update_iova_region; 590 } 591 592 dom->cfg = (struct io_pgtable_cfg) { 593 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 594 IO_PGTABLE_QUIRK_NO_PERMS | 595 IO_PGTABLE_QUIRK_ARM_MTK_EXT, 596 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 597 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 598 .iommu_dev = data->dev, 599 }; 600 601 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) 602 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; 603 604 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 605 dom->cfg.oas = data->enable_4GB ? 33 : 32; 606 else 607 dom->cfg.oas = 35; 608 609 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 610 if (!dom->iop) { 611 dev_err(data->dev, "Failed to alloc io pgtable\n"); 612 return -EINVAL; 613 } 614 615 /* Update our support page sizes bitmap */ 616 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 617 618 update_iova_region: 619 /* Update the iova region for this domain */ 620 region = data->plat_data->iova_region + region_id; 621 dom->domain.geometry.aperture_start = region->iova_base; 622 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 623 dom->domain.geometry.force_aperture = true; 624 return 0; 625 } 626 627 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 628 { 629 struct mtk_iommu_domain *dom; 630 631 if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED) 632 return NULL; 633 634 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 635 if (!dom) 636 return NULL; 637 mutex_init(&dom->mutex); 638 639 return &dom->domain; 640 } 641 642 static void mtk_iommu_domain_free(struct iommu_domain *domain) 643 { 644 kfree(to_mtk_domain(domain)); 645 } 646 647 static int mtk_iommu_attach_device(struct iommu_domain *domain, 648 struct device *dev) 649 { 650 struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; 651 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 652 struct list_head *hw_list = data->hw_list; 653 struct device *m4udev = data->dev; 654 struct mtk_iommu_bank_data *bank; 655 unsigned int bankid; 656 int ret, region_id; 657 658 region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); 659 if (region_id < 0) 660 return region_id; 661 662 bankid = mtk_iommu_get_bank_id(dev, data->plat_data); 663 mutex_lock(&dom->mutex); 664 if (!dom->bank) { 665 /* Data is in the frstdata in sharing pgtable case. */ 666 frstdata = mtk_iommu_get_frst_data(hw_list); 667 668 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id); 669 if (ret) { 670 mutex_unlock(&dom->mutex); 671 return -ENODEV; 672 } 673 dom->bank = &data->bank[bankid]; 674 } 675 mutex_unlock(&dom->mutex); 676 677 mutex_lock(&data->mutex); 678 bank = &data->bank[bankid]; 679 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ 680 ret = pm_runtime_resume_and_get(m4udev); 681 if (ret < 0) { 682 dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); 683 goto err_unlock; 684 } 685 686 ret = mtk_iommu_hw_init(data, bankid); 687 if (ret) { 688 pm_runtime_put(m4udev); 689 goto err_unlock; 690 } 691 bank->m4u_dom = dom; 692 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); 693 694 pm_runtime_put(m4udev); 695 } 696 mutex_unlock(&data->mutex); 697 698 return mtk_iommu_config(data, dev, true, region_id); 699 700 err_unlock: 701 mutex_unlock(&data->mutex); 702 return ret; 703 } 704 705 static void mtk_iommu_detach_device(struct iommu_domain *domain, 706 struct device *dev) 707 { 708 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 709 710 mtk_iommu_config(data, dev, false, 0); 711 } 712 713 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 714 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 715 { 716 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 717 718 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 719 if (dom->bank->parent_data->enable_4GB) 720 paddr |= BIT_ULL(32); 721 722 /* Synchronize with the tlb_lock */ 723 return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); 724 } 725 726 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 727 unsigned long iova, size_t size, 728 struct iommu_iotlb_gather *gather) 729 { 730 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 731 732 iommu_iotlb_gather_add_range(gather, iova, size); 733 return dom->iop->unmap(dom->iop, iova, size, gather); 734 } 735 736 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 737 { 738 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 739 740 mtk_iommu_tlb_flush_all(dom->bank->parent_data); 741 } 742 743 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 744 struct iommu_iotlb_gather *gather) 745 { 746 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 747 size_t length = gather->end - gather->start + 1; 748 749 mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); 750 } 751 752 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 753 size_t size) 754 { 755 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 756 757 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); 758 } 759 760 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 761 dma_addr_t iova) 762 { 763 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 764 phys_addr_t pa; 765 766 pa = dom->iop->iova_to_phys(dom->iop, iova); 767 if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 768 dom->bank->parent_data->enable_4GB && 769 pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 770 pa &= ~BIT_ULL(32); 771 772 return pa; 773 } 774 775 static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 776 { 777 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 778 struct mtk_iommu_data *data; 779 struct device_link *link; 780 struct device *larbdev; 781 unsigned int larbid, larbidx, i; 782 783 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 784 return ERR_PTR(-ENODEV); /* Not a iommu client device */ 785 786 data = dev_iommu_priv_get(dev); 787 788 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 789 return &data->iommu; 790 791 /* 792 * Link the consumer device with the smi-larb device(supplier). 793 * The device that connects with each a larb is a independent HW. 794 * All the ports in each a device should be in the same larbs. 795 */ 796 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 797 if (larbid >= MTK_LARB_NR_MAX) 798 return ERR_PTR(-EINVAL); 799 800 for (i = 1; i < fwspec->num_ids; i++) { 801 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); 802 if (larbid != larbidx) { 803 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 804 larbid, larbidx); 805 return ERR_PTR(-EINVAL); 806 } 807 } 808 larbdev = data->larb_imu[larbid].dev; 809 if (!larbdev) 810 return ERR_PTR(-EINVAL); 811 812 link = device_link_add(dev, larbdev, 813 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 814 if (!link) 815 dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 816 return &data->iommu; 817 } 818 819 static void mtk_iommu_release_device(struct device *dev) 820 { 821 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 822 struct mtk_iommu_data *data; 823 struct device *larbdev; 824 unsigned int larbid; 825 826 data = dev_iommu_priv_get(dev); 827 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 828 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 829 larbdev = data->larb_imu[larbid].dev; 830 device_link_remove(dev, larbdev); 831 } 832 } 833 834 static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) 835 { 836 unsigned int bankid; 837 838 /* 839 * If the bank function is enabled, each bank is a iommu group/domain. 840 * Otherwise, each iova region is a iommu group/domain. 841 */ 842 bankid = mtk_iommu_get_bank_id(dev, plat_data); 843 if (bankid) 844 return bankid; 845 846 return mtk_iommu_get_iova_region_id(dev, plat_data); 847 } 848 849 static struct iommu_group *mtk_iommu_device_group(struct device *dev) 850 { 851 struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; 852 struct list_head *hw_list = c_data->hw_list; 853 struct iommu_group *group; 854 int groupid; 855 856 data = mtk_iommu_get_frst_data(hw_list); 857 if (!data) 858 return ERR_PTR(-ENODEV); 859 860 groupid = mtk_iommu_get_group_id(dev, data->plat_data); 861 if (groupid < 0) 862 return ERR_PTR(groupid); 863 864 mutex_lock(&data->mutex); 865 group = data->m4u_group[groupid]; 866 if (!group) { 867 group = iommu_group_alloc(); 868 if (!IS_ERR(group)) 869 data->m4u_group[groupid] = group; 870 } else { 871 iommu_group_ref_get(group); 872 } 873 mutex_unlock(&data->mutex); 874 return group; 875 } 876 877 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 878 { 879 struct platform_device *m4updev; 880 881 if (args->args_count != 1) { 882 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 883 args->args_count); 884 return -EINVAL; 885 } 886 887 if (!dev_iommu_priv_get(dev)) { 888 /* Get the m4u device */ 889 m4updev = of_find_device_by_node(args->np); 890 if (WARN_ON(!m4updev)) 891 return -EINVAL; 892 893 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 894 } 895 896 return iommu_fwspec_add_ids(dev, args->args, 1); 897 } 898 899 static void mtk_iommu_get_resv_regions(struct device *dev, 900 struct list_head *head) 901 { 902 struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 903 unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; 904 const struct mtk_iommu_iova_region *resv, *curdom; 905 struct iommu_resv_region *region; 906 int prot = IOMMU_WRITE | IOMMU_READ; 907 908 if ((int)regionid < 0) 909 return; 910 curdom = data->plat_data->iova_region + regionid; 911 for (i = 0; i < data->plat_data->iova_region_nr; i++) { 912 resv = data->plat_data->iova_region + i; 913 914 /* Only reserve when the region is inside the current domain */ 915 if (resv->iova_base <= curdom->iova_base || 916 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 917 continue; 918 919 region = iommu_alloc_resv_region(resv->iova_base, resv->size, 920 prot, IOMMU_RESV_RESERVED, 921 GFP_KERNEL); 922 if (!region) 923 return; 924 925 list_add_tail(®ion->list, head); 926 } 927 } 928 929 static const struct iommu_ops mtk_iommu_ops = { 930 .domain_alloc = mtk_iommu_domain_alloc, 931 .probe_device = mtk_iommu_probe_device, 932 .release_device = mtk_iommu_release_device, 933 .device_group = mtk_iommu_device_group, 934 .of_xlate = mtk_iommu_of_xlate, 935 .get_resv_regions = mtk_iommu_get_resv_regions, 936 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 937 .owner = THIS_MODULE, 938 .default_domain_ops = &(const struct iommu_domain_ops) { 939 .attach_dev = mtk_iommu_attach_device, 940 .detach_dev = mtk_iommu_detach_device, 941 .map = mtk_iommu_map, 942 .unmap = mtk_iommu_unmap, 943 .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 944 .iotlb_sync = mtk_iommu_iotlb_sync, 945 .iotlb_sync_map = mtk_iommu_sync_map, 946 .iova_to_phys = mtk_iommu_iova_to_phys, 947 .free = mtk_iommu_domain_free, 948 } 949 }; 950 951 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid) 952 { 953 const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; 954 const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; 955 u32 regval; 956 957 /* 958 * Global control settings are in bank0. May re-init these global registers 959 * since no sure if there is bank0 consumers. 960 */ 961 if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { 962 regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 963 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 964 } else { 965 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); 966 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 967 } 968 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); 969 970 if (data->enable_4GB && 971 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 972 /* 973 * If 4GB mode is enabled, the validate PA range is from 974 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 975 */ 976 regval = F_MMU_VLD_PA_RNG(7, 4); 977 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); 978 } 979 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) 980 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); 981 else 982 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); 983 984 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 985 /* write command throttling mode */ 986 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); 987 regval &= ~F_MMU_WR_THROT_DIS_MASK; 988 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); 989 } 990 991 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 992 /* The register is called STANDARD_AXI_MODE in this case */ 993 regval = 0; 994 } else { 995 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); 996 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) 997 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 998 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 999 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 1000 } 1001 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); 1002 1003 /* Independent settings for each bank */ 1004 regval = F_L2_MULIT_HIT_EN | 1005 F_TABLE_WALK_FAULT_INT_EN | 1006 F_PREETCH_FIFO_OVERFLOW_INT_EN | 1007 F_MISS_FIFO_OVERFLOW_INT_EN | 1008 F_PREFETCH_FIFO_ERR_INT_EN | 1009 F_MISS_FIFO_ERR_INT_EN; 1010 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); 1011 1012 regval = F_INT_TRANSLATION_FAULT | 1013 F_INT_MAIN_MULTI_HIT_FAULT | 1014 F_INT_INVALID_PA_FAULT | 1015 F_INT_ENTRY_REPLACEMENT_FAULT | 1016 F_INT_TLB_MISS_FAULT | 1017 F_INT_MISS_TRANSACTION_FIFO_FAULT | 1018 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 1019 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); 1020 1021 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 1022 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 1023 else 1024 regval = lower_32_bits(data->protect_base) | 1025 upper_32_bits(data->protect_base); 1026 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); 1027 1028 if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, 1029 dev_name(bankx->parent_dev), (void *)bankx)) { 1030 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); 1031 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); 1032 return -ENODEV; 1033 } 1034 1035 return 0; 1036 } 1037 1038 static const struct component_master_ops mtk_iommu_com_ops = { 1039 .bind = mtk_iommu_bind, 1040 .unbind = mtk_iommu_unbind, 1041 }; 1042 1043 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match, 1044 struct mtk_iommu_data *data) 1045 { 1046 struct device_node *larbnode, *smicomm_node, *smi_subcomm_node; 1047 struct platform_device *plarbdev; 1048 struct device_link *link; 1049 int i, larb_nr, ret; 1050 1051 larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); 1052 if (larb_nr < 0) 1053 return larb_nr; 1054 1055 for (i = 0; i < larb_nr; i++) { 1056 u32 id; 1057 1058 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 1059 if (!larbnode) 1060 return -EINVAL; 1061 1062 if (!of_device_is_available(larbnode)) { 1063 of_node_put(larbnode); 1064 continue; 1065 } 1066 1067 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 1068 if (ret)/* The id is consecutive if there is no this property */ 1069 id = i; 1070 1071 plarbdev = of_find_device_by_node(larbnode); 1072 if (!plarbdev) { 1073 of_node_put(larbnode); 1074 return -ENODEV; 1075 } 1076 if (!plarbdev->dev.driver) { 1077 of_node_put(larbnode); 1078 return -EPROBE_DEFER; 1079 } 1080 data->larb_imu[id].dev = &plarbdev->dev; 1081 1082 component_match_add_release(dev, match, component_release_of, 1083 component_compare_of, larbnode); 1084 } 1085 1086 /* Get smi-(sub)-common dev from the last larb. */ 1087 smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 1088 if (!smi_subcomm_node) 1089 return -EINVAL; 1090 1091 /* 1092 * It may have two level smi-common. the node is smi-sub-common if it 1093 * has a new mediatek,smi property. otherwise it is smi-commmon. 1094 */ 1095 smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0); 1096 if (smicomm_node) 1097 of_node_put(smi_subcomm_node); 1098 else 1099 smicomm_node = smi_subcomm_node; 1100 1101 plarbdev = of_find_device_by_node(smicomm_node); 1102 of_node_put(smicomm_node); 1103 data->smicomm_dev = &plarbdev->dev; 1104 1105 link = device_link_add(data->smicomm_dev, dev, 1106 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1107 if (!link) { 1108 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 1109 return -EINVAL; 1110 } 1111 return 0; 1112 } 1113 1114 static int mtk_iommu_probe(struct platform_device *pdev) 1115 { 1116 struct mtk_iommu_data *data; 1117 struct device *dev = &pdev->dev; 1118 struct resource *res; 1119 resource_size_t ioaddr; 1120 struct component_match *match = NULL; 1121 struct regmap *infracfg; 1122 void *protect; 1123 int ret, banks_num, i = 0; 1124 u32 val; 1125 char *p; 1126 struct mtk_iommu_bank_data *bank; 1127 void __iomem *base; 1128 1129 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 1130 if (!data) 1131 return -ENOMEM; 1132 data->dev = dev; 1133 data->plat_data = of_device_get_match_data(dev); 1134 1135 /* Protect memory. HW will access here while translation fault.*/ 1136 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 1137 if (!protect) 1138 return -ENOMEM; 1139 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 1140 1141 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 1142 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg"); 1143 if (IS_ERR(infracfg)) { 1144 /* 1145 * Legacy devicetrees will not specify a phandle to 1146 * mediatek,infracfg: in that case, we use the older 1147 * way to retrieve a syscon to infra. 1148 * 1149 * This is for retrocompatibility purposes only, hence 1150 * no more compatibles shall be added to this. 1151 */ 1152 switch (data->plat_data->m4u_plat) { 1153 case M4U_MT2712: 1154 p = "mediatek,mt2712-infracfg"; 1155 break; 1156 case M4U_MT8173: 1157 p = "mediatek,mt8173-infracfg"; 1158 break; 1159 default: 1160 p = NULL; 1161 } 1162 1163 infracfg = syscon_regmap_lookup_by_compatible(p); 1164 if (IS_ERR(infracfg)) 1165 return PTR_ERR(infracfg); 1166 } 1167 1168 ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 1169 if (ret) 1170 return ret; 1171 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 1172 } 1173 1174 banks_num = data->plat_data->banks_num; 1175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1176 if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) { 1177 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res); 1178 return -EINVAL; 1179 } 1180 base = devm_ioremap_resource(dev, res); 1181 if (IS_ERR(base)) 1182 return PTR_ERR(base); 1183 ioaddr = res->start; 1184 1185 data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); 1186 if (!data->bank) 1187 return -ENOMEM; 1188 1189 do { 1190 if (!data->plat_data->banks_enable[i]) 1191 continue; 1192 bank = &data->bank[i]; 1193 bank->id = i; 1194 bank->base = base + i * MTK_IOMMU_BANK_SZ; 1195 bank->m4u_dom = NULL; 1196 1197 bank->irq = platform_get_irq(pdev, i); 1198 if (bank->irq < 0) 1199 return bank->irq; 1200 bank->parent_dev = dev; 1201 bank->parent_data = data; 1202 spin_lock_init(&bank->tlb_lock); 1203 } while (++i < banks_num); 1204 1205 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 1206 data->bclk = devm_clk_get(dev, "bclk"); 1207 if (IS_ERR(data->bclk)) 1208 return PTR_ERR(data->bclk); 1209 } 1210 1211 pm_runtime_enable(dev); 1212 1213 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1214 ret = mtk_iommu_mm_dts_parse(dev, &match, data); 1215 if (ret) { 1216 dev_err_probe(dev, ret, "mm dts parse fail\n"); 1217 goto out_runtime_disable; 1218 } 1219 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 1220 p = data->plat_data->pericfg_comp_str; 1221 data->pericfg = syscon_regmap_lookup_by_compatible(p); 1222 if (IS_ERR(data->pericfg)) { 1223 ret = PTR_ERR(data->pericfg); 1224 goto out_runtime_disable; 1225 } 1226 } 1227 1228 platform_set_drvdata(pdev, data); 1229 mutex_init(&data->mutex); 1230 1231 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 1232 "mtk-iommu.%pa", &ioaddr); 1233 if (ret) 1234 goto out_link_remove; 1235 1236 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 1237 if (ret) 1238 goto out_sysfs_remove; 1239 1240 if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { 1241 list_add_tail(&data->list, data->plat_data->hw_list); 1242 data->hw_list = data->plat_data->hw_list; 1243 } else { 1244 INIT_LIST_HEAD(&data->hw_list_head); 1245 list_add_tail(&data->list, &data->hw_list_head); 1246 data->hw_list = &data->hw_list_head; 1247 } 1248 1249 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1250 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 1251 if (ret) 1252 goto out_list_del; 1253 } 1254 return ret; 1255 1256 out_list_del: 1257 list_del(&data->list); 1258 iommu_device_unregister(&data->iommu); 1259 out_sysfs_remove: 1260 iommu_device_sysfs_remove(&data->iommu); 1261 out_link_remove: 1262 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 1263 device_link_remove(data->smicomm_dev, dev); 1264 out_runtime_disable: 1265 pm_runtime_disable(dev); 1266 return ret; 1267 } 1268 1269 static int mtk_iommu_remove(struct platform_device *pdev) 1270 { 1271 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 1272 struct mtk_iommu_bank_data *bank; 1273 int i; 1274 1275 iommu_device_sysfs_remove(&data->iommu); 1276 iommu_device_unregister(&data->iommu); 1277 1278 list_del(&data->list); 1279 1280 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1281 device_link_remove(data->smicomm_dev, &pdev->dev); 1282 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 1283 } 1284 pm_runtime_disable(&pdev->dev); 1285 for (i = 0; i < data->plat_data->banks_num; i++) { 1286 bank = &data->bank[i]; 1287 if (!bank->m4u_dom) 1288 continue; 1289 devm_free_irq(&pdev->dev, bank->irq, bank); 1290 } 1291 return 0; 1292 } 1293 1294 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 1295 { 1296 struct mtk_iommu_data *data = dev_get_drvdata(dev); 1297 struct mtk_iommu_suspend_reg *reg = &data->reg; 1298 void __iomem *base; 1299 int i = 0; 1300 1301 base = data->bank[i].base; 1302 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 1303 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 1304 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 1305 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 1306 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 1307 do { 1308 if (!data->plat_data->banks_enable[i]) 1309 continue; 1310 base = data->bank[i].base; 1311 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); 1312 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 1313 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); 1314 } while (++i < data->plat_data->banks_num); 1315 clk_disable_unprepare(data->bclk); 1316 return 0; 1317 } 1318 1319 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 1320 { 1321 struct mtk_iommu_data *data = dev_get_drvdata(dev); 1322 struct mtk_iommu_suspend_reg *reg = &data->reg; 1323 struct mtk_iommu_domain *m4u_dom; 1324 void __iomem *base; 1325 int ret, i = 0; 1326 1327 ret = clk_prepare_enable(data->bclk); 1328 if (ret) { 1329 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 1330 return ret; 1331 } 1332 1333 /* 1334 * Uppon first resume, only enable the clk and return, since the values of the 1335 * registers are not yet set. 1336 */ 1337 if (!reg->wr_len_ctrl) 1338 return 0; 1339 1340 base = data->bank[i].base; 1341 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 1342 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 1343 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 1344 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 1345 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 1346 do { 1347 m4u_dom = data->bank[i].m4u_dom; 1348 if (!data->plat_data->banks_enable[i] || !m4u_dom) 1349 continue; 1350 base = data->bank[i].base; 1351 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); 1352 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); 1353 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); 1354 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); 1355 } while (++i < data->plat_data->banks_num); 1356 1357 /* 1358 * Users may allocate dma buffer before they call pm_runtime_get, 1359 * in which case it will lack the necessary tlb flush. 1360 * Thus, make sure to update the tlb after each PM resume. 1361 */ 1362 mtk_iommu_tlb_flush_all(data); 1363 return 0; 1364 } 1365 1366 static const struct dev_pm_ops mtk_iommu_pm_ops = { 1367 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 1368 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1369 pm_runtime_force_resume) 1370 }; 1371 1372 static const struct mtk_iommu_plat_data mt2712_data = { 1373 .m4u_plat = M4U_MT2712, 1374 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE | 1375 MTK_IOMMU_TYPE_MM, 1376 .hw_list = &m4ulist, 1377 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1378 .iova_region = single_domain, 1379 .banks_num = 1, 1380 .banks_enable = {true}, 1381 .iova_region_nr = ARRAY_SIZE(single_domain), 1382 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1383 }; 1384 1385 static const struct mtk_iommu_plat_data mt6779_data = { 1386 .m4u_plat = M4U_MT6779, 1387 .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | 1388 MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN, 1389 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1390 .banks_num = 1, 1391 .banks_enable = {true}, 1392 .iova_region = single_domain, 1393 .iova_region_nr = ARRAY_SIZE(single_domain), 1394 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1395 }; 1396 1397 static const struct mtk_iommu_plat_data mt6795_data = { 1398 .m4u_plat = M4U_MT6795, 1399 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1400 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 1401 TF_PORT_TO_ADDR_MT8173, 1402 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1403 .banks_num = 1, 1404 .banks_enable = {true}, 1405 .iova_region = single_domain, 1406 .iova_region_nr = ARRAY_SIZE(single_domain), 1407 .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ 1408 }; 1409 1410 static const struct mtk_iommu_plat_data mt8167_data = { 1411 .m4u_plat = M4U_MT8167, 1412 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 1413 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1414 .banks_num = 1, 1415 .banks_enable = {true}, 1416 .iova_region = single_domain, 1417 .iova_region_nr = ARRAY_SIZE(single_domain), 1418 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 1419 }; 1420 1421 static const struct mtk_iommu_plat_data mt8173_data = { 1422 .m4u_plat = M4U_MT8173, 1423 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1424 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 1425 TF_PORT_TO_ADDR_MT8173, 1426 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1427 .banks_num = 1, 1428 .banks_enable = {true}, 1429 .iova_region = single_domain, 1430 .iova_region_nr = ARRAY_SIZE(single_domain), 1431 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1432 }; 1433 1434 static const struct mtk_iommu_plat_data mt8183_data = { 1435 .m4u_plat = M4U_MT8183, 1436 .flags = RESET_AXI | MTK_IOMMU_TYPE_MM, 1437 .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1438 .banks_num = 1, 1439 .banks_enable = {true}, 1440 .iova_region = single_domain, 1441 .iova_region_nr = ARRAY_SIZE(single_domain), 1442 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1443 }; 1444 1445 static const struct mtk_iommu_plat_data mt8186_data_mm = { 1446 .m4u_plat = M4U_MT8186, 1447 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1448 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 1449 .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20}, 1450 {MTK_INVALID_LARBID, 14, 16}, 1451 {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}}, 1452 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1453 .banks_num = 1, 1454 .banks_enable = {true}, 1455 .iova_region = mt8192_multi_dom, 1456 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1457 }; 1458 1459 static const struct mtk_iommu_plat_data mt8192_data = { 1460 .m4u_plat = M4U_MT8192, 1461 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1462 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 1463 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1464 .banks_num = 1, 1465 .banks_enable = {true}, 1466 .iova_region = mt8192_multi_dom, 1467 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1468 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 1469 {0, 14, 16}, {0, 13, 18, 17}}, 1470 }; 1471 1472 static const struct mtk_iommu_plat_data mt8195_data_infra = { 1473 .m4u_plat = M4U_MT8195, 1474 .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1475 MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, 1476 .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", 1477 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1478 .banks_num = 5, 1479 .banks_enable = {true, false, false, false, true}, 1480 .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */ 1481 [4] = GENMASK(31, 20), /* USB */ 1482 }, 1483 .iova_region = single_domain, 1484 .iova_region_nr = ARRAY_SIZE(single_domain), 1485 }; 1486 1487 static const struct mtk_iommu_plat_data mt8195_data_vdo = { 1488 .m4u_plat = M4U_MT8195, 1489 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1490 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1491 .hw_list = &m4ulist, 1492 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1493 .banks_num = 1, 1494 .banks_enable = {true}, 1495 .iova_region = mt8192_multi_dom, 1496 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1497 .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, 1498 {13, 17, 15/* 17b */, 25}, {5}}, 1499 }; 1500 1501 static const struct mtk_iommu_plat_data mt8195_data_vpp = { 1502 .m4u_plat = M4U_MT8195, 1503 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1504 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1505 .hw_list = &m4ulist, 1506 .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1507 .banks_num = 1, 1508 .banks_enable = {true}, 1509 .iova_region = mt8192_multi_dom, 1510 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1511 .larbid_remap = {{1}, {3}, 1512 {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, 1513 {8}, {20}, {12}, 1514 /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ 1515 {14, 16, 29, 26, 30, 31, 18}, 1516 {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, 1517 }; 1518 1519 static const struct of_device_id mtk_iommu_of_ids[] = { 1520 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1521 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 1522 { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, 1523 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1524 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1525 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 1526 { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */ 1527 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1528 { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, 1529 { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, 1530 { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, 1531 {} 1532 }; 1533 1534 static struct platform_driver mtk_iommu_driver = { 1535 .probe = mtk_iommu_probe, 1536 .remove = mtk_iommu_remove, 1537 .driver = { 1538 .name = "mtk-iommu", 1539 .of_match_table = mtk_iommu_of_ids, 1540 .pm = &mtk_iommu_pm_ops, 1541 } 1542 }; 1543 module_platform_driver(mtk_iommu_driver); 1544 1545 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 1546 MODULE_LICENSE("GPL v2"); 1547