1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. 3 * 4 * Author: Stepan Moskovchenko <stepanm@codeaurora.org> 5 */ 6 7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/platform_device.h> 11 #include <linux/errno.h> 12 #include <linux/io.h> 13 #include <linux/io-pgtable.h> 14 #include <linux/interrupt.h> 15 #include <linux/list.h> 16 #include <linux/spinlock.h> 17 #include <linux/slab.h> 18 #include <linux/iommu.h> 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/of_iommu.h> 22 23 #include <asm/cacheflush.h> 24 #include <linux/sizes.h> 25 26 #include "msm_iommu_hw-8xxx.h" 27 #include "msm_iommu.h" 28 29 #define MRC(reg, processor, op1, crn, crm, op2) \ 30 __asm__ __volatile__ ( \ 31 " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \ 32 : "=r" (reg)) 33 34 /* bitmap of the page sizes currently supported */ 35 #define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) 36 37 static DEFINE_SPINLOCK(msm_iommu_lock); 38 static LIST_HEAD(qcom_iommu_devices); 39 static struct iommu_ops msm_iommu_ops; 40 41 struct msm_priv { 42 struct list_head list_attached; 43 struct iommu_domain domain; 44 struct io_pgtable_cfg cfg; 45 struct io_pgtable_ops *iop; 46 struct device *dev; 47 spinlock_t pgtlock; /* pagetable lock */ 48 }; 49 50 static struct msm_priv *to_msm_priv(struct iommu_domain *dom) 51 { 52 return container_of(dom, struct msm_priv, domain); 53 } 54 55 static int __enable_clocks(struct msm_iommu_dev *iommu) 56 { 57 int ret; 58 59 ret = clk_enable(iommu->pclk); 60 if (ret) 61 goto fail; 62 63 if (iommu->clk) { 64 ret = clk_enable(iommu->clk); 65 if (ret) 66 clk_disable(iommu->pclk); 67 } 68 fail: 69 return ret; 70 } 71 72 static void __disable_clocks(struct msm_iommu_dev *iommu) 73 { 74 if (iommu->clk) 75 clk_disable(iommu->clk); 76 clk_disable(iommu->pclk); 77 } 78 79 static void msm_iommu_reset(void __iomem *base, int ncb) 80 { 81 int ctx; 82 83 SET_RPUE(base, 0); 84 SET_RPUEIE(base, 0); 85 SET_ESRRESTORE(base, 0); 86 SET_TBE(base, 0); 87 SET_CR(base, 0); 88 SET_SPDMBE(base, 0); 89 SET_TESTBUSCR(base, 0); 90 SET_TLBRSW(base, 0); 91 SET_GLOBAL_TLBIALL(base, 0); 92 SET_RPU_ACR(base, 0); 93 SET_TLBLKCRWE(base, 1); 94 95 for (ctx = 0; ctx < ncb; ctx++) { 96 SET_BPRCOSH(base, ctx, 0); 97 SET_BPRCISH(base, ctx, 0); 98 SET_BPRCNSH(base, ctx, 0); 99 SET_BPSHCFG(base, ctx, 0); 100 SET_BPMTCFG(base, ctx, 0); 101 SET_ACTLR(base, ctx, 0); 102 SET_SCTLR(base, ctx, 0); 103 SET_FSRRESTORE(base, ctx, 0); 104 SET_TTBR0(base, ctx, 0); 105 SET_TTBR1(base, ctx, 0); 106 SET_TTBCR(base, ctx, 0); 107 SET_BFBCR(base, ctx, 0); 108 SET_PAR(base, ctx, 0); 109 SET_FAR(base, ctx, 0); 110 SET_CTX_TLBIALL(base, ctx, 0); 111 SET_TLBFLPTER(base, ctx, 0); 112 SET_TLBSLPTER(base, ctx, 0); 113 SET_TLBLKCR(base, ctx, 0); 114 SET_CONTEXTIDR(base, ctx, 0); 115 } 116 } 117 118 static void __flush_iotlb(void *cookie) 119 { 120 struct msm_priv *priv = cookie; 121 struct msm_iommu_dev *iommu = NULL; 122 struct msm_iommu_ctx_dev *master; 123 int ret = 0; 124 125 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 126 ret = __enable_clocks(iommu); 127 if (ret) 128 goto fail; 129 130 list_for_each_entry(master, &iommu->ctx_list, list) 131 SET_CTX_TLBIALL(iommu->base, master->num, 0); 132 133 __disable_clocks(iommu); 134 } 135 fail: 136 return; 137 } 138 139 static void __flush_iotlb_range(unsigned long iova, size_t size, 140 size_t granule, bool leaf, void *cookie) 141 { 142 struct msm_priv *priv = cookie; 143 struct msm_iommu_dev *iommu = NULL; 144 struct msm_iommu_ctx_dev *master; 145 int ret = 0; 146 int temp_size; 147 148 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 149 ret = __enable_clocks(iommu); 150 if (ret) 151 goto fail; 152 153 list_for_each_entry(master, &iommu->ctx_list, list) { 154 temp_size = size; 155 do { 156 iova &= TLBIVA_VA; 157 iova |= GET_CONTEXTIDR_ASID(iommu->base, 158 master->num); 159 SET_TLBIVA(iommu->base, master->num, iova); 160 iova += granule; 161 } while (temp_size -= granule); 162 } 163 164 __disable_clocks(iommu); 165 } 166 167 fail: 168 return; 169 } 170 171 static void __flush_iotlb_walk(unsigned long iova, size_t size, 172 size_t granule, void *cookie) 173 { 174 __flush_iotlb_range(iova, size, granule, false, cookie); 175 } 176 177 static void __flush_iotlb_page(struct iommu_iotlb_gather *gather, 178 unsigned long iova, size_t granule, void *cookie) 179 { 180 __flush_iotlb_range(iova, granule, granule, true, cookie); 181 } 182 183 static const struct iommu_flush_ops msm_iommu_flush_ops = { 184 .tlb_flush_all = __flush_iotlb, 185 .tlb_flush_walk = __flush_iotlb_walk, 186 .tlb_add_page = __flush_iotlb_page, 187 }; 188 189 static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end) 190 { 191 int idx; 192 193 do { 194 idx = find_next_zero_bit(map, end, start); 195 if (idx == end) 196 return -ENOSPC; 197 } while (test_and_set_bit(idx, map)); 198 199 return idx; 200 } 201 202 static void msm_iommu_free_ctx(unsigned long *map, int idx) 203 { 204 clear_bit(idx, map); 205 } 206 207 static void config_mids(struct msm_iommu_dev *iommu, 208 struct msm_iommu_ctx_dev *master) 209 { 210 int mid, ctx, i; 211 212 for (i = 0; i < master->num_mids; i++) { 213 mid = master->mids[i]; 214 ctx = master->num; 215 216 SET_M2VCBR_N(iommu->base, mid, 0); 217 SET_CBACR_N(iommu->base, ctx, 0); 218 219 /* Set VMID = 0 */ 220 SET_VMID(iommu->base, mid, 0); 221 222 /* Set the context number for that MID to this context */ 223 SET_CBNDX(iommu->base, mid, ctx); 224 225 /* Set MID associated with this context bank to 0*/ 226 SET_CBVMID(iommu->base, ctx, 0); 227 228 /* Set the ASID for TLB tagging for this context */ 229 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx); 230 231 /* Set security bit override to be Non-secure */ 232 SET_NSCFG(iommu->base, mid, 3); 233 } 234 } 235 236 static void __reset_context(void __iomem *base, int ctx) 237 { 238 SET_BPRCOSH(base, ctx, 0); 239 SET_BPRCISH(base, ctx, 0); 240 SET_BPRCNSH(base, ctx, 0); 241 SET_BPSHCFG(base, ctx, 0); 242 SET_BPMTCFG(base, ctx, 0); 243 SET_ACTLR(base, ctx, 0); 244 SET_SCTLR(base, ctx, 0); 245 SET_FSRRESTORE(base, ctx, 0); 246 SET_TTBR0(base, ctx, 0); 247 SET_TTBR1(base, ctx, 0); 248 SET_TTBCR(base, ctx, 0); 249 SET_BFBCR(base, ctx, 0); 250 SET_PAR(base, ctx, 0); 251 SET_FAR(base, ctx, 0); 252 SET_CTX_TLBIALL(base, ctx, 0); 253 SET_TLBFLPTER(base, ctx, 0); 254 SET_TLBSLPTER(base, ctx, 0); 255 SET_TLBLKCR(base, ctx, 0); 256 } 257 258 static void __program_context(void __iomem *base, int ctx, 259 struct msm_priv *priv) 260 { 261 __reset_context(base, ctx); 262 263 /* Turn on TEX Remap */ 264 SET_TRE(base, ctx, 1); 265 SET_AFE(base, ctx, 1); 266 267 /* Set up HTW mode */ 268 /* TLB miss configuration: perform HTW on miss */ 269 SET_TLBMCFG(base, ctx, 0x3); 270 271 /* V2P configuration: HTW for access */ 272 SET_V2PCFG(base, ctx, 0x3); 273 274 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); 275 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); 276 SET_TTBR1(base, ctx, 0); 277 278 /* Set prrr and nmrr */ 279 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); 280 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr); 281 282 /* Invalidate the TLB for this context */ 283 SET_CTX_TLBIALL(base, ctx, 0); 284 285 /* Set interrupt number to "secure" interrupt */ 286 SET_IRPTNDX(base, ctx, 0); 287 288 /* Enable context fault interrupt */ 289 SET_CFEIE(base, ctx, 1); 290 291 /* Stall access on a context fault and let the handler deal with it */ 292 SET_CFCFG(base, ctx, 1); 293 294 /* Redirect all cacheable requests to L2 slave port. */ 295 SET_RCISH(base, ctx, 1); 296 SET_RCOSH(base, ctx, 1); 297 SET_RCNSH(base, ctx, 1); 298 299 /* Turn on BFB prefetch */ 300 SET_BFBDFE(base, ctx, 1); 301 302 /* Enable the MMU */ 303 SET_M(base, ctx, 1); 304 } 305 306 static struct iommu_domain *msm_iommu_domain_alloc(unsigned type) 307 { 308 struct msm_priv *priv; 309 310 if (type != IOMMU_DOMAIN_UNMANAGED) 311 return NULL; 312 313 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 314 if (!priv) 315 goto fail_nomem; 316 317 INIT_LIST_HEAD(&priv->list_attached); 318 319 priv->domain.geometry.aperture_start = 0; 320 priv->domain.geometry.aperture_end = (1ULL << 32) - 1; 321 priv->domain.geometry.force_aperture = true; 322 323 return &priv->domain; 324 325 fail_nomem: 326 kfree(priv); 327 return NULL; 328 } 329 330 static void msm_iommu_domain_free(struct iommu_domain *domain) 331 { 332 struct msm_priv *priv; 333 unsigned long flags; 334 335 spin_lock_irqsave(&msm_iommu_lock, flags); 336 priv = to_msm_priv(domain); 337 kfree(priv); 338 spin_unlock_irqrestore(&msm_iommu_lock, flags); 339 } 340 341 static int msm_iommu_domain_config(struct msm_priv *priv) 342 { 343 spin_lock_init(&priv->pgtlock); 344 345 priv->cfg = (struct io_pgtable_cfg) { 346 .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap, 347 .ias = 32, 348 .oas = 32, 349 .tlb = &msm_iommu_flush_ops, 350 .iommu_dev = priv->dev, 351 }; 352 353 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv); 354 if (!priv->iop) { 355 dev_err(priv->dev, "Failed to allocate pgtable\n"); 356 return -EINVAL; 357 } 358 359 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap; 360 361 return 0; 362 } 363 364 /* Must be called under msm_iommu_lock */ 365 static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev) 366 { 367 struct msm_iommu_dev *iommu, *ret = NULL; 368 struct msm_iommu_ctx_dev *master; 369 370 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { 371 master = list_first_entry(&iommu->ctx_list, 372 struct msm_iommu_ctx_dev, 373 list); 374 if (master->of_node == dev->of_node) { 375 ret = iommu; 376 break; 377 } 378 } 379 380 return ret; 381 } 382 383 static struct iommu_device *msm_iommu_probe_device(struct device *dev) 384 { 385 struct msm_iommu_dev *iommu; 386 unsigned long flags; 387 388 spin_lock_irqsave(&msm_iommu_lock, flags); 389 iommu = find_iommu_for_dev(dev); 390 spin_unlock_irqrestore(&msm_iommu_lock, flags); 391 392 if (!iommu) 393 return ERR_PTR(-ENODEV); 394 395 return &iommu->iommu; 396 } 397 398 static void msm_iommu_release_device(struct device *dev) 399 { 400 } 401 402 static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) 403 { 404 int ret = 0; 405 unsigned long flags; 406 struct msm_iommu_dev *iommu; 407 struct msm_priv *priv = to_msm_priv(domain); 408 struct msm_iommu_ctx_dev *master; 409 410 priv->dev = dev; 411 msm_iommu_domain_config(priv); 412 413 spin_lock_irqsave(&msm_iommu_lock, flags); 414 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { 415 master = list_first_entry(&iommu->ctx_list, 416 struct msm_iommu_ctx_dev, 417 list); 418 if (master->of_node == dev->of_node) { 419 ret = __enable_clocks(iommu); 420 if (ret) 421 goto fail; 422 423 list_for_each_entry(master, &iommu->ctx_list, list) { 424 if (master->num) { 425 dev_err(dev, "domain already attached"); 426 ret = -EEXIST; 427 goto fail; 428 } 429 master->num = 430 msm_iommu_alloc_ctx(iommu->context_map, 431 0, iommu->ncb); 432 if (IS_ERR_VALUE(master->num)) { 433 ret = -ENODEV; 434 goto fail; 435 } 436 config_mids(iommu, master); 437 __program_context(iommu->base, master->num, 438 priv); 439 } 440 __disable_clocks(iommu); 441 list_add(&iommu->dom_node, &priv->list_attached); 442 } 443 } 444 445 fail: 446 spin_unlock_irqrestore(&msm_iommu_lock, flags); 447 448 return ret; 449 } 450 451 static void msm_iommu_detach_dev(struct iommu_domain *domain, 452 struct device *dev) 453 { 454 struct msm_priv *priv = to_msm_priv(domain); 455 unsigned long flags; 456 struct msm_iommu_dev *iommu; 457 struct msm_iommu_ctx_dev *master; 458 int ret; 459 460 free_io_pgtable_ops(priv->iop); 461 462 spin_lock_irqsave(&msm_iommu_lock, flags); 463 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 464 ret = __enable_clocks(iommu); 465 if (ret) 466 goto fail; 467 468 list_for_each_entry(master, &iommu->ctx_list, list) { 469 msm_iommu_free_ctx(iommu->context_map, master->num); 470 __reset_context(iommu->base, master->num); 471 } 472 __disable_clocks(iommu); 473 } 474 fail: 475 spin_unlock_irqrestore(&msm_iommu_lock, flags); 476 } 477 478 static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, 479 phys_addr_t pa, size_t len, int prot, gfp_t gfp) 480 { 481 struct msm_priv *priv = to_msm_priv(domain); 482 unsigned long flags; 483 int ret; 484 485 spin_lock_irqsave(&priv->pgtlock, flags); 486 ret = priv->iop->map(priv->iop, iova, pa, len, prot, GFP_ATOMIC); 487 spin_unlock_irqrestore(&priv->pgtlock, flags); 488 489 return ret; 490 } 491 492 static void msm_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 493 size_t size) 494 { 495 struct msm_priv *priv = to_msm_priv(domain); 496 497 __flush_iotlb_range(iova, size, SZ_4K, false, priv); 498 } 499 500 static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 501 size_t len, struct iommu_iotlb_gather *gather) 502 { 503 struct msm_priv *priv = to_msm_priv(domain); 504 unsigned long flags; 505 506 spin_lock_irqsave(&priv->pgtlock, flags); 507 len = priv->iop->unmap(priv->iop, iova, len, gather); 508 spin_unlock_irqrestore(&priv->pgtlock, flags); 509 510 return len; 511 } 512 513 static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, 514 dma_addr_t va) 515 { 516 struct msm_priv *priv; 517 struct msm_iommu_dev *iommu; 518 struct msm_iommu_ctx_dev *master; 519 unsigned int par; 520 unsigned long flags; 521 phys_addr_t ret = 0; 522 523 spin_lock_irqsave(&msm_iommu_lock, flags); 524 525 priv = to_msm_priv(domain); 526 iommu = list_first_entry(&priv->list_attached, 527 struct msm_iommu_dev, dom_node); 528 529 if (list_empty(&iommu->ctx_list)) 530 goto fail; 531 532 master = list_first_entry(&iommu->ctx_list, 533 struct msm_iommu_ctx_dev, list); 534 if (!master) 535 goto fail; 536 537 ret = __enable_clocks(iommu); 538 if (ret) 539 goto fail; 540 541 /* Invalidate context TLB */ 542 SET_CTX_TLBIALL(iommu->base, master->num, 0); 543 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); 544 545 par = GET_PAR(iommu->base, master->num); 546 547 /* We are dealing with a supersection */ 548 if (GET_NOFAULT_SS(iommu->base, master->num)) 549 ret = (par & 0xFF000000) | (va & 0x00FFFFFF); 550 else /* Upper 20 bits from PAR, lower 12 from VA */ 551 ret = (par & 0xFFFFF000) | (va & 0x00000FFF); 552 553 if (GET_FAULT(iommu->base, master->num)) 554 ret = 0; 555 556 __disable_clocks(iommu); 557 fail: 558 spin_unlock_irqrestore(&msm_iommu_lock, flags); 559 return ret; 560 } 561 562 static bool msm_iommu_capable(enum iommu_cap cap) 563 { 564 return false; 565 } 566 567 static void print_ctx_regs(void __iomem *base, int ctx) 568 { 569 unsigned int fsr = GET_FSR(base, ctx); 570 pr_err("FAR = %08x PAR = %08x\n", 571 GET_FAR(base, ctx), GET_PAR(base, ctx)); 572 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr, 573 (fsr & 0x02) ? "TF " : "", 574 (fsr & 0x04) ? "AFF " : "", 575 (fsr & 0x08) ? "APF " : "", 576 (fsr & 0x10) ? "TLBMF " : "", 577 (fsr & 0x20) ? "HTWDEEF " : "", 578 (fsr & 0x40) ? "HTWSEEF " : "", 579 (fsr & 0x80) ? "MHF " : "", 580 (fsr & 0x10000) ? "SL " : "", 581 (fsr & 0x40000000) ? "SS " : "", 582 (fsr & 0x80000000) ? "MULTI " : ""); 583 584 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n", 585 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx)); 586 pr_err("TTBR0 = %08x TTBR1 = %08x\n", 587 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx)); 588 pr_err("SCTLR = %08x ACTLR = %08x\n", 589 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx)); 590 } 591 592 static void insert_iommu_master(struct device *dev, 593 struct msm_iommu_dev **iommu, 594 struct of_phandle_args *spec) 595 { 596 struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev); 597 int sid; 598 599 if (list_empty(&(*iommu)->ctx_list)) { 600 master = kzalloc(sizeof(*master), GFP_ATOMIC); 601 master->of_node = dev->of_node; 602 list_add(&master->list, &(*iommu)->ctx_list); 603 dev_iommu_priv_set(dev, master); 604 } 605 606 for (sid = 0; sid < master->num_mids; sid++) 607 if (master->mids[sid] == spec->args[0]) { 608 dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n", 609 sid); 610 return; 611 } 612 613 master->mids[master->num_mids++] = spec->args[0]; 614 } 615 616 static int qcom_iommu_of_xlate(struct device *dev, 617 struct of_phandle_args *spec) 618 { 619 struct msm_iommu_dev *iommu; 620 unsigned long flags; 621 int ret = 0; 622 623 spin_lock_irqsave(&msm_iommu_lock, flags); 624 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) 625 if (iommu->dev->of_node == spec->np) 626 break; 627 628 if (!iommu || iommu->dev->of_node != spec->np) { 629 ret = -ENODEV; 630 goto fail; 631 } 632 633 insert_iommu_master(dev, &iommu, spec); 634 fail: 635 spin_unlock_irqrestore(&msm_iommu_lock, flags); 636 637 return ret; 638 } 639 640 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) 641 { 642 struct msm_iommu_dev *iommu = dev_id; 643 unsigned int fsr; 644 int i, ret; 645 646 spin_lock(&msm_iommu_lock); 647 648 if (!iommu) { 649 pr_err("Invalid device ID in context interrupt handler\n"); 650 goto fail; 651 } 652 653 pr_err("Unexpected IOMMU page fault!\n"); 654 pr_err("base = %08x\n", (unsigned int)iommu->base); 655 656 ret = __enable_clocks(iommu); 657 if (ret) 658 goto fail; 659 660 for (i = 0; i < iommu->ncb; i++) { 661 fsr = GET_FSR(iommu->base, i); 662 if (fsr) { 663 pr_err("Fault occurred in context %d.\n", i); 664 pr_err("Interesting registers:\n"); 665 print_ctx_regs(iommu->base, i); 666 SET_FSR(iommu->base, i, 0x4000000F); 667 } 668 } 669 __disable_clocks(iommu); 670 fail: 671 spin_unlock(&msm_iommu_lock); 672 return 0; 673 } 674 675 static struct iommu_ops msm_iommu_ops = { 676 .capable = msm_iommu_capable, 677 .domain_alloc = msm_iommu_domain_alloc, 678 .domain_free = msm_iommu_domain_free, 679 .attach_dev = msm_iommu_attach_dev, 680 .detach_dev = msm_iommu_detach_dev, 681 .map = msm_iommu_map, 682 .unmap = msm_iommu_unmap, 683 /* 684 * Nothing is needed here, the barrier to guarantee 685 * completion of the tlb sync operation is implicitly 686 * taken care when the iommu client does a writel before 687 * kick starting the other master. 688 */ 689 .iotlb_sync = NULL, 690 .iotlb_sync_map = msm_iommu_sync_map, 691 .iova_to_phys = msm_iommu_iova_to_phys, 692 .probe_device = msm_iommu_probe_device, 693 .release_device = msm_iommu_release_device, 694 .device_group = generic_device_group, 695 .pgsize_bitmap = MSM_IOMMU_PGSIZES, 696 .of_xlate = qcom_iommu_of_xlate, 697 }; 698 699 static int msm_iommu_probe(struct platform_device *pdev) 700 { 701 struct resource *r; 702 resource_size_t ioaddr; 703 struct msm_iommu_dev *iommu; 704 int ret, par, val; 705 706 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL); 707 if (!iommu) 708 return -ENODEV; 709 710 iommu->dev = &pdev->dev; 711 INIT_LIST_HEAD(&iommu->ctx_list); 712 713 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk"); 714 if (IS_ERR(iommu->pclk)) { 715 dev_err(iommu->dev, "could not get smmu_pclk\n"); 716 return PTR_ERR(iommu->pclk); 717 } 718 719 ret = clk_prepare(iommu->pclk); 720 if (ret) { 721 dev_err(iommu->dev, "could not prepare smmu_pclk\n"); 722 return ret; 723 } 724 725 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk"); 726 if (IS_ERR(iommu->clk)) { 727 dev_err(iommu->dev, "could not get iommu_clk\n"); 728 clk_unprepare(iommu->pclk); 729 return PTR_ERR(iommu->clk); 730 } 731 732 ret = clk_prepare(iommu->clk); 733 if (ret) { 734 dev_err(iommu->dev, "could not prepare iommu_clk\n"); 735 clk_unprepare(iommu->pclk); 736 return ret; 737 } 738 739 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 740 iommu->base = devm_ioremap_resource(iommu->dev, r); 741 if (IS_ERR(iommu->base)) { 742 dev_err(iommu->dev, "could not get iommu base\n"); 743 ret = PTR_ERR(iommu->base); 744 goto fail; 745 } 746 ioaddr = r->start; 747 748 iommu->irq = platform_get_irq(pdev, 0); 749 if (iommu->irq < 0) { 750 ret = -ENODEV; 751 goto fail; 752 } 753 754 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val); 755 if (ret) { 756 dev_err(iommu->dev, "could not get ncb\n"); 757 goto fail; 758 } 759 iommu->ncb = val; 760 761 msm_iommu_reset(iommu->base, iommu->ncb); 762 SET_M(iommu->base, 0, 1); 763 SET_PAR(iommu->base, 0, 0); 764 SET_V2PCFG(iommu->base, 0, 1); 765 SET_V2PPR(iommu->base, 0, 0); 766 par = GET_PAR(iommu->base, 0); 767 SET_V2PCFG(iommu->base, 0, 0); 768 SET_M(iommu->base, 0, 0); 769 770 if (!par) { 771 pr_err("Invalid PAR value detected\n"); 772 ret = -ENODEV; 773 goto fail; 774 } 775 776 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL, 777 msm_iommu_fault_handler, 778 IRQF_ONESHOT | IRQF_SHARED, 779 "msm_iommu_secure_irpt_handler", 780 iommu); 781 if (ret) { 782 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret); 783 goto fail; 784 } 785 786 list_add(&iommu->dev_node, &qcom_iommu_devices); 787 788 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL, 789 "msm-smmu.%pa", &ioaddr); 790 if (ret) { 791 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr); 792 goto fail; 793 } 794 795 iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops); 796 iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode); 797 798 ret = iommu_device_register(&iommu->iommu); 799 if (ret) { 800 pr_err("Could not register msm-smmu at %pa\n", &ioaddr); 801 goto fail; 802 } 803 804 bus_set_iommu(&platform_bus_type, &msm_iommu_ops); 805 806 pr_info("device mapped at %p, irq %d with %d ctx banks\n", 807 iommu->base, iommu->irq, iommu->ncb); 808 809 return ret; 810 fail: 811 clk_unprepare(iommu->clk); 812 clk_unprepare(iommu->pclk); 813 return ret; 814 } 815 816 static const struct of_device_id msm_iommu_dt_match[] = { 817 { .compatible = "qcom,apq8064-iommu" }, 818 {} 819 }; 820 821 static int msm_iommu_remove(struct platform_device *pdev) 822 { 823 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev); 824 825 clk_unprepare(iommu->clk); 826 clk_unprepare(iommu->pclk); 827 return 0; 828 } 829 830 static struct platform_driver msm_iommu_driver = { 831 .driver = { 832 .name = "msm_iommu", 833 .of_match_table = msm_iommu_dt_match, 834 }, 835 .probe = msm_iommu_probe, 836 .remove = msm_iommu_remove, 837 }; 838 839 static int __init msm_iommu_driver_init(void) 840 { 841 int ret; 842 843 ret = platform_driver_register(&msm_iommu_driver); 844 if (ret != 0) 845 pr_err("Failed to register IOMMU driver\n"); 846 847 return ret; 848 } 849 subsys_initcall(msm_iommu_driver_init); 850 851