1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * IOMMU API for Renesas VMSA-compatible IPMMU 4 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * 6 * Copyright (C) 2014 Renesas Electronics Corporation 7 */ 8 9 #include <linux/bitmap.h> 10 #include <linux/delay.h> 11 #include <linux/dma-iommu.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/err.h> 14 #include <linux/export.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/io-pgtable.h> 19 #include <linux/iommu.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_iommu.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/sizes.h> 26 #include <linux/slab.h> 27 #include <linux/sys_soc.h> 28 29 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 30 #include <asm/dma-iommu.h> 31 #include <asm/pgalloc.h> 32 #else 33 #define arm_iommu_create_mapping(...) NULL 34 #define arm_iommu_attach_device(...) -ENODEV 35 #define arm_iommu_release_mapping(...) do {} while (0) 36 #define arm_iommu_detach_device(...) do {} while (0) 37 #endif 38 39 #define IPMMU_CTX_MAX 8U 40 #define IPMMU_CTX_INVALID -1 41 42 #define IPMMU_UTLB_MAX 48U 43 44 struct ipmmu_features { 45 bool use_ns_alias_offset; 46 bool has_cache_leaf_nodes; 47 unsigned int number_of_contexts; 48 unsigned int num_utlbs; 49 bool setup_imbuscr; 50 bool twobit_imttbcr_sl0; 51 bool reserved_context; 52 }; 53 54 struct ipmmu_vmsa_device { 55 struct device *dev; 56 void __iomem *base; 57 struct iommu_device iommu; 58 struct ipmmu_vmsa_device *root; 59 const struct ipmmu_features *features; 60 unsigned int num_ctx; 61 spinlock_t lock; /* Protects ctx and domains[] */ 62 DECLARE_BITMAP(ctx, IPMMU_CTX_MAX); 63 struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; 64 s8 utlb_ctx[IPMMU_UTLB_MAX]; 65 66 struct iommu_group *group; 67 struct dma_iommu_mapping *mapping; 68 }; 69 70 struct ipmmu_vmsa_domain { 71 struct ipmmu_vmsa_device *mmu; 72 struct iommu_domain io_domain; 73 74 struct io_pgtable_cfg cfg; 75 struct io_pgtable_ops *iop; 76 77 unsigned int context_id; 78 struct mutex mutex; /* Protects mappings */ 79 }; 80 81 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom) 82 { 83 return container_of(dom, struct ipmmu_vmsa_domain, io_domain); 84 } 85 86 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) 87 { 88 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 89 90 return fwspec ? fwspec->iommu_priv : NULL; 91 } 92 93 #define TLB_LOOP_TIMEOUT 100 /* 100us */ 94 95 /* ----------------------------------------------------------------------------- 96 * Registers Definition 97 */ 98 99 #define IM_NS_ALIAS_OFFSET 0x800 100 101 #define IM_CTX_SIZE 0x40 102 103 #define IMCTR 0x0000 104 #define IMCTR_TRE (1 << 17) 105 #define IMCTR_AFE (1 << 16) 106 #define IMCTR_RTSEL_MASK (3 << 4) 107 #define IMCTR_RTSEL_SHIFT 4 108 #define IMCTR_TREN (1 << 3) 109 #define IMCTR_INTEN (1 << 2) 110 #define IMCTR_FLUSH (1 << 1) 111 #define IMCTR_MMUEN (1 << 0) 112 113 #define IMCAAR 0x0004 114 115 #define IMTTBCR 0x0008 116 #define IMTTBCR_EAE (1 << 31) 117 #define IMTTBCR_PMB (1 << 30) 118 #define IMTTBCR_SH1_NON_SHAREABLE (0 << 28) 119 #define IMTTBCR_SH1_OUTER_SHAREABLE (2 << 28) 120 #define IMTTBCR_SH1_INNER_SHAREABLE (3 << 28) 121 #define IMTTBCR_SH1_MASK (3 << 28) 122 #define IMTTBCR_ORGN1_NC (0 << 26) 123 #define IMTTBCR_ORGN1_WB_WA (1 << 26) 124 #define IMTTBCR_ORGN1_WT (2 << 26) 125 #define IMTTBCR_ORGN1_WB (3 << 26) 126 #define IMTTBCR_ORGN1_MASK (3 << 26) 127 #define IMTTBCR_IRGN1_NC (0 << 24) 128 #define IMTTBCR_IRGN1_WB_WA (1 << 24) 129 #define IMTTBCR_IRGN1_WT (2 << 24) 130 #define IMTTBCR_IRGN1_WB (3 << 24) 131 #define IMTTBCR_IRGN1_MASK (3 << 24) 132 #define IMTTBCR_TSZ1_MASK (7 << 16) 133 #define IMTTBCR_TSZ1_SHIFT 16 134 #define IMTTBCR_SH0_NON_SHAREABLE (0 << 12) 135 #define IMTTBCR_SH0_OUTER_SHAREABLE (2 << 12) 136 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) 137 #define IMTTBCR_SH0_MASK (3 << 12) 138 #define IMTTBCR_ORGN0_NC (0 << 10) 139 #define IMTTBCR_ORGN0_WB_WA (1 << 10) 140 #define IMTTBCR_ORGN0_WT (2 << 10) 141 #define IMTTBCR_ORGN0_WB (3 << 10) 142 #define IMTTBCR_ORGN0_MASK (3 << 10) 143 #define IMTTBCR_IRGN0_NC (0 << 8) 144 #define IMTTBCR_IRGN0_WB_WA (1 << 8) 145 #define IMTTBCR_IRGN0_WT (2 << 8) 146 #define IMTTBCR_IRGN0_WB (3 << 8) 147 #define IMTTBCR_IRGN0_MASK (3 << 8) 148 #define IMTTBCR_SL0_LVL_2 (0 << 4) 149 #define IMTTBCR_SL0_LVL_1 (1 << 4) 150 #define IMTTBCR_TSZ0_MASK (7 << 0) 151 #define IMTTBCR_TSZ0_SHIFT O 152 153 #define IMTTBCR_SL0_TWOBIT_LVL_3 (0 << 6) 154 #define IMTTBCR_SL0_TWOBIT_LVL_2 (1 << 6) 155 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) 156 157 #define IMBUSCR 0x000c 158 #define IMBUSCR_DVM (1 << 2) 159 #define IMBUSCR_BUSSEL_SYS (0 << 0) 160 #define IMBUSCR_BUSSEL_CCI (1 << 0) 161 #define IMBUSCR_BUSSEL_IMCAAR (2 << 0) 162 #define IMBUSCR_BUSSEL_CCI_IMCAAR (3 << 0) 163 #define IMBUSCR_BUSSEL_MASK (3 << 0) 164 165 #define IMTTLBR0 0x0010 166 #define IMTTUBR0 0x0014 167 #define IMTTLBR1 0x0018 168 #define IMTTUBR1 0x001c 169 170 #define IMSTR 0x0020 171 #define IMSTR_ERRLVL_MASK (3 << 12) 172 #define IMSTR_ERRLVL_SHIFT 12 173 #define IMSTR_ERRCODE_TLB_FORMAT (1 << 8) 174 #define IMSTR_ERRCODE_ACCESS_PERM (4 << 8) 175 #define IMSTR_ERRCODE_SECURE_ACCESS (5 << 8) 176 #define IMSTR_ERRCODE_MASK (7 << 8) 177 #define IMSTR_MHIT (1 << 4) 178 #define IMSTR_ABORT (1 << 2) 179 #define IMSTR_PF (1 << 1) 180 #define IMSTR_TF (1 << 0) 181 182 #define IMMAIR0 0x0028 183 #define IMMAIR1 0x002c 184 #define IMMAIR_ATTR_MASK 0xff 185 #define IMMAIR_ATTR_DEVICE 0x04 186 #define IMMAIR_ATTR_NC 0x44 187 #define IMMAIR_ATTR_WBRWA 0xff 188 #define IMMAIR_ATTR_SHIFT(n) ((n) << 3) 189 #define IMMAIR_ATTR_IDX_NC 0 190 #define IMMAIR_ATTR_IDX_WBRWA 1 191 #define IMMAIR_ATTR_IDX_DEV 2 192 193 #define IMELAR 0x0030 /* IMEAR on R-Car Gen2 */ 194 #define IMEUAR 0x0034 /* R-Car Gen3 only */ 195 196 #define IMPCTR 0x0200 197 #define IMPSTR 0x0208 198 #define IMPEAR 0x020c 199 #define IMPMBA(n) (0x0280 + ((n) * 4)) 200 #define IMPMBD(n) (0x02c0 + ((n) * 4)) 201 202 #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n)) 203 #define IMUCTR0(n) (0x0300 + ((n) * 16)) 204 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) 205 #define IMUCTR_FIXADDEN (1 << 31) 206 #define IMUCTR_FIXADD_MASK (0xff << 16) 207 #define IMUCTR_FIXADD_SHIFT 16 208 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) 209 #define IMUCTR_TTSEL_PMB (8 << 4) 210 #define IMUCTR_TTSEL_MASK (15 << 4) 211 #define IMUCTR_FLUSH (1 << 1) 212 #define IMUCTR_MMUEN (1 << 0) 213 214 #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n)) 215 #define IMUASID0(n) (0x0308 + ((n) * 16)) 216 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) 217 #define IMUASID_ASID8_MASK (0xff << 8) 218 #define IMUASID_ASID8_SHIFT 8 219 #define IMUASID_ASID0_MASK (0xff << 0) 220 #define IMUASID_ASID0_SHIFT 0 221 222 /* ----------------------------------------------------------------------------- 223 * Root device handling 224 */ 225 226 static struct platform_driver ipmmu_driver; 227 228 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu) 229 { 230 return mmu->root == mmu; 231 } 232 233 static int __ipmmu_check_device(struct device *dev, void *data) 234 { 235 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); 236 struct ipmmu_vmsa_device **rootp = data; 237 238 if (ipmmu_is_root(mmu)) 239 *rootp = mmu; 240 241 return 0; 242 } 243 244 static struct ipmmu_vmsa_device *ipmmu_find_root(void) 245 { 246 struct ipmmu_vmsa_device *root = NULL; 247 248 return driver_for_each_device(&ipmmu_driver.driver, NULL, &root, 249 __ipmmu_check_device) == 0 ? root : NULL; 250 } 251 252 /* ----------------------------------------------------------------------------- 253 * Read/Write Access 254 */ 255 256 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset) 257 { 258 return ioread32(mmu->base + offset); 259 } 260 261 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset, 262 u32 data) 263 { 264 iowrite32(data, mmu->base + offset); 265 } 266 267 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain, 268 unsigned int reg) 269 { 270 return ipmmu_read(domain->mmu->root, 271 domain->context_id * IM_CTX_SIZE + reg); 272 } 273 274 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain, 275 unsigned int reg, u32 data) 276 { 277 ipmmu_write(domain->mmu->root, 278 domain->context_id * IM_CTX_SIZE + reg, data); 279 } 280 281 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain, 282 unsigned int reg, u32 data) 283 { 284 if (domain->mmu != domain->mmu->root) 285 ipmmu_write(domain->mmu, 286 domain->context_id * IM_CTX_SIZE + reg, data); 287 288 ipmmu_write(domain->mmu->root, 289 domain->context_id * IM_CTX_SIZE + reg, data); 290 } 291 292 /* ----------------------------------------------------------------------------- 293 * TLB and microTLB Management 294 */ 295 296 /* Wait for any pending TLB invalidations to complete */ 297 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain) 298 { 299 unsigned int count = 0; 300 301 while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) { 302 cpu_relax(); 303 if (++count == TLB_LOOP_TIMEOUT) { 304 dev_err_ratelimited(domain->mmu->dev, 305 "TLB sync timed out -- MMU may be deadlocked\n"); 306 return; 307 } 308 udelay(1); 309 } 310 } 311 312 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain) 313 { 314 u32 reg; 315 316 reg = ipmmu_ctx_read_root(domain, IMCTR); 317 reg |= IMCTR_FLUSH; 318 ipmmu_ctx_write_all(domain, IMCTR, reg); 319 320 ipmmu_tlb_sync(domain); 321 } 322 323 /* 324 * Enable MMU translation for the microTLB. 325 */ 326 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, 327 unsigned int utlb) 328 { 329 struct ipmmu_vmsa_device *mmu = domain->mmu; 330 331 /* 332 * TODO: Reference-count the microTLB as several bus masters can be 333 * connected to the same microTLB. 334 */ 335 336 /* TODO: What should we set the ASID to ? */ 337 ipmmu_write(mmu, IMUASID(utlb), 0); 338 /* TODO: Do we need to flush the microTLB ? */ 339 ipmmu_write(mmu, IMUCTR(utlb), 340 IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH | 341 IMUCTR_MMUEN); 342 mmu->utlb_ctx[utlb] = domain->context_id; 343 } 344 345 /* 346 * Disable MMU translation for the microTLB. 347 */ 348 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, 349 unsigned int utlb) 350 { 351 struct ipmmu_vmsa_device *mmu = domain->mmu; 352 353 ipmmu_write(mmu, IMUCTR(utlb), 0); 354 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; 355 } 356 357 static void ipmmu_tlb_flush_all(void *cookie) 358 { 359 struct ipmmu_vmsa_domain *domain = cookie; 360 361 ipmmu_tlb_invalidate(domain); 362 } 363 364 static void ipmmu_tlb_add_flush(unsigned long iova, size_t size, 365 size_t granule, bool leaf, void *cookie) 366 { 367 /* The hardware doesn't support selective TLB flush. */ 368 } 369 370 static const struct iommu_gather_ops ipmmu_gather_ops = { 371 .tlb_flush_all = ipmmu_tlb_flush_all, 372 .tlb_add_flush = ipmmu_tlb_add_flush, 373 .tlb_sync = ipmmu_tlb_flush_all, 374 }; 375 376 /* ----------------------------------------------------------------------------- 377 * Domain/Context Management 378 */ 379 380 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu, 381 struct ipmmu_vmsa_domain *domain) 382 { 383 unsigned long flags; 384 int ret; 385 386 spin_lock_irqsave(&mmu->lock, flags); 387 388 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); 389 if (ret != mmu->num_ctx) { 390 mmu->domains[ret] = domain; 391 set_bit(ret, mmu->ctx); 392 } else 393 ret = -EBUSY; 394 395 spin_unlock_irqrestore(&mmu->lock, flags); 396 397 return ret; 398 } 399 400 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu, 401 unsigned int context_id) 402 { 403 unsigned long flags; 404 405 spin_lock_irqsave(&mmu->lock, flags); 406 407 clear_bit(context_id, mmu->ctx); 408 mmu->domains[context_id] = NULL; 409 410 spin_unlock_irqrestore(&mmu->lock, flags); 411 } 412 413 static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) 414 { 415 u64 ttbr; 416 u32 tmp; 417 418 /* TTBR0 */ 419 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; 420 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); 421 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); 422 423 /* 424 * TTBCR 425 * We use long descriptors with inner-shareable WBWA tables and allocate 426 * the whole 32-bit VA space to TTBR0. 427 */ 428 if (domain->mmu->features->twobit_imttbcr_sl0) 429 tmp = IMTTBCR_SL0_TWOBIT_LVL_1; 430 else 431 tmp = IMTTBCR_SL0_LVL_1; 432 433 ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | 434 IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | 435 IMTTBCR_IRGN0_WB_WA | tmp); 436 437 /* MAIR0 */ 438 ipmmu_ctx_write_root(domain, IMMAIR0, 439 domain->cfg.arm_lpae_s1_cfg.mair[0]); 440 441 /* IMBUSCR */ 442 if (domain->mmu->features->setup_imbuscr) 443 ipmmu_ctx_write_root(domain, IMBUSCR, 444 ipmmu_ctx_read_root(domain, IMBUSCR) & 445 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK)); 446 447 /* 448 * IMSTR 449 * Clear all interrupt flags. 450 */ 451 ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR)); 452 453 /* 454 * IMCTR 455 * Enable the MMU and interrupt generation. The long-descriptor 456 * translation table format doesn't use TEX remapping. Don't enable AF 457 * software management as we have no use for it. Flush the TLB as 458 * required when modifying the context registers. 459 */ 460 ipmmu_ctx_write_all(domain, IMCTR, 461 IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN); 462 } 463 464 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) 465 { 466 int ret; 467 468 /* 469 * Allocate the page table operations. 470 * 471 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory 472 * access, Long-descriptor format" that the NStable bit being set in a 473 * table descriptor will result in the NStable and NS bits of all child 474 * entries being ignored and considered as being set. The IPMMU seems 475 * not to comply with this, as it generates a secure access page fault 476 * if any of the NStable and NS bits isn't set when running in 477 * non-secure mode. 478 */ 479 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; 480 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; 481 domain->cfg.ias = 32; 482 domain->cfg.oas = 40; 483 domain->cfg.tlb = &ipmmu_gather_ops; 484 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); 485 domain->io_domain.geometry.force_aperture = true; 486 /* 487 * TODO: Add support for coherent walk through CCI with DVM and remove 488 * cache handling. For now, delegate it to the io-pgtable code. 489 */ 490 domain->cfg.coherent_walk = false; 491 domain->cfg.iommu_dev = domain->mmu->root->dev; 492 493 /* 494 * Find an unused context. 495 */ 496 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); 497 if (ret < 0) 498 return ret; 499 500 domain->context_id = ret; 501 502 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, 503 domain); 504 if (!domain->iop) { 505 ipmmu_domain_free_context(domain->mmu->root, 506 domain->context_id); 507 return -EINVAL; 508 } 509 510 ipmmu_domain_setup_context(domain); 511 return 0; 512 } 513 514 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain) 515 { 516 if (!domain->mmu) 517 return; 518 519 /* 520 * Disable the context. Flush the TLB as required when modifying the 521 * context registers. 522 * 523 * TODO: Is TLB flush really needed ? 524 */ 525 ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH); 526 ipmmu_tlb_sync(domain); 527 ipmmu_domain_free_context(domain->mmu->root, domain->context_id); 528 } 529 530 /* ----------------------------------------------------------------------------- 531 * Fault Handling 532 */ 533 534 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain) 535 { 536 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF; 537 struct ipmmu_vmsa_device *mmu = domain->mmu; 538 unsigned long iova; 539 u32 status; 540 541 status = ipmmu_ctx_read_root(domain, IMSTR); 542 if (!(status & err_mask)) 543 return IRQ_NONE; 544 545 iova = ipmmu_ctx_read_root(domain, IMELAR); 546 if (IS_ENABLED(CONFIG_64BIT)) 547 iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32; 548 549 /* 550 * Clear the error status flags. Unlike traditional interrupt flag 551 * registers that must be cleared by writing 1, this status register 552 * seems to require 0. The error address register must be read before, 553 * otherwise its value will be 0. 554 */ 555 ipmmu_ctx_write_root(domain, IMSTR, 0); 556 557 /* Log fatal errors. */ 558 if (status & IMSTR_MHIT) 559 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n", 560 iova); 561 if (status & IMSTR_ABORT) 562 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n", 563 iova); 564 565 if (!(status & (IMSTR_PF | IMSTR_TF))) 566 return IRQ_NONE; 567 568 /* 569 * Try to handle page faults and translation faults. 570 * 571 * TODO: We need to look up the faulty device based on the I/O VA. Use 572 * the IOMMU device for now. 573 */ 574 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) 575 return IRQ_HANDLED; 576 577 dev_err_ratelimited(mmu->dev, 578 "Unhandled fault: status 0x%08x iova 0x%lx\n", 579 status, iova); 580 581 return IRQ_HANDLED; 582 } 583 584 static irqreturn_t ipmmu_irq(int irq, void *dev) 585 { 586 struct ipmmu_vmsa_device *mmu = dev; 587 irqreturn_t status = IRQ_NONE; 588 unsigned int i; 589 unsigned long flags; 590 591 spin_lock_irqsave(&mmu->lock, flags); 592 593 /* 594 * Check interrupts for all active contexts. 595 */ 596 for (i = 0; i < mmu->num_ctx; i++) { 597 if (!mmu->domains[i]) 598 continue; 599 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) 600 status = IRQ_HANDLED; 601 } 602 603 spin_unlock_irqrestore(&mmu->lock, flags); 604 605 return status; 606 } 607 608 /* ----------------------------------------------------------------------------- 609 * IOMMU Operations 610 */ 611 612 static struct iommu_domain *__ipmmu_domain_alloc(unsigned type) 613 { 614 struct ipmmu_vmsa_domain *domain; 615 616 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 617 if (!domain) 618 return NULL; 619 620 mutex_init(&domain->mutex); 621 622 return &domain->io_domain; 623 } 624 625 static struct iommu_domain *ipmmu_domain_alloc(unsigned type) 626 { 627 struct iommu_domain *io_domain = NULL; 628 629 switch (type) { 630 case IOMMU_DOMAIN_UNMANAGED: 631 io_domain = __ipmmu_domain_alloc(type); 632 break; 633 634 case IOMMU_DOMAIN_DMA: 635 io_domain = __ipmmu_domain_alloc(type); 636 if (io_domain && iommu_get_dma_cookie(io_domain)) { 637 kfree(io_domain); 638 io_domain = NULL; 639 } 640 break; 641 } 642 643 return io_domain; 644 } 645 646 static void ipmmu_domain_free(struct iommu_domain *io_domain) 647 { 648 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 649 650 /* 651 * Free the domain resources. We assume that all devices have already 652 * been detached. 653 */ 654 iommu_put_dma_cookie(io_domain); 655 ipmmu_domain_destroy_context(domain); 656 free_io_pgtable_ops(domain->iop); 657 kfree(domain); 658 } 659 660 static int ipmmu_attach_device(struct iommu_domain *io_domain, 661 struct device *dev) 662 { 663 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 664 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 665 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 666 unsigned int i; 667 int ret = 0; 668 669 if (!mmu) { 670 dev_err(dev, "Cannot attach to IPMMU\n"); 671 return -ENXIO; 672 } 673 674 mutex_lock(&domain->mutex); 675 676 if (!domain->mmu) { 677 /* The domain hasn't been used yet, initialize it. */ 678 domain->mmu = mmu; 679 ret = ipmmu_domain_init_context(domain); 680 if (ret < 0) { 681 dev_err(dev, "Unable to initialize IPMMU context\n"); 682 domain->mmu = NULL; 683 } else { 684 dev_info(dev, "Using IPMMU context %u\n", 685 domain->context_id); 686 } 687 } else if (domain->mmu != mmu) { 688 /* 689 * Something is wrong, we can't attach two devices using 690 * different IOMMUs to the same domain. 691 */ 692 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n", 693 dev_name(mmu->dev), dev_name(domain->mmu->dev)); 694 ret = -EINVAL; 695 } else 696 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); 697 698 mutex_unlock(&domain->mutex); 699 700 if (ret < 0) 701 return ret; 702 703 for (i = 0; i < fwspec->num_ids; ++i) 704 ipmmu_utlb_enable(domain, fwspec->ids[i]); 705 706 return 0; 707 } 708 709 static void ipmmu_detach_device(struct iommu_domain *io_domain, 710 struct device *dev) 711 { 712 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 713 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 714 unsigned int i; 715 716 for (i = 0; i < fwspec->num_ids; ++i) 717 ipmmu_utlb_disable(domain, fwspec->ids[i]); 718 719 /* 720 * TODO: Optimize by disabling the context when no device is attached. 721 */ 722 } 723 724 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova, 725 phys_addr_t paddr, size_t size, int prot) 726 { 727 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 728 729 if (!domain) 730 return -ENODEV; 731 732 return domain->iop->map(domain->iop, iova, paddr, size, prot); 733 } 734 735 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova, 736 size_t size) 737 { 738 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 739 740 return domain->iop->unmap(domain->iop, iova, size); 741 } 742 743 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain) 744 { 745 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 746 747 if (domain->mmu) 748 ipmmu_tlb_flush_all(domain); 749 } 750 751 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain, 752 dma_addr_t iova) 753 { 754 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 755 756 /* TODO: Is locking needed ? */ 757 758 return domain->iop->iova_to_phys(domain->iop, iova); 759 } 760 761 static int ipmmu_init_platform_device(struct device *dev, 762 struct of_phandle_args *args) 763 { 764 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 765 struct platform_device *ipmmu_pdev; 766 767 ipmmu_pdev = of_find_device_by_node(args->np); 768 if (!ipmmu_pdev) 769 return -ENODEV; 770 771 fwspec->iommu_priv = platform_get_drvdata(ipmmu_pdev); 772 773 return 0; 774 } 775 776 static const struct soc_device_attribute soc_rcar_gen3[] = { 777 { .soc_id = "r8a774a1", }, 778 { .soc_id = "r8a774c0", }, 779 { .soc_id = "r8a7795", }, 780 { .soc_id = "r8a7796", }, 781 { .soc_id = "r8a77965", }, 782 { .soc_id = "r8a77970", }, 783 { .soc_id = "r8a77990", }, 784 { .soc_id = "r8a77995", }, 785 { /* sentinel */ } 786 }; 787 788 static const struct soc_device_attribute soc_rcar_gen3_whitelist[] = { 789 { .soc_id = "r8a774c0", }, 790 { .soc_id = "r8a7795", .revision = "ES3.*" }, 791 { .soc_id = "r8a77965", }, 792 { .soc_id = "r8a77990", }, 793 { .soc_id = "r8a77995", }, 794 { /* sentinel */ } 795 }; 796 797 static const char * const rcar_gen3_slave_whitelist[] = { 798 }; 799 800 static bool ipmmu_slave_whitelist(struct device *dev) 801 { 802 unsigned int i; 803 804 /* 805 * For R-Car Gen3 use a white list to opt-in slave devices. 806 * For Other SoCs, this returns true anyway. 807 */ 808 if (!soc_device_match(soc_rcar_gen3)) 809 return true; 810 811 /* Check whether this R-Car Gen3 can use the IPMMU correctly or not */ 812 if (!soc_device_match(soc_rcar_gen3_whitelist)) 813 return false; 814 815 /* Check whether this slave device can work with the IPMMU */ 816 for (i = 0; i < ARRAY_SIZE(rcar_gen3_slave_whitelist); i++) { 817 if (!strcmp(dev_name(dev), rcar_gen3_slave_whitelist[i])) 818 return true; 819 } 820 821 /* Otherwise, do not allow use of IPMMU */ 822 return false; 823 } 824 825 static int ipmmu_of_xlate(struct device *dev, 826 struct of_phandle_args *spec) 827 { 828 if (!ipmmu_slave_whitelist(dev)) 829 return -ENODEV; 830 831 iommu_fwspec_add_ids(dev, spec->args, 1); 832 833 /* Initialize once - xlate() will call multiple times */ 834 if (to_ipmmu(dev)) 835 return 0; 836 837 return ipmmu_init_platform_device(dev, spec); 838 } 839 840 static int ipmmu_init_arm_mapping(struct device *dev) 841 { 842 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 843 struct iommu_group *group; 844 int ret; 845 846 /* Create a device group and add the device to it. */ 847 group = iommu_group_alloc(); 848 if (IS_ERR(group)) { 849 dev_err(dev, "Failed to allocate IOMMU group\n"); 850 return PTR_ERR(group); 851 } 852 853 ret = iommu_group_add_device(group, dev); 854 iommu_group_put(group); 855 856 if (ret < 0) { 857 dev_err(dev, "Failed to add device to IPMMU group\n"); 858 return ret; 859 } 860 861 /* 862 * Create the ARM mapping, used by the ARM DMA mapping core to allocate 863 * VAs. This will allocate a corresponding IOMMU domain. 864 * 865 * TODO: 866 * - Create one mapping per context (TLB). 867 * - Make the mapping size configurable ? We currently use a 2GB mapping 868 * at a 1GB offset to ensure that NULL VAs will fault. 869 */ 870 if (!mmu->mapping) { 871 struct dma_iommu_mapping *mapping; 872 873 mapping = arm_iommu_create_mapping(&platform_bus_type, 874 SZ_1G, SZ_2G); 875 if (IS_ERR(mapping)) { 876 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); 877 ret = PTR_ERR(mapping); 878 goto error; 879 } 880 881 mmu->mapping = mapping; 882 } 883 884 /* Attach the ARM VA mapping to the device. */ 885 ret = arm_iommu_attach_device(dev, mmu->mapping); 886 if (ret < 0) { 887 dev_err(dev, "Failed to attach device to VA mapping\n"); 888 goto error; 889 } 890 891 return 0; 892 893 error: 894 iommu_group_remove_device(dev); 895 if (mmu->mapping) 896 arm_iommu_release_mapping(mmu->mapping); 897 898 return ret; 899 } 900 901 static int ipmmu_add_device(struct device *dev) 902 { 903 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 904 struct iommu_group *group; 905 int ret; 906 907 /* 908 * Only let through devices that have been verified in xlate() 909 */ 910 if (!mmu) 911 return -ENODEV; 912 913 if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)) { 914 ret = ipmmu_init_arm_mapping(dev); 915 if (ret) 916 return ret; 917 } else { 918 group = iommu_group_get_for_dev(dev); 919 if (IS_ERR(group)) 920 return PTR_ERR(group); 921 922 iommu_group_put(group); 923 } 924 925 iommu_device_link(&mmu->iommu, dev); 926 return 0; 927 } 928 929 static void ipmmu_remove_device(struct device *dev) 930 { 931 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 932 933 iommu_device_unlink(&mmu->iommu, dev); 934 arm_iommu_detach_device(dev); 935 iommu_group_remove_device(dev); 936 } 937 938 static struct iommu_group *ipmmu_find_group(struct device *dev) 939 { 940 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 941 struct iommu_group *group; 942 943 if (mmu->group) 944 return iommu_group_ref_get(mmu->group); 945 946 group = iommu_group_alloc(); 947 if (!IS_ERR(group)) 948 mmu->group = group; 949 950 return group; 951 } 952 953 static const struct iommu_ops ipmmu_ops = { 954 .domain_alloc = ipmmu_domain_alloc, 955 .domain_free = ipmmu_domain_free, 956 .attach_dev = ipmmu_attach_device, 957 .detach_dev = ipmmu_detach_device, 958 .map = ipmmu_map, 959 .unmap = ipmmu_unmap, 960 .flush_iotlb_all = ipmmu_iotlb_sync, 961 .iotlb_sync = ipmmu_iotlb_sync, 962 .iova_to_phys = ipmmu_iova_to_phys, 963 .add_device = ipmmu_add_device, 964 .remove_device = ipmmu_remove_device, 965 .device_group = ipmmu_find_group, 966 .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, 967 .of_xlate = ipmmu_of_xlate, 968 }; 969 970 /* ----------------------------------------------------------------------------- 971 * Probe/remove and init 972 */ 973 974 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) 975 { 976 unsigned int i; 977 978 /* Disable all contexts. */ 979 for (i = 0; i < mmu->num_ctx; ++i) 980 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0); 981 } 982 983 static const struct ipmmu_features ipmmu_features_default = { 984 .use_ns_alias_offset = true, 985 .has_cache_leaf_nodes = false, 986 .number_of_contexts = 1, /* software only tested with one context */ 987 .num_utlbs = 32, 988 .setup_imbuscr = true, 989 .twobit_imttbcr_sl0 = false, 990 .reserved_context = false, 991 }; 992 993 static const struct ipmmu_features ipmmu_features_rcar_gen3 = { 994 .use_ns_alias_offset = false, 995 .has_cache_leaf_nodes = true, 996 .number_of_contexts = 8, 997 .num_utlbs = 48, 998 .setup_imbuscr = false, 999 .twobit_imttbcr_sl0 = true, 1000 .reserved_context = true, 1001 }; 1002 1003 static const struct of_device_id ipmmu_of_ids[] = { 1004 { 1005 .compatible = "renesas,ipmmu-vmsa", 1006 .data = &ipmmu_features_default, 1007 }, { 1008 .compatible = "renesas,ipmmu-r8a774a1", 1009 .data = &ipmmu_features_rcar_gen3, 1010 }, { 1011 .compatible = "renesas,ipmmu-r8a774c0", 1012 .data = &ipmmu_features_rcar_gen3, 1013 }, { 1014 .compatible = "renesas,ipmmu-r8a7795", 1015 .data = &ipmmu_features_rcar_gen3, 1016 }, { 1017 .compatible = "renesas,ipmmu-r8a7796", 1018 .data = &ipmmu_features_rcar_gen3, 1019 }, { 1020 .compatible = "renesas,ipmmu-r8a77965", 1021 .data = &ipmmu_features_rcar_gen3, 1022 }, { 1023 .compatible = "renesas,ipmmu-r8a77970", 1024 .data = &ipmmu_features_rcar_gen3, 1025 }, { 1026 .compatible = "renesas,ipmmu-r8a77990", 1027 .data = &ipmmu_features_rcar_gen3, 1028 }, { 1029 .compatible = "renesas,ipmmu-r8a77995", 1030 .data = &ipmmu_features_rcar_gen3, 1031 }, { 1032 /* Terminator */ 1033 }, 1034 }; 1035 1036 static int ipmmu_probe(struct platform_device *pdev) 1037 { 1038 struct ipmmu_vmsa_device *mmu; 1039 struct resource *res; 1040 int irq; 1041 int ret; 1042 1043 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); 1044 if (!mmu) { 1045 dev_err(&pdev->dev, "cannot allocate device data\n"); 1046 return -ENOMEM; 1047 } 1048 1049 mmu->dev = &pdev->dev; 1050 spin_lock_init(&mmu->lock); 1051 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); 1052 mmu->features = of_device_get_match_data(&pdev->dev); 1053 memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs); 1054 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 1055 1056 /* Map I/O memory and request IRQ. */ 1057 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1058 mmu->base = devm_ioremap_resource(&pdev->dev, res); 1059 if (IS_ERR(mmu->base)) 1060 return PTR_ERR(mmu->base); 1061 1062 /* 1063 * The IPMMU has two register banks, for secure and non-secure modes. 1064 * The bank mapped at the beginning of the IPMMU address space 1065 * corresponds to the running mode of the CPU. When running in secure 1066 * mode the non-secure register bank is also available at an offset. 1067 * 1068 * Secure mode operation isn't clearly documented and is thus currently 1069 * not implemented in the driver. Furthermore, preliminary tests of 1070 * non-secure operation with the main register bank were not successful. 1071 * Offset the registers base unconditionally to point to the non-secure 1072 * alias space for now. 1073 */ 1074 if (mmu->features->use_ns_alias_offset) 1075 mmu->base += IM_NS_ALIAS_OFFSET; 1076 1077 mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts); 1078 1079 irq = platform_get_irq(pdev, 0); 1080 1081 /* 1082 * Determine if this IPMMU instance is a root device by checking for 1083 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. 1084 */ 1085 if (!mmu->features->has_cache_leaf_nodes || 1086 !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL)) 1087 mmu->root = mmu; 1088 else 1089 mmu->root = ipmmu_find_root(); 1090 1091 /* 1092 * Wait until the root device has been registered for sure. 1093 */ 1094 if (!mmu->root) 1095 return -EPROBE_DEFER; 1096 1097 /* Root devices have mandatory IRQs */ 1098 if (ipmmu_is_root(mmu)) { 1099 if (irq < 0) { 1100 dev_err(&pdev->dev, "no IRQ found\n"); 1101 return irq; 1102 } 1103 1104 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, 1105 dev_name(&pdev->dev), mmu); 1106 if (ret < 0) { 1107 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); 1108 return ret; 1109 } 1110 1111 ipmmu_device_reset(mmu); 1112 1113 if (mmu->features->reserved_context) { 1114 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n"); 1115 set_bit(0, mmu->ctx); 1116 } 1117 } 1118 1119 /* 1120 * Register the IPMMU to the IOMMU subsystem in the following cases: 1121 * - R-Car Gen2 IPMMU (all devices registered) 1122 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) 1123 */ 1124 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) { 1125 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, 1126 dev_name(&pdev->dev)); 1127 if (ret) 1128 return ret; 1129 1130 iommu_device_set_ops(&mmu->iommu, &ipmmu_ops); 1131 iommu_device_set_fwnode(&mmu->iommu, 1132 &pdev->dev.of_node->fwnode); 1133 1134 ret = iommu_device_register(&mmu->iommu); 1135 if (ret) 1136 return ret; 1137 1138 #if defined(CONFIG_IOMMU_DMA) 1139 if (!iommu_present(&platform_bus_type)) 1140 bus_set_iommu(&platform_bus_type, &ipmmu_ops); 1141 #endif 1142 } 1143 1144 /* 1145 * We can't create the ARM mapping here as it requires the bus to have 1146 * an IOMMU, which only happens when bus_set_iommu() is called in 1147 * ipmmu_init() after the probe function returns. 1148 */ 1149 1150 platform_set_drvdata(pdev, mmu); 1151 1152 return 0; 1153 } 1154 1155 static int ipmmu_remove(struct platform_device *pdev) 1156 { 1157 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev); 1158 1159 iommu_device_sysfs_remove(&mmu->iommu); 1160 iommu_device_unregister(&mmu->iommu); 1161 1162 arm_iommu_release_mapping(mmu->mapping); 1163 1164 ipmmu_device_reset(mmu); 1165 1166 return 0; 1167 } 1168 1169 #ifdef CONFIG_PM_SLEEP 1170 static int ipmmu_resume_noirq(struct device *dev) 1171 { 1172 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); 1173 unsigned int i; 1174 1175 /* Reset root MMU and restore contexts */ 1176 if (ipmmu_is_root(mmu)) { 1177 ipmmu_device_reset(mmu); 1178 1179 for (i = 0; i < mmu->num_ctx; i++) { 1180 if (!mmu->domains[i]) 1181 continue; 1182 1183 ipmmu_domain_setup_context(mmu->domains[i]); 1184 } 1185 } 1186 1187 /* Re-enable active micro-TLBs */ 1188 for (i = 0; i < mmu->features->num_utlbs; i++) { 1189 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID) 1190 continue; 1191 1192 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i); 1193 } 1194 1195 return 0; 1196 } 1197 1198 static const struct dev_pm_ops ipmmu_pm = { 1199 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq) 1200 }; 1201 #define DEV_PM_OPS &ipmmu_pm 1202 #else 1203 #define DEV_PM_OPS NULL 1204 #endif /* CONFIG_PM_SLEEP */ 1205 1206 static struct platform_driver ipmmu_driver = { 1207 .driver = { 1208 .name = "ipmmu-vmsa", 1209 .of_match_table = of_match_ptr(ipmmu_of_ids), 1210 .pm = DEV_PM_OPS, 1211 }, 1212 .probe = ipmmu_probe, 1213 .remove = ipmmu_remove, 1214 }; 1215 1216 static int __init ipmmu_init(void) 1217 { 1218 struct device_node *np; 1219 static bool setup_done; 1220 int ret; 1221 1222 if (setup_done) 1223 return 0; 1224 1225 np = of_find_matching_node(NULL, ipmmu_of_ids); 1226 if (!np) 1227 return 0; 1228 1229 of_node_put(np); 1230 1231 ret = platform_driver_register(&ipmmu_driver); 1232 if (ret < 0) 1233 return ret; 1234 1235 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 1236 if (!iommu_present(&platform_bus_type)) 1237 bus_set_iommu(&platform_bus_type, &ipmmu_ops); 1238 #endif 1239 1240 setup_done = true; 1241 return 0; 1242 } 1243 subsys_initcall(ipmmu_init); 1244