1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * IOMMU API for Renesas VMSA-compatible IPMMU 4 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * 6 * Copyright (C) 2014-2020 Renesas Electronics Corporation 7 */ 8 9 #include <linux/bitmap.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/export.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/io-pgtable.h> 18 #include <linux/iommu.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/sizes.h> 24 #include <linux/slab.h> 25 #include <linux/sys_soc.h> 26 27 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 28 #include <asm/dma-iommu.h> 29 #else 30 #define arm_iommu_create_mapping(...) NULL 31 #define arm_iommu_attach_device(...) -ENODEV 32 #define arm_iommu_release_mapping(...) do {} while (0) 33 #define arm_iommu_detach_device(...) do {} while (0) 34 #endif 35 36 #define IPMMU_CTX_MAX 16U 37 #define IPMMU_CTX_INVALID -1 38 39 #define IPMMU_UTLB_MAX 64U 40 41 struct ipmmu_features { 42 bool use_ns_alias_offset; 43 bool has_cache_leaf_nodes; 44 unsigned int number_of_contexts; 45 unsigned int num_utlbs; 46 bool setup_imbuscr; 47 bool twobit_imttbcr_sl0; 48 bool reserved_context; 49 bool cache_snoop; 50 unsigned int ctx_offset_base; 51 unsigned int ctx_offset_stride; 52 unsigned int utlb_offset_base; 53 }; 54 55 struct ipmmu_vmsa_device { 56 struct device *dev; 57 void __iomem *base; 58 struct iommu_device iommu; 59 struct ipmmu_vmsa_device *root; 60 const struct ipmmu_features *features; 61 unsigned int num_ctx; 62 spinlock_t lock; /* Protects ctx and domains[] */ 63 DECLARE_BITMAP(ctx, IPMMU_CTX_MAX); 64 struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; 65 s8 utlb_ctx[IPMMU_UTLB_MAX]; 66 67 struct iommu_group *group; 68 struct dma_iommu_mapping *mapping; 69 }; 70 71 struct ipmmu_vmsa_domain { 72 struct ipmmu_vmsa_device *mmu; 73 struct iommu_domain io_domain; 74 75 struct io_pgtable_cfg cfg; 76 struct io_pgtable_ops *iop; 77 78 unsigned int context_id; 79 struct mutex mutex; /* Protects mappings */ 80 }; 81 82 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom) 83 { 84 return container_of(dom, struct ipmmu_vmsa_domain, io_domain); 85 } 86 87 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) 88 { 89 return dev_iommu_priv_get(dev); 90 } 91 92 #define TLB_LOOP_TIMEOUT 100 /* 100us */ 93 94 /* ----------------------------------------------------------------------------- 95 * Registers Definition 96 */ 97 98 #define IM_NS_ALIAS_OFFSET 0x800 99 100 /* MMU "context" registers */ 101 #define IMCTR 0x0000 /* R-Car Gen2/3 */ 102 #define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */ 103 #define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */ 104 #define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */ 105 106 #define IMTTBCR 0x0008 /* R-Car Gen2/3 */ 107 #define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */ 108 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */ 109 #define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */ 110 #define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */ 111 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */ 112 #define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */ 113 114 #define IMBUSCR 0x000c /* R-Car Gen2 only */ 115 #define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */ 116 #define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */ 117 118 #define IMTTLBR0 0x0010 /* R-Car Gen2/3 */ 119 #define IMTTUBR0 0x0014 /* R-Car Gen2/3 */ 120 121 #define IMSTR 0x0020 /* R-Car Gen2/3 */ 122 #define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */ 123 #define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */ 124 #define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */ 125 #define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */ 126 127 #define IMMAIR0 0x0028 /* R-Car Gen2/3 */ 128 129 #define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */ 130 #define IMEUAR 0x0034 /* R-Car Gen3 only */ 131 132 /* uTLB registers */ 133 #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n)) 134 #define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */ 135 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */ 136 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */ 137 #define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */ 138 #define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */ 139 140 #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n)) 141 #define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */ 142 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */ 143 144 /* ----------------------------------------------------------------------------- 145 * Root device handling 146 */ 147 148 static struct platform_driver ipmmu_driver; 149 150 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu) 151 { 152 return mmu->root == mmu; 153 } 154 155 static int __ipmmu_check_device(struct device *dev, void *data) 156 { 157 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); 158 struct ipmmu_vmsa_device **rootp = data; 159 160 if (ipmmu_is_root(mmu)) 161 *rootp = mmu; 162 163 return 0; 164 } 165 166 static struct ipmmu_vmsa_device *ipmmu_find_root(void) 167 { 168 struct ipmmu_vmsa_device *root = NULL; 169 170 return driver_for_each_device(&ipmmu_driver.driver, NULL, &root, 171 __ipmmu_check_device) == 0 ? root : NULL; 172 } 173 174 /* ----------------------------------------------------------------------------- 175 * Read/Write Access 176 */ 177 178 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset) 179 { 180 return ioread32(mmu->base + offset); 181 } 182 183 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset, 184 u32 data) 185 { 186 iowrite32(data, mmu->base + offset); 187 } 188 189 static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu, 190 unsigned int context_id, unsigned int reg) 191 { 192 unsigned int base = mmu->features->ctx_offset_base; 193 194 if (context_id > 7) 195 base += 0x800 - 8 * 0x40; 196 197 return base + context_id * mmu->features->ctx_offset_stride + reg; 198 } 199 200 static u32 ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu, 201 unsigned int context_id, unsigned int reg) 202 { 203 return ipmmu_read(mmu, ipmmu_ctx_reg(mmu, context_id, reg)); 204 } 205 206 static void ipmmu_ctx_write(struct ipmmu_vmsa_device *mmu, 207 unsigned int context_id, unsigned int reg, u32 data) 208 { 209 ipmmu_write(mmu, ipmmu_ctx_reg(mmu, context_id, reg), data); 210 } 211 212 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain, 213 unsigned int reg) 214 { 215 return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg); 216 } 217 218 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain, 219 unsigned int reg, u32 data) 220 { 221 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); 222 } 223 224 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain, 225 unsigned int reg, u32 data) 226 { 227 if (domain->mmu != domain->mmu->root) 228 ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data); 229 230 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); 231 } 232 233 static u32 ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, unsigned int reg) 234 { 235 return mmu->features->utlb_offset_base + reg; 236 } 237 238 static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu, 239 unsigned int utlb, u32 data) 240 { 241 ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)), data); 242 } 243 244 static void ipmmu_imuctr_write(struct ipmmu_vmsa_device *mmu, 245 unsigned int utlb, u32 data) 246 { 247 ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUCTR(utlb)), data); 248 } 249 250 /* ----------------------------------------------------------------------------- 251 * TLB and microTLB Management 252 */ 253 254 /* Wait for any pending TLB invalidations to complete */ 255 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain) 256 { 257 unsigned int count = 0; 258 259 while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) { 260 cpu_relax(); 261 if (++count == TLB_LOOP_TIMEOUT) { 262 dev_err_ratelimited(domain->mmu->dev, 263 "TLB sync timed out -- MMU may be deadlocked\n"); 264 return; 265 } 266 udelay(1); 267 } 268 } 269 270 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain) 271 { 272 u32 reg; 273 274 reg = ipmmu_ctx_read_root(domain, IMCTR); 275 reg |= IMCTR_FLUSH; 276 ipmmu_ctx_write_all(domain, IMCTR, reg); 277 278 ipmmu_tlb_sync(domain); 279 } 280 281 /* 282 * Enable MMU translation for the microTLB. 283 */ 284 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, 285 unsigned int utlb) 286 { 287 struct ipmmu_vmsa_device *mmu = domain->mmu; 288 289 /* 290 * TODO: Reference-count the microTLB as several bus masters can be 291 * connected to the same microTLB. 292 */ 293 294 /* TODO: What should we set the ASID to ? */ 295 ipmmu_imuasid_write(mmu, utlb, 0); 296 /* TODO: Do we need to flush the microTLB ? */ 297 ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) | 298 IMUCTR_FLUSH | IMUCTR_MMUEN); 299 mmu->utlb_ctx[utlb] = domain->context_id; 300 } 301 302 /* 303 * Disable MMU translation for the microTLB. 304 */ 305 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, 306 unsigned int utlb) 307 { 308 struct ipmmu_vmsa_device *mmu = domain->mmu; 309 310 ipmmu_imuctr_write(mmu, utlb, 0); 311 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; 312 } 313 314 static void ipmmu_tlb_flush_all(void *cookie) 315 { 316 struct ipmmu_vmsa_domain *domain = cookie; 317 318 ipmmu_tlb_invalidate(domain); 319 } 320 321 static void ipmmu_tlb_flush(unsigned long iova, size_t size, 322 size_t granule, void *cookie) 323 { 324 ipmmu_tlb_flush_all(cookie); 325 } 326 327 static const struct iommu_flush_ops ipmmu_flush_ops = { 328 .tlb_flush_all = ipmmu_tlb_flush_all, 329 .tlb_flush_walk = ipmmu_tlb_flush, 330 }; 331 332 /* ----------------------------------------------------------------------------- 333 * Domain/Context Management 334 */ 335 336 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu, 337 struct ipmmu_vmsa_domain *domain) 338 { 339 unsigned long flags; 340 int ret; 341 342 spin_lock_irqsave(&mmu->lock, flags); 343 344 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); 345 if (ret != mmu->num_ctx) { 346 mmu->domains[ret] = domain; 347 set_bit(ret, mmu->ctx); 348 } else 349 ret = -EBUSY; 350 351 spin_unlock_irqrestore(&mmu->lock, flags); 352 353 return ret; 354 } 355 356 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu, 357 unsigned int context_id) 358 { 359 unsigned long flags; 360 361 spin_lock_irqsave(&mmu->lock, flags); 362 363 clear_bit(context_id, mmu->ctx); 364 mmu->domains[context_id] = NULL; 365 366 spin_unlock_irqrestore(&mmu->lock, flags); 367 } 368 369 static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) 370 { 371 u64 ttbr; 372 u32 tmp; 373 374 /* TTBR0 */ 375 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; 376 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); 377 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); 378 379 /* 380 * TTBCR 381 * We use long descriptors and allocate the whole 32-bit VA space to 382 * TTBR0. 383 */ 384 if (domain->mmu->features->twobit_imttbcr_sl0) 385 tmp = IMTTBCR_SL0_TWOBIT_LVL_1; 386 else 387 tmp = IMTTBCR_SL0_LVL_1; 388 389 if (domain->mmu->features->cache_snoop) 390 tmp |= IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | 391 IMTTBCR_IRGN0_WB_WA; 392 393 ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | tmp); 394 395 /* MAIR0 */ 396 ipmmu_ctx_write_root(domain, IMMAIR0, 397 domain->cfg.arm_lpae_s1_cfg.mair); 398 399 /* IMBUSCR */ 400 if (domain->mmu->features->setup_imbuscr) 401 ipmmu_ctx_write_root(domain, IMBUSCR, 402 ipmmu_ctx_read_root(domain, IMBUSCR) & 403 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK)); 404 405 /* 406 * IMSTR 407 * Clear all interrupt flags. 408 */ 409 ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR)); 410 411 /* 412 * IMCTR 413 * Enable the MMU and interrupt generation. The long-descriptor 414 * translation table format doesn't use TEX remapping. Don't enable AF 415 * software management as we have no use for it. Flush the TLB as 416 * required when modifying the context registers. 417 */ 418 ipmmu_ctx_write_all(domain, IMCTR, 419 IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN); 420 } 421 422 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) 423 { 424 int ret; 425 426 /* 427 * Allocate the page table operations. 428 * 429 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory 430 * access, Long-descriptor format" that the NStable bit being set in a 431 * table descriptor will result in the NStable and NS bits of all child 432 * entries being ignored and considered as being set. The IPMMU seems 433 * not to comply with this, as it generates a secure access page fault 434 * if any of the NStable and NS bits isn't set when running in 435 * non-secure mode. 436 */ 437 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; 438 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; 439 domain->cfg.ias = 32; 440 domain->cfg.oas = 40; 441 domain->cfg.tlb = &ipmmu_flush_ops; 442 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); 443 domain->io_domain.geometry.force_aperture = true; 444 /* 445 * TODO: Add support for coherent walk through CCI with DVM and remove 446 * cache handling. For now, delegate it to the io-pgtable code. 447 */ 448 domain->cfg.coherent_walk = false; 449 domain->cfg.iommu_dev = domain->mmu->root->dev; 450 451 /* 452 * Find an unused context. 453 */ 454 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); 455 if (ret < 0) 456 return ret; 457 458 domain->context_id = ret; 459 460 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, 461 domain); 462 if (!domain->iop) { 463 ipmmu_domain_free_context(domain->mmu->root, 464 domain->context_id); 465 return -EINVAL; 466 } 467 468 ipmmu_domain_setup_context(domain); 469 return 0; 470 } 471 472 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain) 473 { 474 if (!domain->mmu) 475 return; 476 477 /* 478 * Disable the context. Flush the TLB as required when modifying the 479 * context registers. 480 * 481 * TODO: Is TLB flush really needed ? 482 */ 483 ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH); 484 ipmmu_tlb_sync(domain); 485 ipmmu_domain_free_context(domain->mmu->root, domain->context_id); 486 } 487 488 /* ----------------------------------------------------------------------------- 489 * Fault Handling 490 */ 491 492 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain) 493 { 494 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF; 495 struct ipmmu_vmsa_device *mmu = domain->mmu; 496 unsigned long iova; 497 u32 status; 498 499 status = ipmmu_ctx_read_root(domain, IMSTR); 500 if (!(status & err_mask)) 501 return IRQ_NONE; 502 503 iova = ipmmu_ctx_read_root(domain, IMELAR); 504 if (IS_ENABLED(CONFIG_64BIT)) 505 iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32; 506 507 /* 508 * Clear the error status flags. Unlike traditional interrupt flag 509 * registers that must be cleared by writing 1, this status register 510 * seems to require 0. The error address register must be read before, 511 * otherwise its value will be 0. 512 */ 513 ipmmu_ctx_write_root(domain, IMSTR, 0); 514 515 /* Log fatal errors. */ 516 if (status & IMSTR_MHIT) 517 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n", 518 iova); 519 if (status & IMSTR_ABORT) 520 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n", 521 iova); 522 523 if (!(status & (IMSTR_PF | IMSTR_TF))) 524 return IRQ_NONE; 525 526 /* 527 * Try to handle page faults and translation faults. 528 * 529 * TODO: We need to look up the faulty device based on the I/O VA. Use 530 * the IOMMU device for now. 531 */ 532 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) 533 return IRQ_HANDLED; 534 535 dev_err_ratelimited(mmu->dev, 536 "Unhandled fault: status 0x%08x iova 0x%lx\n", 537 status, iova); 538 539 return IRQ_HANDLED; 540 } 541 542 static irqreturn_t ipmmu_irq(int irq, void *dev) 543 { 544 struct ipmmu_vmsa_device *mmu = dev; 545 irqreturn_t status = IRQ_NONE; 546 unsigned int i; 547 unsigned long flags; 548 549 spin_lock_irqsave(&mmu->lock, flags); 550 551 /* 552 * Check interrupts for all active contexts. 553 */ 554 for (i = 0; i < mmu->num_ctx; i++) { 555 if (!mmu->domains[i]) 556 continue; 557 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) 558 status = IRQ_HANDLED; 559 } 560 561 spin_unlock_irqrestore(&mmu->lock, flags); 562 563 return status; 564 } 565 566 /* ----------------------------------------------------------------------------- 567 * IOMMU Operations 568 */ 569 570 static struct iommu_domain *ipmmu_domain_alloc(unsigned type) 571 { 572 struct ipmmu_vmsa_domain *domain; 573 574 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) 575 return NULL; 576 577 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 578 if (!domain) 579 return NULL; 580 581 mutex_init(&domain->mutex); 582 583 return &domain->io_domain; 584 } 585 586 static void ipmmu_domain_free(struct iommu_domain *io_domain) 587 { 588 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 589 590 /* 591 * Free the domain resources. We assume that all devices have already 592 * been detached. 593 */ 594 ipmmu_domain_destroy_context(domain); 595 free_io_pgtable_ops(domain->iop); 596 kfree(domain); 597 } 598 599 static int ipmmu_attach_device(struct iommu_domain *io_domain, 600 struct device *dev) 601 { 602 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 603 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 604 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 605 unsigned int i; 606 int ret = 0; 607 608 if (!mmu) { 609 dev_err(dev, "Cannot attach to IPMMU\n"); 610 return -ENXIO; 611 } 612 613 mutex_lock(&domain->mutex); 614 615 if (!domain->mmu) { 616 /* The domain hasn't been used yet, initialize it. */ 617 domain->mmu = mmu; 618 ret = ipmmu_domain_init_context(domain); 619 if (ret < 0) { 620 dev_err(dev, "Unable to initialize IPMMU context\n"); 621 domain->mmu = NULL; 622 } else { 623 dev_info(dev, "Using IPMMU context %u\n", 624 domain->context_id); 625 } 626 } else if (domain->mmu != mmu) { 627 /* 628 * Something is wrong, we can't attach two devices using 629 * different IOMMUs to the same domain. 630 */ 631 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n", 632 dev_name(mmu->dev), dev_name(domain->mmu->dev)); 633 ret = -EINVAL; 634 } else 635 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); 636 637 mutex_unlock(&domain->mutex); 638 639 if (ret < 0) 640 return ret; 641 642 for (i = 0; i < fwspec->num_ids; ++i) 643 ipmmu_utlb_enable(domain, fwspec->ids[i]); 644 645 return 0; 646 } 647 648 static void ipmmu_detach_device(struct iommu_domain *io_domain, 649 struct device *dev) 650 { 651 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 652 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 653 unsigned int i; 654 655 for (i = 0; i < fwspec->num_ids; ++i) 656 ipmmu_utlb_disable(domain, fwspec->ids[i]); 657 658 /* 659 * TODO: Optimize by disabling the context when no device is attached. 660 */ 661 } 662 663 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova, 664 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 665 { 666 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 667 668 if (!domain) 669 return -ENODEV; 670 671 return domain->iop->map(domain->iop, iova, paddr, size, prot, gfp); 672 } 673 674 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova, 675 size_t size, struct iommu_iotlb_gather *gather) 676 { 677 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 678 679 return domain->iop->unmap(domain->iop, iova, size, gather); 680 } 681 682 static void ipmmu_flush_iotlb_all(struct iommu_domain *io_domain) 683 { 684 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 685 686 if (domain->mmu) 687 ipmmu_tlb_flush_all(domain); 688 } 689 690 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain, 691 struct iommu_iotlb_gather *gather) 692 { 693 ipmmu_flush_iotlb_all(io_domain); 694 } 695 696 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain, 697 dma_addr_t iova) 698 { 699 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 700 701 /* TODO: Is locking needed ? */ 702 703 return domain->iop->iova_to_phys(domain->iop, iova); 704 } 705 706 static int ipmmu_init_platform_device(struct device *dev, 707 struct of_phandle_args *args) 708 { 709 struct platform_device *ipmmu_pdev; 710 711 ipmmu_pdev = of_find_device_by_node(args->np); 712 if (!ipmmu_pdev) 713 return -ENODEV; 714 715 dev_iommu_priv_set(dev, platform_get_drvdata(ipmmu_pdev)); 716 717 return 0; 718 } 719 720 static const struct soc_device_attribute soc_needs_opt_in[] = { 721 { .family = "R-Car Gen3", }, 722 { .family = "RZ/G2", }, 723 { /* sentinel */ } 724 }; 725 726 static const struct soc_device_attribute soc_denylist[] = { 727 { .soc_id = "r8a774a1", }, 728 { .soc_id = "r8a7795", .revision = "ES1.*" }, 729 { .soc_id = "r8a7795", .revision = "ES2.*" }, 730 { .soc_id = "r8a7796", }, 731 { /* sentinel */ } 732 }; 733 734 static const char * const devices_allowlist[] = { 735 "ee100000.mmc", 736 "ee120000.mmc", 737 "ee140000.mmc", 738 "ee160000.mmc" 739 }; 740 741 static bool ipmmu_device_is_allowed(struct device *dev) 742 { 743 unsigned int i; 744 745 /* 746 * R-Car Gen3 and RZ/G2 use the allow list to opt-in devices. 747 * For Other SoCs, this returns true anyway. 748 */ 749 if (!soc_device_match(soc_needs_opt_in)) 750 return true; 751 752 /* Check whether this SoC can use the IPMMU correctly or not */ 753 if (soc_device_match(soc_denylist)) 754 return false; 755 756 /* Check whether this device can work with the IPMMU */ 757 for (i = 0; i < ARRAY_SIZE(devices_allowlist); i++) { 758 if (!strcmp(dev_name(dev), devices_allowlist[i])) 759 return true; 760 } 761 762 /* Otherwise, do not allow use of IPMMU */ 763 return false; 764 } 765 766 static int ipmmu_of_xlate(struct device *dev, 767 struct of_phandle_args *spec) 768 { 769 if (!ipmmu_device_is_allowed(dev)) 770 return -ENODEV; 771 772 iommu_fwspec_add_ids(dev, spec->args, 1); 773 774 /* Initialize once - xlate() will call multiple times */ 775 if (to_ipmmu(dev)) 776 return 0; 777 778 return ipmmu_init_platform_device(dev, spec); 779 } 780 781 static int ipmmu_init_arm_mapping(struct device *dev) 782 { 783 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 784 int ret; 785 786 /* 787 * Create the ARM mapping, used by the ARM DMA mapping core to allocate 788 * VAs. This will allocate a corresponding IOMMU domain. 789 * 790 * TODO: 791 * - Create one mapping per context (TLB). 792 * - Make the mapping size configurable ? We currently use a 2GB mapping 793 * at a 1GB offset to ensure that NULL VAs will fault. 794 */ 795 if (!mmu->mapping) { 796 struct dma_iommu_mapping *mapping; 797 798 mapping = arm_iommu_create_mapping(&platform_bus_type, 799 SZ_1G, SZ_2G); 800 if (IS_ERR(mapping)) { 801 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); 802 ret = PTR_ERR(mapping); 803 goto error; 804 } 805 806 mmu->mapping = mapping; 807 } 808 809 /* Attach the ARM VA mapping to the device. */ 810 ret = arm_iommu_attach_device(dev, mmu->mapping); 811 if (ret < 0) { 812 dev_err(dev, "Failed to attach device to VA mapping\n"); 813 goto error; 814 } 815 816 return 0; 817 818 error: 819 if (mmu->mapping) 820 arm_iommu_release_mapping(mmu->mapping); 821 822 return ret; 823 } 824 825 static struct iommu_device *ipmmu_probe_device(struct device *dev) 826 { 827 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 828 829 /* 830 * Only let through devices that have been verified in xlate() 831 */ 832 if (!mmu) 833 return ERR_PTR(-ENODEV); 834 835 return &mmu->iommu; 836 } 837 838 static void ipmmu_probe_finalize(struct device *dev) 839 { 840 int ret = 0; 841 842 if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)) 843 ret = ipmmu_init_arm_mapping(dev); 844 845 if (ret) 846 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); 847 } 848 849 static void ipmmu_release_device(struct device *dev) 850 { 851 arm_iommu_detach_device(dev); 852 } 853 854 static struct iommu_group *ipmmu_find_group(struct device *dev) 855 { 856 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 857 struct iommu_group *group; 858 859 if (mmu->group) 860 return iommu_group_ref_get(mmu->group); 861 862 group = iommu_group_alloc(); 863 if (!IS_ERR(group)) 864 mmu->group = group; 865 866 return group; 867 } 868 869 static const struct iommu_ops ipmmu_ops = { 870 .domain_alloc = ipmmu_domain_alloc, 871 .domain_free = ipmmu_domain_free, 872 .attach_dev = ipmmu_attach_device, 873 .detach_dev = ipmmu_detach_device, 874 .map = ipmmu_map, 875 .unmap = ipmmu_unmap, 876 .flush_iotlb_all = ipmmu_flush_iotlb_all, 877 .iotlb_sync = ipmmu_iotlb_sync, 878 .iova_to_phys = ipmmu_iova_to_phys, 879 .probe_device = ipmmu_probe_device, 880 .release_device = ipmmu_release_device, 881 .probe_finalize = ipmmu_probe_finalize, 882 .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA) 883 ? generic_device_group : ipmmu_find_group, 884 .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, 885 .of_xlate = ipmmu_of_xlate, 886 }; 887 888 /* ----------------------------------------------------------------------------- 889 * Probe/remove and init 890 */ 891 892 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) 893 { 894 unsigned int i; 895 896 /* Disable all contexts. */ 897 for (i = 0; i < mmu->num_ctx; ++i) 898 ipmmu_ctx_write(mmu, i, IMCTR, 0); 899 } 900 901 static const struct ipmmu_features ipmmu_features_default = { 902 .use_ns_alias_offset = true, 903 .has_cache_leaf_nodes = false, 904 .number_of_contexts = 1, /* software only tested with one context */ 905 .num_utlbs = 32, 906 .setup_imbuscr = true, 907 .twobit_imttbcr_sl0 = false, 908 .reserved_context = false, 909 .cache_snoop = true, 910 .ctx_offset_base = 0, 911 .ctx_offset_stride = 0x40, 912 .utlb_offset_base = 0, 913 }; 914 915 static const struct ipmmu_features ipmmu_features_rcar_gen3 = { 916 .use_ns_alias_offset = false, 917 .has_cache_leaf_nodes = true, 918 .number_of_contexts = 8, 919 .num_utlbs = 48, 920 .setup_imbuscr = false, 921 .twobit_imttbcr_sl0 = true, 922 .reserved_context = true, 923 .cache_snoop = false, 924 .ctx_offset_base = 0, 925 .ctx_offset_stride = 0x40, 926 .utlb_offset_base = 0, 927 }; 928 929 static const struct ipmmu_features ipmmu_features_r8a779a0 = { 930 .use_ns_alias_offset = false, 931 .has_cache_leaf_nodes = true, 932 .number_of_contexts = 16, 933 .num_utlbs = 64, 934 .setup_imbuscr = false, 935 .twobit_imttbcr_sl0 = true, 936 .reserved_context = true, 937 .cache_snoop = false, 938 .ctx_offset_base = 0x10000, 939 .ctx_offset_stride = 0x1040, 940 .utlb_offset_base = 0x3000, 941 }; 942 943 static const struct of_device_id ipmmu_of_ids[] = { 944 { 945 .compatible = "renesas,ipmmu-vmsa", 946 .data = &ipmmu_features_default, 947 }, { 948 .compatible = "renesas,ipmmu-r8a774a1", 949 .data = &ipmmu_features_rcar_gen3, 950 }, { 951 .compatible = "renesas,ipmmu-r8a774b1", 952 .data = &ipmmu_features_rcar_gen3, 953 }, { 954 .compatible = "renesas,ipmmu-r8a774c0", 955 .data = &ipmmu_features_rcar_gen3, 956 }, { 957 .compatible = "renesas,ipmmu-r8a774e1", 958 .data = &ipmmu_features_rcar_gen3, 959 }, { 960 .compatible = "renesas,ipmmu-r8a7795", 961 .data = &ipmmu_features_rcar_gen3, 962 }, { 963 .compatible = "renesas,ipmmu-r8a7796", 964 .data = &ipmmu_features_rcar_gen3, 965 }, { 966 .compatible = "renesas,ipmmu-r8a77961", 967 .data = &ipmmu_features_rcar_gen3, 968 }, { 969 .compatible = "renesas,ipmmu-r8a77965", 970 .data = &ipmmu_features_rcar_gen3, 971 }, { 972 .compatible = "renesas,ipmmu-r8a77970", 973 .data = &ipmmu_features_rcar_gen3, 974 }, { 975 .compatible = "renesas,ipmmu-r8a77980", 976 .data = &ipmmu_features_rcar_gen3, 977 }, { 978 .compatible = "renesas,ipmmu-r8a77990", 979 .data = &ipmmu_features_rcar_gen3, 980 }, { 981 .compatible = "renesas,ipmmu-r8a77995", 982 .data = &ipmmu_features_rcar_gen3, 983 }, { 984 .compatible = "renesas,ipmmu-r8a779a0", 985 .data = &ipmmu_features_r8a779a0, 986 }, { 987 /* Terminator */ 988 }, 989 }; 990 991 static int ipmmu_probe(struct platform_device *pdev) 992 { 993 struct ipmmu_vmsa_device *mmu; 994 struct resource *res; 995 int irq; 996 int ret; 997 998 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); 999 if (!mmu) { 1000 dev_err(&pdev->dev, "cannot allocate device data\n"); 1001 return -ENOMEM; 1002 } 1003 1004 mmu->dev = &pdev->dev; 1005 spin_lock_init(&mmu->lock); 1006 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); 1007 mmu->features = of_device_get_match_data(&pdev->dev); 1008 memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs); 1009 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 1010 1011 /* Map I/O memory and request IRQ. */ 1012 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1013 mmu->base = devm_ioremap_resource(&pdev->dev, res); 1014 if (IS_ERR(mmu->base)) 1015 return PTR_ERR(mmu->base); 1016 1017 /* 1018 * The IPMMU has two register banks, for secure and non-secure modes. 1019 * The bank mapped at the beginning of the IPMMU address space 1020 * corresponds to the running mode of the CPU. When running in secure 1021 * mode the non-secure register bank is also available at an offset. 1022 * 1023 * Secure mode operation isn't clearly documented and is thus currently 1024 * not implemented in the driver. Furthermore, preliminary tests of 1025 * non-secure operation with the main register bank were not successful. 1026 * Offset the registers base unconditionally to point to the non-secure 1027 * alias space for now. 1028 */ 1029 if (mmu->features->use_ns_alias_offset) 1030 mmu->base += IM_NS_ALIAS_OFFSET; 1031 1032 mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts); 1033 1034 /* 1035 * Determine if this IPMMU instance is a root device by checking for 1036 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. 1037 */ 1038 if (!mmu->features->has_cache_leaf_nodes || 1039 !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL)) 1040 mmu->root = mmu; 1041 else 1042 mmu->root = ipmmu_find_root(); 1043 1044 /* 1045 * Wait until the root device has been registered for sure. 1046 */ 1047 if (!mmu->root) 1048 return -EPROBE_DEFER; 1049 1050 /* Root devices have mandatory IRQs */ 1051 if (ipmmu_is_root(mmu)) { 1052 irq = platform_get_irq(pdev, 0); 1053 if (irq < 0) 1054 return irq; 1055 1056 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, 1057 dev_name(&pdev->dev), mmu); 1058 if (ret < 0) { 1059 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); 1060 return ret; 1061 } 1062 1063 ipmmu_device_reset(mmu); 1064 1065 if (mmu->features->reserved_context) { 1066 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n"); 1067 set_bit(0, mmu->ctx); 1068 } 1069 } 1070 1071 /* 1072 * Register the IPMMU to the IOMMU subsystem in the following cases: 1073 * - R-Car Gen2 IPMMU (all devices registered) 1074 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) 1075 */ 1076 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) { 1077 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, 1078 dev_name(&pdev->dev)); 1079 if (ret) 1080 return ret; 1081 1082 ret = iommu_device_register(&mmu->iommu, &ipmmu_ops, &pdev->dev); 1083 if (ret) 1084 return ret; 1085 1086 #if defined(CONFIG_IOMMU_DMA) 1087 if (!iommu_present(&platform_bus_type)) 1088 bus_set_iommu(&platform_bus_type, &ipmmu_ops); 1089 #endif 1090 } 1091 1092 /* 1093 * We can't create the ARM mapping here as it requires the bus to have 1094 * an IOMMU, which only happens when bus_set_iommu() is called in 1095 * ipmmu_init() after the probe function returns. 1096 */ 1097 1098 platform_set_drvdata(pdev, mmu); 1099 1100 return 0; 1101 } 1102 1103 static int ipmmu_remove(struct platform_device *pdev) 1104 { 1105 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev); 1106 1107 iommu_device_sysfs_remove(&mmu->iommu); 1108 iommu_device_unregister(&mmu->iommu); 1109 1110 arm_iommu_release_mapping(mmu->mapping); 1111 1112 ipmmu_device_reset(mmu); 1113 1114 return 0; 1115 } 1116 1117 #ifdef CONFIG_PM_SLEEP 1118 static int ipmmu_resume_noirq(struct device *dev) 1119 { 1120 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); 1121 unsigned int i; 1122 1123 /* Reset root MMU and restore contexts */ 1124 if (ipmmu_is_root(mmu)) { 1125 ipmmu_device_reset(mmu); 1126 1127 for (i = 0; i < mmu->num_ctx; i++) { 1128 if (!mmu->domains[i]) 1129 continue; 1130 1131 ipmmu_domain_setup_context(mmu->domains[i]); 1132 } 1133 } 1134 1135 /* Re-enable active micro-TLBs */ 1136 for (i = 0; i < mmu->features->num_utlbs; i++) { 1137 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID) 1138 continue; 1139 1140 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i); 1141 } 1142 1143 return 0; 1144 } 1145 1146 static const struct dev_pm_ops ipmmu_pm = { 1147 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq) 1148 }; 1149 #define DEV_PM_OPS &ipmmu_pm 1150 #else 1151 #define DEV_PM_OPS NULL 1152 #endif /* CONFIG_PM_SLEEP */ 1153 1154 static struct platform_driver ipmmu_driver = { 1155 .driver = { 1156 .name = "ipmmu-vmsa", 1157 .of_match_table = of_match_ptr(ipmmu_of_ids), 1158 .pm = DEV_PM_OPS, 1159 }, 1160 .probe = ipmmu_probe, 1161 .remove = ipmmu_remove, 1162 }; 1163 1164 static int __init ipmmu_init(void) 1165 { 1166 struct device_node *np; 1167 static bool setup_done; 1168 int ret; 1169 1170 if (setup_done) 1171 return 0; 1172 1173 np = of_find_matching_node(NULL, ipmmu_of_ids); 1174 if (!np) 1175 return 0; 1176 1177 of_node_put(np); 1178 1179 ret = platform_driver_register(&ipmmu_driver); 1180 if (ret < 0) 1181 return ret; 1182 1183 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 1184 if (!iommu_present(&platform_bus_type)) 1185 bus_set_iommu(&platform_bus_type, &ipmmu_ops); 1186 #endif 1187 1188 setup_done = true; 1189 return 0; 1190 } 1191 subsys_initcall(ipmmu_init); 1192