1 /* 2 * IPMMU VMSA 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 */ 10 11 #include <linux/bitmap.h> 12 #include <linux/delay.h> 13 #include <linux/dma-iommu.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/export.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iommu.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_iommu.h> 24 #include <linux/of_platform.h> 25 #include <linux/platform_device.h> 26 #include <linux/sizes.h> 27 #include <linux/slab.h> 28 #include <linux/sys_soc.h> 29 30 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 31 #include <asm/dma-iommu.h> 32 #include <asm/pgalloc.h> 33 #else 34 #define arm_iommu_create_mapping(...) NULL 35 #define arm_iommu_attach_device(...) -ENODEV 36 #define arm_iommu_release_mapping(...) do {} while (0) 37 #define arm_iommu_detach_device(...) do {} while (0) 38 #endif 39 40 #include "io-pgtable.h" 41 42 #define IPMMU_CTX_MAX 8 43 44 struct ipmmu_features { 45 bool use_ns_alias_offset; 46 bool has_cache_leaf_nodes; 47 unsigned int number_of_contexts; 48 bool setup_imbuscr; 49 bool twobit_imttbcr_sl0; 50 }; 51 52 struct ipmmu_vmsa_device { 53 struct device *dev; 54 void __iomem *base; 55 struct iommu_device iommu; 56 struct ipmmu_vmsa_device *root; 57 const struct ipmmu_features *features; 58 unsigned int num_utlbs; 59 unsigned int num_ctx; 60 spinlock_t lock; /* Protects ctx and domains[] */ 61 DECLARE_BITMAP(ctx, IPMMU_CTX_MAX); 62 struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; 63 64 struct iommu_group *group; 65 struct dma_iommu_mapping *mapping; 66 }; 67 68 struct ipmmu_vmsa_domain { 69 struct ipmmu_vmsa_device *mmu; 70 struct iommu_domain io_domain; 71 72 struct io_pgtable_cfg cfg; 73 struct io_pgtable_ops *iop; 74 75 unsigned int context_id; 76 spinlock_t lock; /* Protects mappings */ 77 }; 78 79 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom) 80 { 81 return container_of(dom, struct ipmmu_vmsa_domain, io_domain); 82 } 83 84 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) 85 { 86 return dev->iommu_fwspec ? dev->iommu_fwspec->iommu_priv : NULL; 87 } 88 89 #define TLB_LOOP_TIMEOUT 100 /* 100us */ 90 91 /* ----------------------------------------------------------------------------- 92 * Registers Definition 93 */ 94 95 #define IM_NS_ALIAS_OFFSET 0x800 96 97 #define IM_CTX_SIZE 0x40 98 99 #define IMCTR 0x0000 100 #define IMCTR_TRE (1 << 17) 101 #define IMCTR_AFE (1 << 16) 102 #define IMCTR_RTSEL_MASK (3 << 4) 103 #define IMCTR_RTSEL_SHIFT 4 104 #define IMCTR_TREN (1 << 3) 105 #define IMCTR_INTEN (1 << 2) 106 #define IMCTR_FLUSH (1 << 1) 107 #define IMCTR_MMUEN (1 << 0) 108 109 #define IMCAAR 0x0004 110 111 #define IMTTBCR 0x0008 112 #define IMTTBCR_EAE (1 << 31) 113 #define IMTTBCR_PMB (1 << 30) 114 #define IMTTBCR_SH1_NON_SHAREABLE (0 << 28) 115 #define IMTTBCR_SH1_OUTER_SHAREABLE (2 << 28) 116 #define IMTTBCR_SH1_INNER_SHAREABLE (3 << 28) 117 #define IMTTBCR_SH1_MASK (3 << 28) 118 #define IMTTBCR_ORGN1_NC (0 << 26) 119 #define IMTTBCR_ORGN1_WB_WA (1 << 26) 120 #define IMTTBCR_ORGN1_WT (2 << 26) 121 #define IMTTBCR_ORGN1_WB (3 << 26) 122 #define IMTTBCR_ORGN1_MASK (3 << 26) 123 #define IMTTBCR_IRGN1_NC (0 << 24) 124 #define IMTTBCR_IRGN1_WB_WA (1 << 24) 125 #define IMTTBCR_IRGN1_WT (2 << 24) 126 #define IMTTBCR_IRGN1_WB (3 << 24) 127 #define IMTTBCR_IRGN1_MASK (3 << 24) 128 #define IMTTBCR_TSZ1_MASK (7 << 16) 129 #define IMTTBCR_TSZ1_SHIFT 16 130 #define IMTTBCR_SH0_NON_SHAREABLE (0 << 12) 131 #define IMTTBCR_SH0_OUTER_SHAREABLE (2 << 12) 132 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) 133 #define IMTTBCR_SH0_MASK (3 << 12) 134 #define IMTTBCR_ORGN0_NC (0 << 10) 135 #define IMTTBCR_ORGN0_WB_WA (1 << 10) 136 #define IMTTBCR_ORGN0_WT (2 << 10) 137 #define IMTTBCR_ORGN0_WB (3 << 10) 138 #define IMTTBCR_ORGN0_MASK (3 << 10) 139 #define IMTTBCR_IRGN0_NC (0 << 8) 140 #define IMTTBCR_IRGN0_WB_WA (1 << 8) 141 #define IMTTBCR_IRGN0_WT (2 << 8) 142 #define IMTTBCR_IRGN0_WB (3 << 8) 143 #define IMTTBCR_IRGN0_MASK (3 << 8) 144 #define IMTTBCR_SL0_LVL_2 (0 << 4) 145 #define IMTTBCR_SL0_LVL_1 (1 << 4) 146 #define IMTTBCR_TSZ0_MASK (7 << 0) 147 #define IMTTBCR_TSZ0_SHIFT O 148 149 #define IMTTBCR_SL0_TWOBIT_LVL_3 (0 << 6) 150 #define IMTTBCR_SL0_TWOBIT_LVL_2 (1 << 6) 151 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) 152 153 #define IMBUSCR 0x000c 154 #define IMBUSCR_DVM (1 << 2) 155 #define IMBUSCR_BUSSEL_SYS (0 << 0) 156 #define IMBUSCR_BUSSEL_CCI (1 << 0) 157 #define IMBUSCR_BUSSEL_IMCAAR (2 << 0) 158 #define IMBUSCR_BUSSEL_CCI_IMCAAR (3 << 0) 159 #define IMBUSCR_BUSSEL_MASK (3 << 0) 160 161 #define IMTTLBR0 0x0010 162 #define IMTTUBR0 0x0014 163 #define IMTTLBR1 0x0018 164 #define IMTTUBR1 0x001c 165 166 #define IMSTR 0x0020 167 #define IMSTR_ERRLVL_MASK (3 << 12) 168 #define IMSTR_ERRLVL_SHIFT 12 169 #define IMSTR_ERRCODE_TLB_FORMAT (1 << 8) 170 #define IMSTR_ERRCODE_ACCESS_PERM (4 << 8) 171 #define IMSTR_ERRCODE_SECURE_ACCESS (5 << 8) 172 #define IMSTR_ERRCODE_MASK (7 << 8) 173 #define IMSTR_MHIT (1 << 4) 174 #define IMSTR_ABORT (1 << 2) 175 #define IMSTR_PF (1 << 1) 176 #define IMSTR_TF (1 << 0) 177 178 #define IMMAIR0 0x0028 179 #define IMMAIR1 0x002c 180 #define IMMAIR_ATTR_MASK 0xff 181 #define IMMAIR_ATTR_DEVICE 0x04 182 #define IMMAIR_ATTR_NC 0x44 183 #define IMMAIR_ATTR_WBRWA 0xff 184 #define IMMAIR_ATTR_SHIFT(n) ((n) << 3) 185 #define IMMAIR_ATTR_IDX_NC 0 186 #define IMMAIR_ATTR_IDX_WBRWA 1 187 #define IMMAIR_ATTR_IDX_DEV 2 188 189 #define IMEAR 0x0030 190 191 #define IMPCTR 0x0200 192 #define IMPSTR 0x0208 193 #define IMPEAR 0x020c 194 #define IMPMBA(n) (0x0280 + ((n) * 4)) 195 #define IMPMBD(n) (0x02c0 + ((n) * 4)) 196 197 #define IMUCTR(n) (0x0300 + ((n) * 16)) 198 #define IMUCTR_FIXADDEN (1 << 31) 199 #define IMUCTR_FIXADD_MASK (0xff << 16) 200 #define IMUCTR_FIXADD_SHIFT 16 201 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) 202 #define IMUCTR_TTSEL_PMB (8 << 4) 203 #define IMUCTR_TTSEL_MASK (15 << 4) 204 #define IMUCTR_FLUSH (1 << 1) 205 #define IMUCTR_MMUEN (1 << 0) 206 207 #define IMUASID(n) (0x0308 + ((n) * 16)) 208 #define IMUASID_ASID8_MASK (0xff << 8) 209 #define IMUASID_ASID8_SHIFT 8 210 #define IMUASID_ASID0_MASK (0xff << 0) 211 #define IMUASID_ASID0_SHIFT 0 212 213 /* ----------------------------------------------------------------------------- 214 * Root device handling 215 */ 216 217 static struct platform_driver ipmmu_driver; 218 219 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu) 220 { 221 return mmu->root == mmu; 222 } 223 224 static int __ipmmu_check_device(struct device *dev, void *data) 225 { 226 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); 227 struct ipmmu_vmsa_device **rootp = data; 228 229 if (ipmmu_is_root(mmu)) 230 *rootp = mmu; 231 232 return 0; 233 } 234 235 static struct ipmmu_vmsa_device *ipmmu_find_root(void) 236 { 237 struct ipmmu_vmsa_device *root = NULL; 238 239 return driver_for_each_device(&ipmmu_driver.driver, NULL, &root, 240 __ipmmu_check_device) == 0 ? root : NULL; 241 } 242 243 /* ----------------------------------------------------------------------------- 244 * Read/Write Access 245 */ 246 247 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset) 248 { 249 return ioread32(mmu->base + offset); 250 } 251 252 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset, 253 u32 data) 254 { 255 iowrite32(data, mmu->base + offset); 256 } 257 258 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain, 259 unsigned int reg) 260 { 261 return ipmmu_read(domain->mmu->root, 262 domain->context_id * IM_CTX_SIZE + reg); 263 } 264 265 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain, 266 unsigned int reg, u32 data) 267 { 268 ipmmu_write(domain->mmu->root, 269 domain->context_id * IM_CTX_SIZE + reg, data); 270 } 271 272 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain, 273 unsigned int reg, u32 data) 274 { 275 if (domain->mmu != domain->mmu->root) 276 ipmmu_write(domain->mmu, 277 domain->context_id * IM_CTX_SIZE + reg, data); 278 279 ipmmu_write(domain->mmu->root, 280 domain->context_id * IM_CTX_SIZE + reg, data); 281 } 282 283 /* ----------------------------------------------------------------------------- 284 * TLB and microTLB Management 285 */ 286 287 /* Wait for any pending TLB invalidations to complete */ 288 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain) 289 { 290 unsigned int count = 0; 291 292 while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) { 293 cpu_relax(); 294 if (++count == TLB_LOOP_TIMEOUT) { 295 dev_err_ratelimited(domain->mmu->dev, 296 "TLB sync timed out -- MMU may be deadlocked\n"); 297 return; 298 } 299 udelay(1); 300 } 301 } 302 303 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain) 304 { 305 u32 reg; 306 307 reg = ipmmu_ctx_read_root(domain, IMCTR); 308 reg |= IMCTR_FLUSH; 309 ipmmu_ctx_write_all(domain, IMCTR, reg); 310 311 ipmmu_tlb_sync(domain); 312 } 313 314 /* 315 * Enable MMU translation for the microTLB. 316 */ 317 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, 318 unsigned int utlb) 319 { 320 struct ipmmu_vmsa_device *mmu = domain->mmu; 321 322 /* 323 * TODO: Reference-count the microTLB as several bus masters can be 324 * connected to the same microTLB. 325 */ 326 327 /* TODO: What should we set the ASID to ? */ 328 ipmmu_write(mmu, IMUASID(utlb), 0); 329 /* TODO: Do we need to flush the microTLB ? */ 330 ipmmu_write(mmu, IMUCTR(utlb), 331 IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH | 332 IMUCTR_MMUEN); 333 } 334 335 /* 336 * Disable MMU translation for the microTLB. 337 */ 338 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, 339 unsigned int utlb) 340 { 341 struct ipmmu_vmsa_device *mmu = domain->mmu; 342 343 ipmmu_write(mmu, IMUCTR(utlb), 0); 344 } 345 346 static void ipmmu_tlb_flush_all(void *cookie) 347 { 348 struct ipmmu_vmsa_domain *domain = cookie; 349 350 ipmmu_tlb_invalidate(domain); 351 } 352 353 static void ipmmu_tlb_add_flush(unsigned long iova, size_t size, 354 size_t granule, bool leaf, void *cookie) 355 { 356 /* The hardware doesn't support selective TLB flush. */ 357 } 358 359 static const struct iommu_gather_ops ipmmu_gather_ops = { 360 .tlb_flush_all = ipmmu_tlb_flush_all, 361 .tlb_add_flush = ipmmu_tlb_add_flush, 362 .tlb_sync = ipmmu_tlb_flush_all, 363 }; 364 365 /* ----------------------------------------------------------------------------- 366 * Domain/Context Management 367 */ 368 369 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu, 370 struct ipmmu_vmsa_domain *domain) 371 { 372 unsigned long flags; 373 int ret; 374 375 spin_lock_irqsave(&mmu->lock, flags); 376 377 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); 378 if (ret != mmu->num_ctx) { 379 mmu->domains[ret] = domain; 380 set_bit(ret, mmu->ctx); 381 } else 382 ret = -EBUSY; 383 384 spin_unlock_irqrestore(&mmu->lock, flags); 385 386 return ret; 387 } 388 389 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu, 390 unsigned int context_id) 391 { 392 unsigned long flags; 393 394 spin_lock_irqsave(&mmu->lock, flags); 395 396 clear_bit(context_id, mmu->ctx); 397 mmu->domains[context_id] = NULL; 398 399 spin_unlock_irqrestore(&mmu->lock, flags); 400 } 401 402 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) 403 { 404 u64 ttbr; 405 u32 tmp; 406 int ret; 407 408 /* 409 * Allocate the page table operations. 410 * 411 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory 412 * access, Long-descriptor format" that the NStable bit being set in a 413 * table descriptor will result in the NStable and NS bits of all child 414 * entries being ignored and considered as being set. The IPMMU seems 415 * not to comply with this, as it generates a secure access page fault 416 * if any of the NStable and NS bits isn't set when running in 417 * non-secure mode. 418 */ 419 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; 420 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; 421 domain->cfg.ias = 32; 422 domain->cfg.oas = 40; 423 domain->cfg.tlb = &ipmmu_gather_ops; 424 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); 425 domain->io_domain.geometry.force_aperture = true; 426 /* 427 * TODO: Add support for coherent walk through CCI with DVM and remove 428 * cache handling. For now, delegate it to the io-pgtable code. 429 */ 430 domain->cfg.iommu_dev = domain->mmu->root->dev; 431 432 /* 433 * Find an unused context. 434 */ 435 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); 436 if (ret < 0) 437 return ret; 438 439 domain->context_id = ret; 440 441 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, 442 domain); 443 if (!domain->iop) { 444 ipmmu_domain_free_context(domain->mmu->root, 445 domain->context_id); 446 return -EINVAL; 447 } 448 449 /* TTBR0 */ 450 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; 451 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); 452 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); 453 454 /* 455 * TTBCR 456 * We use long descriptors with inner-shareable WBWA tables and allocate 457 * the whole 32-bit VA space to TTBR0. 458 */ 459 if (domain->mmu->features->twobit_imttbcr_sl0) 460 tmp = IMTTBCR_SL0_TWOBIT_LVL_1; 461 else 462 tmp = IMTTBCR_SL0_LVL_1; 463 464 ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | 465 IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | 466 IMTTBCR_IRGN0_WB_WA | tmp); 467 468 /* MAIR0 */ 469 ipmmu_ctx_write_root(domain, IMMAIR0, 470 domain->cfg.arm_lpae_s1_cfg.mair[0]); 471 472 /* IMBUSCR */ 473 if (domain->mmu->features->setup_imbuscr) 474 ipmmu_ctx_write_root(domain, IMBUSCR, 475 ipmmu_ctx_read_root(domain, IMBUSCR) & 476 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK)); 477 478 /* 479 * IMSTR 480 * Clear all interrupt flags. 481 */ 482 ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR)); 483 484 /* 485 * IMCTR 486 * Enable the MMU and interrupt generation. The long-descriptor 487 * translation table format doesn't use TEX remapping. Don't enable AF 488 * software management as we have no use for it. Flush the TLB as 489 * required when modifying the context registers. 490 */ 491 ipmmu_ctx_write_all(domain, IMCTR, 492 IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN); 493 494 return 0; 495 } 496 497 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain) 498 { 499 /* 500 * Disable the context. Flush the TLB as required when modifying the 501 * context registers. 502 * 503 * TODO: Is TLB flush really needed ? 504 */ 505 ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH); 506 ipmmu_tlb_sync(domain); 507 ipmmu_domain_free_context(domain->mmu->root, domain->context_id); 508 } 509 510 /* ----------------------------------------------------------------------------- 511 * Fault Handling 512 */ 513 514 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain) 515 { 516 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF; 517 struct ipmmu_vmsa_device *mmu = domain->mmu; 518 u32 status; 519 u32 iova; 520 521 status = ipmmu_ctx_read_root(domain, IMSTR); 522 if (!(status & err_mask)) 523 return IRQ_NONE; 524 525 iova = ipmmu_ctx_read_root(domain, IMEAR); 526 527 /* 528 * Clear the error status flags. Unlike traditional interrupt flag 529 * registers that must be cleared by writing 1, this status register 530 * seems to require 0. The error address register must be read before, 531 * otherwise its value will be 0. 532 */ 533 ipmmu_ctx_write_root(domain, IMSTR, 0); 534 535 /* Log fatal errors. */ 536 if (status & IMSTR_MHIT) 537 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n", 538 iova); 539 if (status & IMSTR_ABORT) 540 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n", 541 iova); 542 543 if (!(status & (IMSTR_PF | IMSTR_TF))) 544 return IRQ_NONE; 545 546 /* 547 * Try to handle page faults and translation faults. 548 * 549 * TODO: We need to look up the faulty device based on the I/O VA. Use 550 * the IOMMU device for now. 551 */ 552 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) 553 return IRQ_HANDLED; 554 555 dev_err_ratelimited(mmu->dev, 556 "Unhandled fault: status 0x%08x iova 0x%08x\n", 557 status, iova); 558 559 return IRQ_HANDLED; 560 } 561 562 static irqreturn_t ipmmu_irq(int irq, void *dev) 563 { 564 struct ipmmu_vmsa_device *mmu = dev; 565 irqreturn_t status = IRQ_NONE; 566 unsigned int i; 567 unsigned long flags; 568 569 spin_lock_irqsave(&mmu->lock, flags); 570 571 /* 572 * Check interrupts for all active contexts. 573 */ 574 for (i = 0; i < mmu->num_ctx; i++) { 575 if (!mmu->domains[i]) 576 continue; 577 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) 578 status = IRQ_HANDLED; 579 } 580 581 spin_unlock_irqrestore(&mmu->lock, flags); 582 583 return status; 584 } 585 586 /* ----------------------------------------------------------------------------- 587 * IOMMU Operations 588 */ 589 590 static struct iommu_domain *__ipmmu_domain_alloc(unsigned type) 591 { 592 struct ipmmu_vmsa_domain *domain; 593 594 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 595 if (!domain) 596 return NULL; 597 598 spin_lock_init(&domain->lock); 599 600 return &domain->io_domain; 601 } 602 603 static struct iommu_domain *ipmmu_domain_alloc(unsigned type) 604 { 605 struct iommu_domain *io_domain = NULL; 606 607 switch (type) { 608 case IOMMU_DOMAIN_UNMANAGED: 609 io_domain = __ipmmu_domain_alloc(type); 610 break; 611 612 case IOMMU_DOMAIN_DMA: 613 io_domain = __ipmmu_domain_alloc(type); 614 if (io_domain && iommu_get_dma_cookie(io_domain)) { 615 kfree(io_domain); 616 io_domain = NULL; 617 } 618 break; 619 } 620 621 return io_domain; 622 } 623 624 static void ipmmu_domain_free(struct iommu_domain *io_domain) 625 { 626 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 627 628 /* 629 * Free the domain resources. We assume that all devices have already 630 * been detached. 631 */ 632 iommu_put_dma_cookie(io_domain); 633 ipmmu_domain_destroy_context(domain); 634 free_io_pgtable_ops(domain->iop); 635 kfree(domain); 636 } 637 638 static int ipmmu_attach_device(struct iommu_domain *io_domain, 639 struct device *dev) 640 { 641 struct iommu_fwspec *fwspec = dev->iommu_fwspec; 642 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 643 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 644 unsigned long flags; 645 unsigned int i; 646 int ret = 0; 647 648 if (!mmu) { 649 dev_err(dev, "Cannot attach to IPMMU\n"); 650 return -ENXIO; 651 } 652 653 spin_lock_irqsave(&domain->lock, flags); 654 655 if (!domain->mmu) { 656 /* The domain hasn't been used yet, initialize it. */ 657 domain->mmu = mmu; 658 ret = ipmmu_domain_init_context(domain); 659 if (ret < 0) { 660 dev_err(dev, "Unable to initialize IPMMU context\n"); 661 domain->mmu = NULL; 662 } else { 663 dev_info(dev, "Using IPMMU context %u\n", 664 domain->context_id); 665 } 666 } else if (domain->mmu != mmu) { 667 /* 668 * Something is wrong, we can't attach two devices using 669 * different IOMMUs to the same domain. 670 */ 671 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n", 672 dev_name(mmu->dev), dev_name(domain->mmu->dev)); 673 ret = -EINVAL; 674 } else 675 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); 676 677 spin_unlock_irqrestore(&domain->lock, flags); 678 679 if (ret < 0) 680 return ret; 681 682 for (i = 0; i < fwspec->num_ids; ++i) 683 ipmmu_utlb_enable(domain, fwspec->ids[i]); 684 685 return 0; 686 } 687 688 static void ipmmu_detach_device(struct iommu_domain *io_domain, 689 struct device *dev) 690 { 691 struct iommu_fwspec *fwspec = dev->iommu_fwspec; 692 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 693 unsigned int i; 694 695 for (i = 0; i < fwspec->num_ids; ++i) 696 ipmmu_utlb_disable(domain, fwspec->ids[i]); 697 698 /* 699 * TODO: Optimize by disabling the context when no device is attached. 700 */ 701 } 702 703 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova, 704 phys_addr_t paddr, size_t size, int prot) 705 { 706 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 707 708 if (!domain) 709 return -ENODEV; 710 711 return domain->iop->map(domain->iop, iova, paddr, size, prot); 712 } 713 714 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova, 715 size_t size) 716 { 717 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 718 719 return domain->iop->unmap(domain->iop, iova, size); 720 } 721 722 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain) 723 { 724 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 725 726 if (domain->mmu) 727 ipmmu_tlb_flush_all(domain); 728 } 729 730 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain, 731 dma_addr_t iova) 732 { 733 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 734 735 /* TODO: Is locking needed ? */ 736 737 return domain->iop->iova_to_phys(domain->iop, iova); 738 } 739 740 static int ipmmu_init_platform_device(struct device *dev, 741 struct of_phandle_args *args) 742 { 743 struct platform_device *ipmmu_pdev; 744 745 ipmmu_pdev = of_find_device_by_node(args->np); 746 if (!ipmmu_pdev) 747 return -ENODEV; 748 749 dev->iommu_fwspec->iommu_priv = platform_get_drvdata(ipmmu_pdev); 750 return 0; 751 } 752 753 static bool ipmmu_slave_whitelist(struct device *dev) 754 { 755 /* By default, do not allow use of IPMMU */ 756 return false; 757 } 758 759 static const struct soc_device_attribute soc_r8a7795[] = { 760 { .soc_id = "r8a7795", }, 761 { /* sentinel */ } 762 }; 763 764 static int ipmmu_of_xlate(struct device *dev, 765 struct of_phandle_args *spec) 766 { 767 /* For R-Car Gen3 use a white list to opt-in slave devices */ 768 if (soc_device_match(soc_r8a7795) && !ipmmu_slave_whitelist(dev)) 769 return -ENODEV; 770 771 iommu_fwspec_add_ids(dev, spec->args, 1); 772 773 /* Initialize once - xlate() will call multiple times */ 774 if (to_ipmmu(dev)) 775 return 0; 776 777 return ipmmu_init_platform_device(dev, spec); 778 } 779 780 static int ipmmu_init_arm_mapping(struct device *dev) 781 { 782 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 783 struct iommu_group *group; 784 int ret; 785 786 /* Create a device group and add the device to it. */ 787 group = iommu_group_alloc(); 788 if (IS_ERR(group)) { 789 dev_err(dev, "Failed to allocate IOMMU group\n"); 790 return PTR_ERR(group); 791 } 792 793 ret = iommu_group_add_device(group, dev); 794 iommu_group_put(group); 795 796 if (ret < 0) { 797 dev_err(dev, "Failed to add device to IPMMU group\n"); 798 return ret; 799 } 800 801 /* 802 * Create the ARM mapping, used by the ARM DMA mapping core to allocate 803 * VAs. This will allocate a corresponding IOMMU domain. 804 * 805 * TODO: 806 * - Create one mapping per context (TLB). 807 * - Make the mapping size configurable ? We currently use a 2GB mapping 808 * at a 1GB offset to ensure that NULL VAs will fault. 809 */ 810 if (!mmu->mapping) { 811 struct dma_iommu_mapping *mapping; 812 813 mapping = arm_iommu_create_mapping(&platform_bus_type, 814 SZ_1G, SZ_2G); 815 if (IS_ERR(mapping)) { 816 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); 817 ret = PTR_ERR(mapping); 818 goto error; 819 } 820 821 mmu->mapping = mapping; 822 } 823 824 /* Attach the ARM VA mapping to the device. */ 825 ret = arm_iommu_attach_device(dev, mmu->mapping); 826 if (ret < 0) { 827 dev_err(dev, "Failed to attach device to VA mapping\n"); 828 goto error; 829 } 830 831 return 0; 832 833 error: 834 iommu_group_remove_device(dev); 835 if (mmu->mapping) 836 arm_iommu_release_mapping(mmu->mapping); 837 838 return ret; 839 } 840 841 static int ipmmu_add_device(struct device *dev) 842 { 843 struct iommu_group *group; 844 845 /* 846 * Only let through devices that have been verified in xlate() 847 */ 848 if (!to_ipmmu(dev)) 849 return -ENODEV; 850 851 if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)) 852 return ipmmu_init_arm_mapping(dev); 853 854 group = iommu_group_get_for_dev(dev); 855 if (IS_ERR(group)) 856 return PTR_ERR(group); 857 858 iommu_group_put(group); 859 return 0; 860 } 861 862 static void ipmmu_remove_device(struct device *dev) 863 { 864 arm_iommu_detach_device(dev); 865 iommu_group_remove_device(dev); 866 } 867 868 static struct iommu_group *ipmmu_find_group(struct device *dev) 869 { 870 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 871 struct iommu_group *group; 872 873 if (mmu->group) 874 return iommu_group_ref_get(mmu->group); 875 876 group = iommu_group_alloc(); 877 if (!IS_ERR(group)) 878 mmu->group = group; 879 880 return group; 881 } 882 883 static const struct iommu_ops ipmmu_ops = { 884 .domain_alloc = ipmmu_domain_alloc, 885 .domain_free = ipmmu_domain_free, 886 .attach_dev = ipmmu_attach_device, 887 .detach_dev = ipmmu_detach_device, 888 .map = ipmmu_map, 889 .unmap = ipmmu_unmap, 890 .flush_iotlb_all = ipmmu_iotlb_sync, 891 .iotlb_sync = ipmmu_iotlb_sync, 892 .map_sg = default_iommu_map_sg, 893 .iova_to_phys = ipmmu_iova_to_phys, 894 .add_device = ipmmu_add_device, 895 .remove_device = ipmmu_remove_device, 896 .device_group = ipmmu_find_group, 897 .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, 898 .of_xlate = ipmmu_of_xlate, 899 }; 900 901 /* ----------------------------------------------------------------------------- 902 * Probe/remove and init 903 */ 904 905 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) 906 { 907 unsigned int i; 908 909 /* Disable all contexts. */ 910 for (i = 0; i < mmu->num_ctx; ++i) 911 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0); 912 } 913 914 static const struct ipmmu_features ipmmu_features_default = { 915 .use_ns_alias_offset = true, 916 .has_cache_leaf_nodes = false, 917 .number_of_contexts = 1, /* software only tested with one context */ 918 .setup_imbuscr = true, 919 .twobit_imttbcr_sl0 = false, 920 }; 921 922 static const struct ipmmu_features ipmmu_features_r8a7795 = { 923 .use_ns_alias_offset = false, 924 .has_cache_leaf_nodes = true, 925 .number_of_contexts = 8, 926 .setup_imbuscr = false, 927 .twobit_imttbcr_sl0 = true, 928 }; 929 930 static const struct of_device_id ipmmu_of_ids[] = { 931 { 932 .compatible = "renesas,ipmmu-vmsa", 933 .data = &ipmmu_features_default, 934 }, { 935 .compatible = "renesas,ipmmu-r8a7795", 936 .data = &ipmmu_features_r8a7795, 937 }, { 938 /* Terminator */ 939 }, 940 }; 941 942 MODULE_DEVICE_TABLE(of, ipmmu_of_ids); 943 944 static int ipmmu_probe(struct platform_device *pdev) 945 { 946 struct ipmmu_vmsa_device *mmu; 947 struct resource *res; 948 int irq; 949 int ret; 950 951 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); 952 if (!mmu) { 953 dev_err(&pdev->dev, "cannot allocate device data\n"); 954 return -ENOMEM; 955 } 956 957 mmu->dev = &pdev->dev; 958 mmu->num_utlbs = 32; 959 spin_lock_init(&mmu->lock); 960 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); 961 mmu->features = of_device_get_match_data(&pdev->dev); 962 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 963 964 /* Map I/O memory and request IRQ. */ 965 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 966 mmu->base = devm_ioremap_resource(&pdev->dev, res); 967 if (IS_ERR(mmu->base)) 968 return PTR_ERR(mmu->base); 969 970 /* 971 * The IPMMU has two register banks, for secure and non-secure modes. 972 * The bank mapped at the beginning of the IPMMU address space 973 * corresponds to the running mode of the CPU. When running in secure 974 * mode the non-secure register bank is also available at an offset. 975 * 976 * Secure mode operation isn't clearly documented and is thus currently 977 * not implemented in the driver. Furthermore, preliminary tests of 978 * non-secure operation with the main register bank were not successful. 979 * Offset the registers base unconditionally to point to the non-secure 980 * alias space for now. 981 */ 982 if (mmu->features->use_ns_alias_offset) 983 mmu->base += IM_NS_ALIAS_OFFSET; 984 985 mmu->num_ctx = min_t(unsigned int, IPMMU_CTX_MAX, 986 mmu->features->number_of_contexts); 987 988 irq = platform_get_irq(pdev, 0); 989 990 /* 991 * Determine if this IPMMU instance is a root device by checking for 992 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. 993 */ 994 if (!mmu->features->has_cache_leaf_nodes || 995 !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL)) 996 mmu->root = mmu; 997 else 998 mmu->root = ipmmu_find_root(); 999 1000 /* 1001 * Wait until the root device has been registered for sure. 1002 */ 1003 if (!mmu->root) 1004 return -EPROBE_DEFER; 1005 1006 /* Root devices have mandatory IRQs */ 1007 if (ipmmu_is_root(mmu)) { 1008 if (irq < 0) { 1009 dev_err(&pdev->dev, "no IRQ found\n"); 1010 return irq; 1011 } 1012 1013 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, 1014 dev_name(&pdev->dev), mmu); 1015 if (ret < 0) { 1016 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); 1017 return ret; 1018 } 1019 1020 ipmmu_device_reset(mmu); 1021 } 1022 1023 /* 1024 * Register the IPMMU to the IOMMU subsystem in the following cases: 1025 * - R-Car Gen2 IPMMU (all devices registered) 1026 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) 1027 */ 1028 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) { 1029 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, 1030 dev_name(&pdev->dev)); 1031 if (ret) 1032 return ret; 1033 1034 iommu_device_set_ops(&mmu->iommu, &ipmmu_ops); 1035 iommu_device_set_fwnode(&mmu->iommu, 1036 &pdev->dev.of_node->fwnode); 1037 1038 ret = iommu_device_register(&mmu->iommu); 1039 if (ret) 1040 return ret; 1041 1042 #if defined(CONFIG_IOMMU_DMA) 1043 if (!iommu_present(&platform_bus_type)) 1044 bus_set_iommu(&platform_bus_type, &ipmmu_ops); 1045 #endif 1046 } 1047 1048 /* 1049 * We can't create the ARM mapping here as it requires the bus to have 1050 * an IOMMU, which only happens when bus_set_iommu() is called in 1051 * ipmmu_init() after the probe function returns. 1052 */ 1053 1054 platform_set_drvdata(pdev, mmu); 1055 1056 return 0; 1057 } 1058 1059 static int ipmmu_remove(struct platform_device *pdev) 1060 { 1061 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev); 1062 1063 iommu_device_sysfs_remove(&mmu->iommu); 1064 iommu_device_unregister(&mmu->iommu); 1065 1066 arm_iommu_release_mapping(mmu->mapping); 1067 1068 ipmmu_device_reset(mmu); 1069 1070 return 0; 1071 } 1072 1073 static struct platform_driver ipmmu_driver = { 1074 .driver = { 1075 .name = "ipmmu-vmsa", 1076 .of_match_table = of_match_ptr(ipmmu_of_ids), 1077 }, 1078 .probe = ipmmu_probe, 1079 .remove = ipmmu_remove, 1080 }; 1081 1082 static int __init ipmmu_init(void) 1083 { 1084 static bool setup_done; 1085 int ret; 1086 1087 if (setup_done) 1088 return 0; 1089 1090 ret = platform_driver_register(&ipmmu_driver); 1091 if (ret < 0) 1092 return ret; 1093 1094 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 1095 if (!iommu_present(&platform_bus_type)) 1096 bus_set_iommu(&platform_bus_type, &ipmmu_ops); 1097 #endif 1098 1099 setup_done = true; 1100 return 0; 1101 } 1102 1103 static void __exit ipmmu_exit(void) 1104 { 1105 return platform_driver_unregister(&ipmmu_driver); 1106 } 1107 1108 subsys_initcall(ipmmu_init); 1109 module_exit(ipmmu_exit); 1110 1111 #ifdef CONFIG_IOMMU_DMA 1112 static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np) 1113 { 1114 ipmmu_init(); 1115 return 0; 1116 } 1117 1118 IOMMU_OF_DECLARE(ipmmu_vmsa_iommu_of, "renesas,ipmmu-vmsa", 1119 ipmmu_vmsa_iommu_of_setup); 1120 IOMMU_OF_DECLARE(ipmmu_r8a7795_iommu_of, "renesas,ipmmu-r8a7795", 1121 ipmmu_vmsa_iommu_of_setup); 1122 #endif 1123 1124 MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU"); 1125 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 1126 MODULE_LICENSE("GPL v2"); 1127