1 /* 2 * IPMMU VMSA 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 */ 10 11 #include <linux/bitmap.h> 12 #include <linux/delay.h> 13 #include <linux/dma-iommu.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/export.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iommu.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_iommu.h> 24 #include <linux/of_platform.h> 25 #include <linux/platform_device.h> 26 #include <linux/sizes.h> 27 #include <linux/slab.h> 28 #include <linux/sys_soc.h> 29 30 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 31 #include <asm/dma-iommu.h> 32 #include <asm/pgalloc.h> 33 #else 34 #define arm_iommu_create_mapping(...) NULL 35 #define arm_iommu_attach_device(...) -ENODEV 36 #define arm_iommu_release_mapping(...) do {} while (0) 37 #define arm_iommu_detach_device(...) do {} while (0) 38 #endif 39 40 #include "io-pgtable.h" 41 42 #define IPMMU_CTX_MAX 8 43 44 struct ipmmu_features { 45 bool use_ns_alias_offset; 46 bool has_cache_leaf_nodes; 47 unsigned int number_of_contexts; 48 bool setup_imbuscr; 49 bool twobit_imttbcr_sl0; 50 bool reserved_context; 51 }; 52 53 struct ipmmu_vmsa_device { 54 struct device *dev; 55 void __iomem *base; 56 struct iommu_device iommu; 57 struct ipmmu_vmsa_device *root; 58 const struct ipmmu_features *features; 59 unsigned int num_utlbs; 60 unsigned int num_ctx; 61 spinlock_t lock; /* Protects ctx and domains[] */ 62 DECLARE_BITMAP(ctx, IPMMU_CTX_MAX); 63 struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; 64 65 struct iommu_group *group; 66 struct dma_iommu_mapping *mapping; 67 }; 68 69 struct ipmmu_vmsa_domain { 70 struct ipmmu_vmsa_device *mmu; 71 struct iommu_domain io_domain; 72 73 struct io_pgtable_cfg cfg; 74 struct io_pgtable_ops *iop; 75 76 unsigned int context_id; 77 struct mutex mutex; /* Protects mappings */ 78 }; 79 80 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom) 81 { 82 return container_of(dom, struct ipmmu_vmsa_domain, io_domain); 83 } 84 85 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) 86 { 87 return dev->iommu_fwspec ? dev->iommu_fwspec->iommu_priv : NULL; 88 } 89 90 #define TLB_LOOP_TIMEOUT 100 /* 100us */ 91 92 /* ----------------------------------------------------------------------------- 93 * Registers Definition 94 */ 95 96 #define IM_NS_ALIAS_OFFSET 0x800 97 98 #define IM_CTX_SIZE 0x40 99 100 #define IMCTR 0x0000 101 #define IMCTR_TRE (1 << 17) 102 #define IMCTR_AFE (1 << 16) 103 #define IMCTR_RTSEL_MASK (3 << 4) 104 #define IMCTR_RTSEL_SHIFT 4 105 #define IMCTR_TREN (1 << 3) 106 #define IMCTR_INTEN (1 << 2) 107 #define IMCTR_FLUSH (1 << 1) 108 #define IMCTR_MMUEN (1 << 0) 109 110 #define IMCAAR 0x0004 111 112 #define IMTTBCR 0x0008 113 #define IMTTBCR_EAE (1 << 31) 114 #define IMTTBCR_PMB (1 << 30) 115 #define IMTTBCR_SH1_NON_SHAREABLE (0 << 28) 116 #define IMTTBCR_SH1_OUTER_SHAREABLE (2 << 28) 117 #define IMTTBCR_SH1_INNER_SHAREABLE (3 << 28) 118 #define IMTTBCR_SH1_MASK (3 << 28) 119 #define IMTTBCR_ORGN1_NC (0 << 26) 120 #define IMTTBCR_ORGN1_WB_WA (1 << 26) 121 #define IMTTBCR_ORGN1_WT (2 << 26) 122 #define IMTTBCR_ORGN1_WB (3 << 26) 123 #define IMTTBCR_ORGN1_MASK (3 << 26) 124 #define IMTTBCR_IRGN1_NC (0 << 24) 125 #define IMTTBCR_IRGN1_WB_WA (1 << 24) 126 #define IMTTBCR_IRGN1_WT (2 << 24) 127 #define IMTTBCR_IRGN1_WB (3 << 24) 128 #define IMTTBCR_IRGN1_MASK (3 << 24) 129 #define IMTTBCR_TSZ1_MASK (7 << 16) 130 #define IMTTBCR_TSZ1_SHIFT 16 131 #define IMTTBCR_SH0_NON_SHAREABLE (0 << 12) 132 #define IMTTBCR_SH0_OUTER_SHAREABLE (2 << 12) 133 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) 134 #define IMTTBCR_SH0_MASK (3 << 12) 135 #define IMTTBCR_ORGN0_NC (0 << 10) 136 #define IMTTBCR_ORGN0_WB_WA (1 << 10) 137 #define IMTTBCR_ORGN0_WT (2 << 10) 138 #define IMTTBCR_ORGN0_WB (3 << 10) 139 #define IMTTBCR_ORGN0_MASK (3 << 10) 140 #define IMTTBCR_IRGN0_NC (0 << 8) 141 #define IMTTBCR_IRGN0_WB_WA (1 << 8) 142 #define IMTTBCR_IRGN0_WT (2 << 8) 143 #define IMTTBCR_IRGN0_WB (3 << 8) 144 #define IMTTBCR_IRGN0_MASK (3 << 8) 145 #define IMTTBCR_SL0_LVL_2 (0 << 4) 146 #define IMTTBCR_SL0_LVL_1 (1 << 4) 147 #define IMTTBCR_TSZ0_MASK (7 << 0) 148 #define IMTTBCR_TSZ0_SHIFT O 149 150 #define IMTTBCR_SL0_TWOBIT_LVL_3 (0 << 6) 151 #define IMTTBCR_SL0_TWOBIT_LVL_2 (1 << 6) 152 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) 153 154 #define IMBUSCR 0x000c 155 #define IMBUSCR_DVM (1 << 2) 156 #define IMBUSCR_BUSSEL_SYS (0 << 0) 157 #define IMBUSCR_BUSSEL_CCI (1 << 0) 158 #define IMBUSCR_BUSSEL_IMCAAR (2 << 0) 159 #define IMBUSCR_BUSSEL_CCI_IMCAAR (3 << 0) 160 #define IMBUSCR_BUSSEL_MASK (3 << 0) 161 162 #define IMTTLBR0 0x0010 163 #define IMTTUBR0 0x0014 164 #define IMTTLBR1 0x0018 165 #define IMTTUBR1 0x001c 166 167 #define IMSTR 0x0020 168 #define IMSTR_ERRLVL_MASK (3 << 12) 169 #define IMSTR_ERRLVL_SHIFT 12 170 #define IMSTR_ERRCODE_TLB_FORMAT (1 << 8) 171 #define IMSTR_ERRCODE_ACCESS_PERM (4 << 8) 172 #define IMSTR_ERRCODE_SECURE_ACCESS (5 << 8) 173 #define IMSTR_ERRCODE_MASK (7 << 8) 174 #define IMSTR_MHIT (1 << 4) 175 #define IMSTR_ABORT (1 << 2) 176 #define IMSTR_PF (1 << 1) 177 #define IMSTR_TF (1 << 0) 178 179 #define IMMAIR0 0x0028 180 #define IMMAIR1 0x002c 181 #define IMMAIR_ATTR_MASK 0xff 182 #define IMMAIR_ATTR_DEVICE 0x04 183 #define IMMAIR_ATTR_NC 0x44 184 #define IMMAIR_ATTR_WBRWA 0xff 185 #define IMMAIR_ATTR_SHIFT(n) ((n) << 3) 186 #define IMMAIR_ATTR_IDX_NC 0 187 #define IMMAIR_ATTR_IDX_WBRWA 1 188 #define IMMAIR_ATTR_IDX_DEV 2 189 190 #define IMEAR 0x0030 191 192 #define IMPCTR 0x0200 193 #define IMPSTR 0x0208 194 #define IMPEAR 0x020c 195 #define IMPMBA(n) (0x0280 + ((n) * 4)) 196 #define IMPMBD(n) (0x02c0 + ((n) * 4)) 197 198 #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n)) 199 #define IMUCTR0(n) (0x0300 + ((n) * 16)) 200 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) 201 #define IMUCTR_FIXADDEN (1 << 31) 202 #define IMUCTR_FIXADD_MASK (0xff << 16) 203 #define IMUCTR_FIXADD_SHIFT 16 204 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) 205 #define IMUCTR_TTSEL_PMB (8 << 4) 206 #define IMUCTR_TTSEL_MASK (15 << 4) 207 #define IMUCTR_FLUSH (1 << 1) 208 #define IMUCTR_MMUEN (1 << 0) 209 210 #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n)) 211 #define IMUASID0(n) (0x0308 + ((n) * 16)) 212 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) 213 #define IMUASID_ASID8_MASK (0xff << 8) 214 #define IMUASID_ASID8_SHIFT 8 215 #define IMUASID_ASID0_MASK (0xff << 0) 216 #define IMUASID_ASID0_SHIFT 0 217 218 /* ----------------------------------------------------------------------------- 219 * Root device handling 220 */ 221 222 static struct platform_driver ipmmu_driver; 223 224 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu) 225 { 226 return mmu->root == mmu; 227 } 228 229 static int __ipmmu_check_device(struct device *dev, void *data) 230 { 231 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); 232 struct ipmmu_vmsa_device **rootp = data; 233 234 if (ipmmu_is_root(mmu)) 235 *rootp = mmu; 236 237 return 0; 238 } 239 240 static struct ipmmu_vmsa_device *ipmmu_find_root(void) 241 { 242 struct ipmmu_vmsa_device *root = NULL; 243 244 return driver_for_each_device(&ipmmu_driver.driver, NULL, &root, 245 __ipmmu_check_device) == 0 ? root : NULL; 246 } 247 248 /* ----------------------------------------------------------------------------- 249 * Read/Write Access 250 */ 251 252 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset) 253 { 254 return ioread32(mmu->base + offset); 255 } 256 257 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset, 258 u32 data) 259 { 260 iowrite32(data, mmu->base + offset); 261 } 262 263 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain, 264 unsigned int reg) 265 { 266 return ipmmu_read(domain->mmu->root, 267 domain->context_id * IM_CTX_SIZE + reg); 268 } 269 270 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain, 271 unsigned int reg, u32 data) 272 { 273 ipmmu_write(domain->mmu->root, 274 domain->context_id * IM_CTX_SIZE + reg, data); 275 } 276 277 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain, 278 unsigned int reg, u32 data) 279 { 280 if (domain->mmu != domain->mmu->root) 281 ipmmu_write(domain->mmu, 282 domain->context_id * IM_CTX_SIZE + reg, data); 283 284 ipmmu_write(domain->mmu->root, 285 domain->context_id * IM_CTX_SIZE + reg, data); 286 } 287 288 /* ----------------------------------------------------------------------------- 289 * TLB and microTLB Management 290 */ 291 292 /* Wait for any pending TLB invalidations to complete */ 293 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain) 294 { 295 unsigned int count = 0; 296 297 while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) { 298 cpu_relax(); 299 if (++count == TLB_LOOP_TIMEOUT) { 300 dev_err_ratelimited(domain->mmu->dev, 301 "TLB sync timed out -- MMU may be deadlocked\n"); 302 return; 303 } 304 udelay(1); 305 } 306 } 307 308 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain) 309 { 310 u32 reg; 311 312 reg = ipmmu_ctx_read_root(domain, IMCTR); 313 reg |= IMCTR_FLUSH; 314 ipmmu_ctx_write_all(domain, IMCTR, reg); 315 316 ipmmu_tlb_sync(domain); 317 } 318 319 /* 320 * Enable MMU translation for the microTLB. 321 */ 322 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, 323 unsigned int utlb) 324 { 325 struct ipmmu_vmsa_device *mmu = domain->mmu; 326 327 /* 328 * TODO: Reference-count the microTLB as several bus masters can be 329 * connected to the same microTLB. 330 */ 331 332 /* TODO: What should we set the ASID to ? */ 333 ipmmu_write(mmu, IMUASID(utlb), 0); 334 /* TODO: Do we need to flush the microTLB ? */ 335 ipmmu_write(mmu, IMUCTR(utlb), 336 IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH | 337 IMUCTR_MMUEN); 338 } 339 340 /* 341 * Disable MMU translation for the microTLB. 342 */ 343 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, 344 unsigned int utlb) 345 { 346 struct ipmmu_vmsa_device *mmu = domain->mmu; 347 348 ipmmu_write(mmu, IMUCTR(utlb), 0); 349 } 350 351 static void ipmmu_tlb_flush_all(void *cookie) 352 { 353 struct ipmmu_vmsa_domain *domain = cookie; 354 355 ipmmu_tlb_invalidate(domain); 356 } 357 358 static void ipmmu_tlb_add_flush(unsigned long iova, size_t size, 359 size_t granule, bool leaf, void *cookie) 360 { 361 /* The hardware doesn't support selective TLB flush. */ 362 } 363 364 static const struct iommu_gather_ops ipmmu_gather_ops = { 365 .tlb_flush_all = ipmmu_tlb_flush_all, 366 .tlb_add_flush = ipmmu_tlb_add_flush, 367 .tlb_sync = ipmmu_tlb_flush_all, 368 }; 369 370 /* ----------------------------------------------------------------------------- 371 * Domain/Context Management 372 */ 373 374 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu, 375 struct ipmmu_vmsa_domain *domain) 376 { 377 unsigned long flags; 378 int ret; 379 380 spin_lock_irqsave(&mmu->lock, flags); 381 382 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); 383 if (ret != mmu->num_ctx) { 384 mmu->domains[ret] = domain; 385 set_bit(ret, mmu->ctx); 386 } else 387 ret = -EBUSY; 388 389 spin_unlock_irqrestore(&mmu->lock, flags); 390 391 return ret; 392 } 393 394 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu, 395 unsigned int context_id) 396 { 397 unsigned long flags; 398 399 spin_lock_irqsave(&mmu->lock, flags); 400 401 clear_bit(context_id, mmu->ctx); 402 mmu->domains[context_id] = NULL; 403 404 spin_unlock_irqrestore(&mmu->lock, flags); 405 } 406 407 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) 408 { 409 u64 ttbr; 410 u32 tmp; 411 int ret; 412 413 /* 414 * Allocate the page table operations. 415 * 416 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory 417 * access, Long-descriptor format" that the NStable bit being set in a 418 * table descriptor will result in the NStable and NS bits of all child 419 * entries being ignored and considered as being set. The IPMMU seems 420 * not to comply with this, as it generates a secure access page fault 421 * if any of the NStable and NS bits isn't set when running in 422 * non-secure mode. 423 */ 424 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; 425 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; 426 domain->cfg.ias = 32; 427 domain->cfg.oas = 40; 428 domain->cfg.tlb = &ipmmu_gather_ops; 429 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); 430 domain->io_domain.geometry.force_aperture = true; 431 /* 432 * TODO: Add support for coherent walk through CCI with DVM and remove 433 * cache handling. For now, delegate it to the io-pgtable code. 434 */ 435 domain->cfg.iommu_dev = domain->mmu->root->dev; 436 437 /* 438 * Find an unused context. 439 */ 440 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); 441 if (ret < 0) 442 return ret; 443 444 domain->context_id = ret; 445 446 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, 447 domain); 448 if (!domain->iop) { 449 ipmmu_domain_free_context(domain->mmu->root, 450 domain->context_id); 451 return -EINVAL; 452 } 453 454 /* TTBR0 */ 455 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; 456 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); 457 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); 458 459 /* 460 * TTBCR 461 * We use long descriptors with inner-shareable WBWA tables and allocate 462 * the whole 32-bit VA space to TTBR0. 463 */ 464 if (domain->mmu->features->twobit_imttbcr_sl0) 465 tmp = IMTTBCR_SL0_TWOBIT_LVL_1; 466 else 467 tmp = IMTTBCR_SL0_LVL_1; 468 469 ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | 470 IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | 471 IMTTBCR_IRGN0_WB_WA | tmp); 472 473 /* MAIR0 */ 474 ipmmu_ctx_write_root(domain, IMMAIR0, 475 domain->cfg.arm_lpae_s1_cfg.mair[0]); 476 477 /* IMBUSCR */ 478 if (domain->mmu->features->setup_imbuscr) 479 ipmmu_ctx_write_root(domain, IMBUSCR, 480 ipmmu_ctx_read_root(domain, IMBUSCR) & 481 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK)); 482 483 /* 484 * IMSTR 485 * Clear all interrupt flags. 486 */ 487 ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR)); 488 489 /* 490 * IMCTR 491 * Enable the MMU and interrupt generation. The long-descriptor 492 * translation table format doesn't use TEX remapping. Don't enable AF 493 * software management as we have no use for it. Flush the TLB as 494 * required when modifying the context registers. 495 */ 496 ipmmu_ctx_write_all(domain, IMCTR, 497 IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN); 498 499 return 0; 500 } 501 502 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain) 503 { 504 /* 505 * Disable the context. Flush the TLB as required when modifying the 506 * context registers. 507 * 508 * TODO: Is TLB flush really needed ? 509 */ 510 ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH); 511 ipmmu_tlb_sync(domain); 512 ipmmu_domain_free_context(domain->mmu->root, domain->context_id); 513 } 514 515 /* ----------------------------------------------------------------------------- 516 * Fault Handling 517 */ 518 519 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain) 520 { 521 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF; 522 struct ipmmu_vmsa_device *mmu = domain->mmu; 523 u32 status; 524 u32 iova; 525 526 status = ipmmu_ctx_read_root(domain, IMSTR); 527 if (!(status & err_mask)) 528 return IRQ_NONE; 529 530 iova = ipmmu_ctx_read_root(domain, IMEAR); 531 532 /* 533 * Clear the error status flags. Unlike traditional interrupt flag 534 * registers that must be cleared by writing 1, this status register 535 * seems to require 0. The error address register must be read before, 536 * otherwise its value will be 0. 537 */ 538 ipmmu_ctx_write_root(domain, IMSTR, 0); 539 540 /* Log fatal errors. */ 541 if (status & IMSTR_MHIT) 542 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n", 543 iova); 544 if (status & IMSTR_ABORT) 545 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n", 546 iova); 547 548 if (!(status & (IMSTR_PF | IMSTR_TF))) 549 return IRQ_NONE; 550 551 /* 552 * Try to handle page faults and translation faults. 553 * 554 * TODO: We need to look up the faulty device based on the I/O VA. Use 555 * the IOMMU device for now. 556 */ 557 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) 558 return IRQ_HANDLED; 559 560 dev_err_ratelimited(mmu->dev, 561 "Unhandled fault: status 0x%08x iova 0x%08x\n", 562 status, iova); 563 564 return IRQ_HANDLED; 565 } 566 567 static irqreturn_t ipmmu_irq(int irq, void *dev) 568 { 569 struct ipmmu_vmsa_device *mmu = dev; 570 irqreturn_t status = IRQ_NONE; 571 unsigned int i; 572 unsigned long flags; 573 574 spin_lock_irqsave(&mmu->lock, flags); 575 576 /* 577 * Check interrupts for all active contexts. 578 */ 579 for (i = 0; i < mmu->num_ctx; i++) { 580 if (!mmu->domains[i]) 581 continue; 582 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) 583 status = IRQ_HANDLED; 584 } 585 586 spin_unlock_irqrestore(&mmu->lock, flags); 587 588 return status; 589 } 590 591 /* ----------------------------------------------------------------------------- 592 * IOMMU Operations 593 */ 594 595 static struct iommu_domain *__ipmmu_domain_alloc(unsigned type) 596 { 597 struct ipmmu_vmsa_domain *domain; 598 599 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 600 if (!domain) 601 return NULL; 602 603 mutex_init(&domain->mutex); 604 605 return &domain->io_domain; 606 } 607 608 static struct iommu_domain *ipmmu_domain_alloc(unsigned type) 609 { 610 struct iommu_domain *io_domain = NULL; 611 612 switch (type) { 613 case IOMMU_DOMAIN_UNMANAGED: 614 io_domain = __ipmmu_domain_alloc(type); 615 break; 616 617 case IOMMU_DOMAIN_DMA: 618 io_domain = __ipmmu_domain_alloc(type); 619 if (io_domain && iommu_get_dma_cookie(io_domain)) { 620 kfree(io_domain); 621 io_domain = NULL; 622 } 623 break; 624 } 625 626 return io_domain; 627 } 628 629 static void ipmmu_domain_free(struct iommu_domain *io_domain) 630 { 631 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 632 633 /* 634 * Free the domain resources. We assume that all devices have already 635 * been detached. 636 */ 637 iommu_put_dma_cookie(io_domain); 638 ipmmu_domain_destroy_context(domain); 639 free_io_pgtable_ops(domain->iop); 640 kfree(domain); 641 } 642 643 static int ipmmu_attach_device(struct iommu_domain *io_domain, 644 struct device *dev) 645 { 646 struct iommu_fwspec *fwspec = dev->iommu_fwspec; 647 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 648 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 649 unsigned int i; 650 int ret = 0; 651 652 if (!mmu) { 653 dev_err(dev, "Cannot attach to IPMMU\n"); 654 return -ENXIO; 655 } 656 657 mutex_lock(&domain->mutex); 658 659 if (!domain->mmu) { 660 /* The domain hasn't been used yet, initialize it. */ 661 domain->mmu = mmu; 662 ret = ipmmu_domain_init_context(domain); 663 if (ret < 0) { 664 dev_err(dev, "Unable to initialize IPMMU context\n"); 665 domain->mmu = NULL; 666 } else { 667 dev_info(dev, "Using IPMMU context %u\n", 668 domain->context_id); 669 } 670 } else if (domain->mmu != mmu) { 671 /* 672 * Something is wrong, we can't attach two devices using 673 * different IOMMUs to the same domain. 674 */ 675 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n", 676 dev_name(mmu->dev), dev_name(domain->mmu->dev)); 677 ret = -EINVAL; 678 } else 679 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); 680 681 mutex_unlock(&domain->mutex); 682 683 if (ret < 0) 684 return ret; 685 686 for (i = 0; i < fwspec->num_ids; ++i) 687 ipmmu_utlb_enable(domain, fwspec->ids[i]); 688 689 return 0; 690 } 691 692 static void ipmmu_detach_device(struct iommu_domain *io_domain, 693 struct device *dev) 694 { 695 struct iommu_fwspec *fwspec = dev->iommu_fwspec; 696 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 697 unsigned int i; 698 699 for (i = 0; i < fwspec->num_ids; ++i) 700 ipmmu_utlb_disable(domain, fwspec->ids[i]); 701 702 /* 703 * TODO: Optimize by disabling the context when no device is attached. 704 */ 705 } 706 707 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova, 708 phys_addr_t paddr, size_t size, int prot) 709 { 710 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 711 712 if (!domain) 713 return -ENODEV; 714 715 return domain->iop->map(domain->iop, iova, paddr, size, prot); 716 } 717 718 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova, 719 size_t size) 720 { 721 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 722 723 return domain->iop->unmap(domain->iop, iova, size); 724 } 725 726 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain) 727 { 728 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 729 730 if (domain->mmu) 731 ipmmu_tlb_flush_all(domain); 732 } 733 734 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain, 735 dma_addr_t iova) 736 { 737 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); 738 739 /* TODO: Is locking needed ? */ 740 741 return domain->iop->iova_to_phys(domain->iop, iova); 742 } 743 744 static int ipmmu_init_platform_device(struct device *dev, 745 struct of_phandle_args *args) 746 { 747 struct platform_device *ipmmu_pdev; 748 749 ipmmu_pdev = of_find_device_by_node(args->np); 750 if (!ipmmu_pdev) 751 return -ENODEV; 752 753 dev->iommu_fwspec->iommu_priv = platform_get_drvdata(ipmmu_pdev); 754 return 0; 755 } 756 757 static bool ipmmu_slave_whitelist(struct device *dev) 758 { 759 /* By default, do not allow use of IPMMU */ 760 return false; 761 } 762 763 static const struct soc_device_attribute soc_rcar_gen3[] = { 764 { .soc_id = "r8a7795", }, 765 { .soc_id = "r8a7796", }, 766 { .soc_id = "r8a77965", }, 767 { .soc_id = "r8a77970", }, 768 { .soc_id = "r8a77995", }, 769 { /* sentinel */ } 770 }; 771 772 static int ipmmu_of_xlate(struct device *dev, 773 struct of_phandle_args *spec) 774 { 775 /* For R-Car Gen3 use a white list to opt-in slave devices */ 776 if (soc_device_match(soc_rcar_gen3) && !ipmmu_slave_whitelist(dev)) 777 return -ENODEV; 778 779 iommu_fwspec_add_ids(dev, spec->args, 1); 780 781 /* Initialize once - xlate() will call multiple times */ 782 if (to_ipmmu(dev)) 783 return 0; 784 785 return ipmmu_init_platform_device(dev, spec); 786 } 787 788 static int ipmmu_init_arm_mapping(struct device *dev) 789 { 790 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 791 struct iommu_group *group; 792 int ret; 793 794 /* Create a device group and add the device to it. */ 795 group = iommu_group_alloc(); 796 if (IS_ERR(group)) { 797 dev_err(dev, "Failed to allocate IOMMU group\n"); 798 return PTR_ERR(group); 799 } 800 801 ret = iommu_group_add_device(group, dev); 802 iommu_group_put(group); 803 804 if (ret < 0) { 805 dev_err(dev, "Failed to add device to IPMMU group\n"); 806 return ret; 807 } 808 809 /* 810 * Create the ARM mapping, used by the ARM DMA mapping core to allocate 811 * VAs. This will allocate a corresponding IOMMU domain. 812 * 813 * TODO: 814 * - Create one mapping per context (TLB). 815 * - Make the mapping size configurable ? We currently use a 2GB mapping 816 * at a 1GB offset to ensure that NULL VAs will fault. 817 */ 818 if (!mmu->mapping) { 819 struct dma_iommu_mapping *mapping; 820 821 mapping = arm_iommu_create_mapping(&platform_bus_type, 822 SZ_1G, SZ_2G); 823 if (IS_ERR(mapping)) { 824 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); 825 ret = PTR_ERR(mapping); 826 goto error; 827 } 828 829 mmu->mapping = mapping; 830 } 831 832 /* Attach the ARM VA mapping to the device. */ 833 ret = arm_iommu_attach_device(dev, mmu->mapping); 834 if (ret < 0) { 835 dev_err(dev, "Failed to attach device to VA mapping\n"); 836 goto error; 837 } 838 839 return 0; 840 841 error: 842 iommu_group_remove_device(dev); 843 if (mmu->mapping) 844 arm_iommu_release_mapping(mmu->mapping); 845 846 return ret; 847 } 848 849 static int ipmmu_add_device(struct device *dev) 850 { 851 struct iommu_group *group; 852 853 /* 854 * Only let through devices that have been verified in xlate() 855 */ 856 if (!to_ipmmu(dev)) 857 return -ENODEV; 858 859 if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)) 860 return ipmmu_init_arm_mapping(dev); 861 862 group = iommu_group_get_for_dev(dev); 863 if (IS_ERR(group)) 864 return PTR_ERR(group); 865 866 iommu_group_put(group); 867 return 0; 868 } 869 870 static void ipmmu_remove_device(struct device *dev) 871 { 872 arm_iommu_detach_device(dev); 873 iommu_group_remove_device(dev); 874 } 875 876 static struct iommu_group *ipmmu_find_group(struct device *dev) 877 { 878 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); 879 struct iommu_group *group; 880 881 if (mmu->group) 882 return iommu_group_ref_get(mmu->group); 883 884 group = iommu_group_alloc(); 885 if (!IS_ERR(group)) 886 mmu->group = group; 887 888 return group; 889 } 890 891 static const struct iommu_ops ipmmu_ops = { 892 .domain_alloc = ipmmu_domain_alloc, 893 .domain_free = ipmmu_domain_free, 894 .attach_dev = ipmmu_attach_device, 895 .detach_dev = ipmmu_detach_device, 896 .map = ipmmu_map, 897 .unmap = ipmmu_unmap, 898 .flush_iotlb_all = ipmmu_iotlb_sync, 899 .iotlb_sync = ipmmu_iotlb_sync, 900 .iova_to_phys = ipmmu_iova_to_phys, 901 .add_device = ipmmu_add_device, 902 .remove_device = ipmmu_remove_device, 903 .device_group = ipmmu_find_group, 904 .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, 905 .of_xlate = ipmmu_of_xlate, 906 }; 907 908 /* ----------------------------------------------------------------------------- 909 * Probe/remove and init 910 */ 911 912 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) 913 { 914 unsigned int i; 915 916 /* Disable all contexts. */ 917 for (i = 0; i < mmu->num_ctx; ++i) 918 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0); 919 } 920 921 static const struct ipmmu_features ipmmu_features_default = { 922 .use_ns_alias_offset = true, 923 .has_cache_leaf_nodes = false, 924 .number_of_contexts = 1, /* software only tested with one context */ 925 .setup_imbuscr = true, 926 .twobit_imttbcr_sl0 = false, 927 .reserved_context = false, 928 }; 929 930 static const struct ipmmu_features ipmmu_features_rcar_gen3 = { 931 .use_ns_alias_offset = false, 932 .has_cache_leaf_nodes = true, 933 .number_of_contexts = 8, 934 .setup_imbuscr = false, 935 .twobit_imttbcr_sl0 = true, 936 .reserved_context = true, 937 }; 938 939 static const struct of_device_id ipmmu_of_ids[] = { 940 { 941 .compatible = "renesas,ipmmu-vmsa", 942 .data = &ipmmu_features_default, 943 }, { 944 .compatible = "renesas,ipmmu-r8a7795", 945 .data = &ipmmu_features_rcar_gen3, 946 }, { 947 .compatible = "renesas,ipmmu-r8a7796", 948 .data = &ipmmu_features_rcar_gen3, 949 }, { 950 .compatible = "renesas,ipmmu-r8a77965", 951 .data = &ipmmu_features_rcar_gen3, 952 }, { 953 .compatible = "renesas,ipmmu-r8a77970", 954 .data = &ipmmu_features_rcar_gen3, 955 }, { 956 .compatible = "renesas,ipmmu-r8a77995", 957 .data = &ipmmu_features_rcar_gen3, 958 }, { 959 /* Terminator */ 960 }, 961 }; 962 963 MODULE_DEVICE_TABLE(of, ipmmu_of_ids); 964 965 static int ipmmu_probe(struct platform_device *pdev) 966 { 967 struct ipmmu_vmsa_device *mmu; 968 struct resource *res; 969 int irq; 970 int ret; 971 972 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); 973 if (!mmu) { 974 dev_err(&pdev->dev, "cannot allocate device data\n"); 975 return -ENOMEM; 976 } 977 978 mmu->dev = &pdev->dev; 979 mmu->num_utlbs = 48; 980 spin_lock_init(&mmu->lock); 981 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); 982 mmu->features = of_device_get_match_data(&pdev->dev); 983 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 984 985 /* Map I/O memory and request IRQ. */ 986 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 987 mmu->base = devm_ioremap_resource(&pdev->dev, res); 988 if (IS_ERR(mmu->base)) 989 return PTR_ERR(mmu->base); 990 991 /* 992 * The IPMMU has two register banks, for secure and non-secure modes. 993 * The bank mapped at the beginning of the IPMMU address space 994 * corresponds to the running mode of the CPU. When running in secure 995 * mode the non-secure register bank is also available at an offset. 996 * 997 * Secure mode operation isn't clearly documented and is thus currently 998 * not implemented in the driver. Furthermore, preliminary tests of 999 * non-secure operation with the main register bank were not successful. 1000 * Offset the registers base unconditionally to point to the non-secure 1001 * alias space for now. 1002 */ 1003 if (mmu->features->use_ns_alias_offset) 1004 mmu->base += IM_NS_ALIAS_OFFSET; 1005 1006 mmu->num_ctx = min_t(unsigned int, IPMMU_CTX_MAX, 1007 mmu->features->number_of_contexts); 1008 1009 irq = platform_get_irq(pdev, 0); 1010 1011 /* 1012 * Determine if this IPMMU instance is a root device by checking for 1013 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. 1014 */ 1015 if (!mmu->features->has_cache_leaf_nodes || 1016 !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL)) 1017 mmu->root = mmu; 1018 else 1019 mmu->root = ipmmu_find_root(); 1020 1021 /* 1022 * Wait until the root device has been registered for sure. 1023 */ 1024 if (!mmu->root) 1025 return -EPROBE_DEFER; 1026 1027 /* Root devices have mandatory IRQs */ 1028 if (ipmmu_is_root(mmu)) { 1029 if (irq < 0) { 1030 dev_err(&pdev->dev, "no IRQ found\n"); 1031 return irq; 1032 } 1033 1034 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, 1035 dev_name(&pdev->dev), mmu); 1036 if (ret < 0) { 1037 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); 1038 return ret; 1039 } 1040 1041 ipmmu_device_reset(mmu); 1042 1043 if (mmu->features->reserved_context) { 1044 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n"); 1045 set_bit(0, mmu->ctx); 1046 } 1047 } 1048 1049 /* 1050 * Register the IPMMU to the IOMMU subsystem in the following cases: 1051 * - R-Car Gen2 IPMMU (all devices registered) 1052 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) 1053 */ 1054 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) { 1055 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, 1056 dev_name(&pdev->dev)); 1057 if (ret) 1058 return ret; 1059 1060 iommu_device_set_ops(&mmu->iommu, &ipmmu_ops); 1061 iommu_device_set_fwnode(&mmu->iommu, 1062 &pdev->dev.of_node->fwnode); 1063 1064 ret = iommu_device_register(&mmu->iommu); 1065 if (ret) 1066 return ret; 1067 1068 #if defined(CONFIG_IOMMU_DMA) 1069 if (!iommu_present(&platform_bus_type)) 1070 bus_set_iommu(&platform_bus_type, &ipmmu_ops); 1071 #endif 1072 } 1073 1074 /* 1075 * We can't create the ARM mapping here as it requires the bus to have 1076 * an IOMMU, which only happens when bus_set_iommu() is called in 1077 * ipmmu_init() after the probe function returns. 1078 */ 1079 1080 platform_set_drvdata(pdev, mmu); 1081 1082 return 0; 1083 } 1084 1085 static int ipmmu_remove(struct platform_device *pdev) 1086 { 1087 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev); 1088 1089 iommu_device_sysfs_remove(&mmu->iommu); 1090 iommu_device_unregister(&mmu->iommu); 1091 1092 arm_iommu_release_mapping(mmu->mapping); 1093 1094 ipmmu_device_reset(mmu); 1095 1096 return 0; 1097 } 1098 1099 static struct platform_driver ipmmu_driver = { 1100 .driver = { 1101 .name = "ipmmu-vmsa", 1102 .of_match_table = of_match_ptr(ipmmu_of_ids), 1103 }, 1104 .probe = ipmmu_probe, 1105 .remove = ipmmu_remove, 1106 }; 1107 1108 static int __init ipmmu_init(void) 1109 { 1110 struct device_node *np; 1111 static bool setup_done; 1112 int ret; 1113 1114 if (setup_done) 1115 return 0; 1116 1117 np = of_find_matching_node(NULL, ipmmu_of_ids); 1118 if (!np) 1119 return 0; 1120 1121 of_node_put(np); 1122 1123 ret = platform_driver_register(&ipmmu_driver); 1124 if (ret < 0) 1125 return ret; 1126 1127 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) 1128 if (!iommu_present(&platform_bus_type)) 1129 bus_set_iommu(&platform_bus_type, &ipmmu_ops); 1130 #endif 1131 1132 setup_done = true; 1133 return 0; 1134 } 1135 1136 static void __exit ipmmu_exit(void) 1137 { 1138 return platform_driver_unregister(&ipmmu_driver); 1139 } 1140 1141 subsys_initcall(ipmmu_init); 1142 module_exit(ipmmu_exit); 1143 1144 MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU"); 1145 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 1146 MODULE_LICENSE("GPL v2"); 1147