1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES.
3  */
4 #ifndef _UAPI_IOMMUFD_TEST_H
5 #define _UAPI_IOMMUFD_TEST_H
6 
7 #include <linux/types.h>
8 #include <linux/iommufd.h>
9 
10 enum {
11 	IOMMU_TEST_OP_ADD_RESERVED = 1,
12 	IOMMU_TEST_OP_MOCK_DOMAIN,
13 	IOMMU_TEST_OP_MD_CHECK_MAP,
14 	IOMMU_TEST_OP_MD_CHECK_REFS,
15 	IOMMU_TEST_OP_CREATE_ACCESS,
16 	IOMMU_TEST_OP_DESTROY_ACCESS_PAGES,
17 	IOMMU_TEST_OP_ACCESS_PAGES,
18 	IOMMU_TEST_OP_ACCESS_RW,
19 	IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT,
20 };
21 
22 enum {
23 	MOCK_APERTURE_START = 1UL << 24,
24 	MOCK_APERTURE_LAST = (1UL << 31) - 1,
25 };
26 
27 enum {
28 	MOCK_FLAGS_ACCESS_WRITE = 1 << 0,
29 	MOCK_FLAGS_ACCESS_SYZ = 1 << 16,
30 };
31 
32 enum {
33 	MOCK_ACCESS_RW_WRITE = 1 << 0,
34 	MOCK_ACCESS_RW_SLOW_PATH = 1 << 2,
35 };
36 
37 enum {
38 	MOCK_FLAGS_ACCESS_CREATE_NEEDS_PIN_PAGES = 1 << 0,
39 };
40 
41 struct iommu_test_cmd {
42 	__u32 size;
43 	__u32 op;
44 	__u32 id;
45 	__u32 __reserved;
46 	union {
47 		struct {
48 			__aligned_u64 start;
49 			__aligned_u64 length;
50 		} add_reserved;
51 		struct {
52 			__u32 out_device_id;
53 			__u32 out_hwpt_id;
54 		} mock_domain;
55 		struct {
56 			__aligned_u64 iova;
57 			__aligned_u64 length;
58 			__aligned_u64 uptr;
59 		} check_map;
60 		struct {
61 			__aligned_u64 length;
62 			__aligned_u64 uptr;
63 			__u32 refs;
64 		} check_refs;
65 		struct {
66 			__u32 out_access_fd;
67 			__u32 flags;
68 		} create_access;
69 		struct {
70 			__u32 access_pages_id;
71 		} destroy_access_pages;
72 		struct {
73 			__u32 flags;
74 			__u32 out_access_pages_id;
75 			__aligned_u64 iova;
76 			__aligned_u64 length;
77 			__aligned_u64 uptr;
78 		} access_pages;
79 		struct {
80 			__aligned_u64 iova;
81 			__aligned_u64 length;
82 			__aligned_u64 uptr;
83 			__u32 flags;
84 		} access_rw;
85 		struct {
86 			__u32 limit;
87 		} memory_limit;
88 	};
89 	__u32 last;
90 };
91 #define IOMMU_TEST_CMD _IO(IOMMUFD_TYPE, IOMMUFD_CMD_BASE + 32)
92 
93 #endif
94