1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CPU-agnostic ARM page table allocator. 4 * 5 * ARMv7 Short-descriptor format, supporting 6 * - Basic memory attributes 7 * - Simplified access permissions (AP[2:1] model) 8 * - Backwards-compatible TEX remap 9 * - Large pages/supersections (if indicated by the caller) 10 * 11 * Not supporting: 12 * - Legacy access permissions (AP[2:0] model) 13 * 14 * Almost certainly never supporting: 15 * - PXN 16 * - Domains 17 * 18 * Copyright (C) 2014-2015 ARM Limited 19 * Copyright (c) 2014-2015 MediaTek Inc. 20 */ 21 22 #define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt 23 24 #include <linux/atomic.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/gfp.h> 27 #include <linux/io-pgtable.h> 28 #include <linux/iommu.h> 29 #include <linux/kernel.h> 30 #include <linux/kmemleak.h> 31 #include <linux/sizes.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 #include <linux/types.h> 35 36 #include <asm/barrier.h> 37 38 /* Struct accessors */ 39 #define io_pgtable_to_data(x) \ 40 container_of((x), struct arm_v7s_io_pgtable, iop) 41 42 #define io_pgtable_ops_to_data(x) \ 43 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) 44 45 /* 46 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2, 47 * and 12 bits in a page. 48 * MediaTek extend 2 bits to reach 34bits, 14 bits at lvl1 and 8 bits at lvl2. 49 */ 50 #define ARM_V7S_ADDR_BITS 32 51 #define _ARM_V7S_LVL_BITS(lvl, cfg) ((lvl) == 1 ? ((cfg)->ias - 20) : 8) 52 #define ARM_V7S_LVL_SHIFT(lvl) ((lvl) == 1 ? 20 : 12) 53 #define ARM_V7S_TABLE_SHIFT 10 54 55 #define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl, cfg)) 56 #define ARM_V7S_TABLE_SIZE(lvl, cfg) \ 57 (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte)) 58 59 #define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl)) 60 #define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl))) 61 #define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT)) 62 #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1) 63 #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \ 64 int _l = lvl; \ 65 ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \ 66 }) 67 68 /* 69 * Large page/supersection entries are effectively a block of 16 page/section 70 * entries, along the lines of the LPAE contiguous hint, but all with the 71 * same output address. For want of a better common name we'll call them 72 * "contiguous" versions of their respective page/section entries here, but 73 * noting the distinction (WRT to TLB maintenance) that they represent *one* 74 * entry repeated 16 times, not 16 separate entries (as in the LPAE case). 75 */ 76 #define ARM_V7S_CONT_PAGES 16 77 78 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */ 79 #define ARM_V7S_PTE_TYPE_TABLE 0x1 80 #define ARM_V7S_PTE_TYPE_PAGE 0x2 81 #define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1 82 83 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0) 84 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) \ 85 ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE)) 86 87 /* Page table bits */ 88 #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl))) 89 #define ARM_V7S_ATTR_B BIT(2) 90 #define ARM_V7S_ATTR_C BIT(3) 91 #define ARM_V7S_ATTR_NS_TABLE BIT(3) 92 #define ARM_V7S_ATTR_NS_SECTION BIT(19) 93 94 #define ARM_V7S_CONT_SECTION BIT(18) 95 #define ARM_V7S_CONT_PAGE_XN_SHIFT 15 96 97 /* 98 * The attribute bits are consistently ordered*, but occupy bits [17:10] of 99 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual 100 * fields relative to that 8-bit block, plus a total shift relative to the PTE. 101 */ 102 #define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6) 103 104 #define ARM_V7S_ATTR_MASK 0xff 105 #define ARM_V7S_ATTR_AP0 BIT(0) 106 #define ARM_V7S_ATTR_AP1 BIT(1) 107 #define ARM_V7S_ATTR_AP2 BIT(5) 108 #define ARM_V7S_ATTR_S BIT(6) 109 #define ARM_V7S_ATTR_NG BIT(7) 110 #define ARM_V7S_TEX_SHIFT 2 111 #define ARM_V7S_TEX_MASK 0x7 112 #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) 113 114 /* MediaTek extend the bits below for PA 32bit/33bit/34bit */ 115 #define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) 116 #define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) 117 #define ARM_V7S_ATTR_MTK_PA_BIT34 BIT(5) 118 119 /* *well, except for TEX on level 2 large pages, of course :( */ 120 #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 121 #define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT) 122 123 /* Simplified access permissions */ 124 #define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0 125 #define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1 126 #define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2 127 128 /* Register bits */ 129 #define ARM_V7S_RGN_NC 0 130 #define ARM_V7S_RGN_WBWA 1 131 #define ARM_V7S_RGN_WT 2 132 #define ARM_V7S_RGN_WB 3 133 134 #define ARM_V7S_PRRR_TYPE_DEVICE 1 135 #define ARM_V7S_PRRR_TYPE_NORMAL 2 136 #define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2)) 137 #define ARM_V7S_PRRR_DS0 BIT(16) 138 #define ARM_V7S_PRRR_DS1 BIT(17) 139 #define ARM_V7S_PRRR_NS0 BIT(18) 140 #define ARM_V7S_PRRR_NS1 BIT(19) 141 #define ARM_V7S_PRRR_NOS(n) BIT((n) + 24) 142 143 #define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2)) 144 #define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16)) 145 146 #define ARM_V7S_TTBR_S BIT(1) 147 #define ARM_V7S_TTBR_NOS BIT(5) 148 #define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3) 149 #define ARM_V7S_TTBR_IRGN_ATTR(attr) \ 150 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1)) 151 152 #ifdef CONFIG_ZONE_DMA32 153 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA32 154 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA32 155 #else 156 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA 157 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA 158 #endif 159 160 typedef u32 arm_v7s_iopte; 161 162 static bool selftest_running; 163 164 struct arm_v7s_io_pgtable { 165 struct io_pgtable iop; 166 167 arm_v7s_iopte *pgd; 168 struct kmem_cache *l2_tables; 169 spinlock_t split_lock; 170 }; 171 172 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl); 173 174 static dma_addr_t __arm_v7s_dma_addr(void *pages) 175 { 176 return (dma_addr_t)virt_to_phys(pages); 177 } 178 179 static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg) 180 { 181 return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 182 (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT); 183 } 184 185 static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, 186 struct io_pgtable_cfg *cfg) 187 { 188 arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl); 189 190 if (!arm_v7s_is_mtk_enabled(cfg)) 191 return pte; 192 193 if (paddr & BIT_ULL(32)) 194 pte |= ARM_V7S_ATTR_MTK_PA_BIT32; 195 if (paddr & BIT_ULL(33)) 196 pte |= ARM_V7S_ATTR_MTK_PA_BIT33; 197 if (paddr & BIT_ULL(34)) 198 pte |= ARM_V7S_ATTR_MTK_PA_BIT34; 199 return pte; 200 } 201 202 static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, 203 struct io_pgtable_cfg *cfg) 204 { 205 arm_v7s_iopte mask; 206 phys_addr_t paddr; 207 208 if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) 209 mask = ARM_V7S_TABLE_MASK; 210 else if (arm_v7s_pte_is_cont(pte, lvl)) 211 mask = ARM_V7S_LVL_MASK(lvl) * ARM_V7S_CONT_PAGES; 212 else 213 mask = ARM_V7S_LVL_MASK(lvl); 214 215 paddr = pte & mask; 216 if (!arm_v7s_is_mtk_enabled(cfg)) 217 return paddr; 218 219 if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) 220 paddr |= BIT_ULL(32); 221 if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) 222 paddr |= BIT_ULL(33); 223 if (pte & ARM_V7S_ATTR_MTK_PA_BIT34) 224 paddr |= BIT_ULL(34); 225 return paddr; 226 } 227 228 static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl, 229 struct arm_v7s_io_pgtable *data) 230 { 231 return phys_to_virt(iopte_to_paddr(pte, lvl, &data->iop.cfg)); 232 } 233 234 static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp, 235 struct arm_v7s_io_pgtable *data) 236 { 237 struct io_pgtable_cfg *cfg = &data->iop.cfg; 238 struct device *dev = cfg->iommu_dev; 239 phys_addr_t phys; 240 dma_addr_t dma; 241 size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg); 242 void *table = NULL; 243 244 if (lvl == 1) 245 table = (void *)__get_free_pages( 246 __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size)); 247 else if (lvl == 2) 248 table = kmem_cache_zalloc(data->l2_tables, gfp); 249 phys = virt_to_phys(table); 250 if (phys != (arm_v7s_iopte)phys) { 251 /* Doesn't fit in PTE */ 252 dev_err(dev, "Page table does not fit in PTE: %pa", &phys); 253 goto out_free; 254 } 255 if (table && !cfg->coherent_walk) { 256 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE); 257 if (dma_mapping_error(dev, dma)) 258 goto out_free; 259 /* 260 * We depend on the IOMMU being able to work with any physical 261 * address directly, so if the DMA layer suggests otherwise by 262 * translating or truncating them, that bodes very badly... 263 */ 264 if (dma != phys) 265 goto out_unmap; 266 } 267 if (lvl == 2) 268 kmemleak_ignore(table); 269 return table; 270 271 out_unmap: 272 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"); 273 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); 274 out_free: 275 if (lvl == 1) 276 free_pages((unsigned long)table, get_order(size)); 277 else 278 kmem_cache_free(data->l2_tables, table); 279 return NULL; 280 } 281 282 static void __arm_v7s_free_table(void *table, int lvl, 283 struct arm_v7s_io_pgtable *data) 284 { 285 struct io_pgtable_cfg *cfg = &data->iop.cfg; 286 struct device *dev = cfg->iommu_dev; 287 size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg); 288 289 if (!cfg->coherent_walk) 290 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size, 291 DMA_TO_DEVICE); 292 if (lvl == 1) 293 free_pages((unsigned long)table, get_order(size)); 294 else 295 kmem_cache_free(data->l2_tables, table); 296 } 297 298 static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries, 299 struct io_pgtable_cfg *cfg) 300 { 301 if (cfg->coherent_walk) 302 return; 303 304 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep), 305 num_entries * sizeof(*ptep), DMA_TO_DEVICE); 306 } 307 static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte, 308 int num_entries, struct io_pgtable_cfg *cfg) 309 { 310 int i; 311 312 for (i = 0; i < num_entries; i++) 313 ptep[i] = pte; 314 315 __arm_v7s_pte_sync(ptep, num_entries, cfg); 316 } 317 318 static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, 319 struct io_pgtable_cfg *cfg) 320 { 321 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS); 322 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S; 323 324 if (!(prot & IOMMU_MMIO)) 325 pte |= ARM_V7S_ATTR_TEX(1); 326 if (ap) { 327 pte |= ARM_V7S_PTE_AF; 328 if (!(prot & IOMMU_PRIV)) 329 pte |= ARM_V7S_PTE_AP_UNPRIV; 330 if (!(prot & IOMMU_WRITE)) 331 pte |= ARM_V7S_PTE_AP_RDONLY; 332 } 333 pte <<= ARM_V7S_ATTR_SHIFT(lvl); 334 335 if ((prot & IOMMU_NOEXEC) && ap) 336 pte |= ARM_V7S_ATTR_XN(lvl); 337 if (prot & IOMMU_MMIO) 338 pte |= ARM_V7S_ATTR_B; 339 else if (prot & IOMMU_CACHE) 340 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C; 341 342 pte |= ARM_V7S_PTE_TYPE_PAGE; 343 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) 344 pte |= ARM_V7S_ATTR_NS_SECTION; 345 346 return pte; 347 } 348 349 static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl) 350 { 351 int prot = IOMMU_READ; 352 arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl); 353 354 if (!(attr & ARM_V7S_PTE_AP_RDONLY)) 355 prot |= IOMMU_WRITE; 356 if (!(attr & ARM_V7S_PTE_AP_UNPRIV)) 357 prot |= IOMMU_PRIV; 358 if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0) 359 prot |= IOMMU_MMIO; 360 else if (pte & ARM_V7S_ATTR_C) 361 prot |= IOMMU_CACHE; 362 if (pte & ARM_V7S_ATTR_XN(lvl)) 363 prot |= IOMMU_NOEXEC; 364 365 return prot; 366 } 367 368 static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl) 369 { 370 if (lvl == 1) { 371 pte |= ARM_V7S_CONT_SECTION; 372 } else if (lvl == 2) { 373 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl); 374 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK; 375 376 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE; 377 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) | 378 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) | 379 ARM_V7S_PTE_TYPE_CONT_PAGE; 380 } 381 return pte; 382 } 383 384 static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl) 385 { 386 if (lvl == 1) { 387 pte &= ~ARM_V7S_CONT_SECTION; 388 } else if (lvl == 2) { 389 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT); 390 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK << 391 ARM_V7S_CONT_PAGE_TEX_SHIFT); 392 393 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE; 394 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) | 395 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) | 396 ARM_V7S_PTE_TYPE_PAGE; 397 } 398 return pte; 399 } 400 401 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl) 402 { 403 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl)) 404 return pte & ARM_V7S_CONT_SECTION; 405 else if (lvl == 2) 406 return !(pte & ARM_V7S_PTE_TYPE_PAGE); 407 return false; 408 } 409 410 static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *, 411 struct iommu_iotlb_gather *, unsigned long, 412 size_t, int, arm_v7s_iopte *); 413 414 static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data, 415 unsigned long iova, phys_addr_t paddr, int prot, 416 int lvl, int num_entries, arm_v7s_iopte *ptep) 417 { 418 struct io_pgtable_cfg *cfg = &data->iop.cfg; 419 arm_v7s_iopte pte; 420 int i; 421 422 for (i = 0; i < num_entries; i++) 423 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) { 424 /* 425 * We need to unmap and free the old table before 426 * overwriting it with a block entry. 427 */ 428 arm_v7s_iopte *tblp; 429 size_t sz = ARM_V7S_BLOCK_SIZE(lvl); 430 431 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl, cfg); 432 if (WARN_ON(__arm_v7s_unmap(data, NULL, iova + i * sz, 433 sz, lvl, tblp) != sz)) 434 return -EINVAL; 435 } else if (ptep[i]) { 436 /* We require an unmap first */ 437 WARN_ON(!selftest_running); 438 return -EEXIST; 439 } 440 441 pte = arm_v7s_prot_to_pte(prot, lvl, cfg); 442 if (num_entries > 1) 443 pte = arm_v7s_pte_to_cont(pte, lvl); 444 445 pte |= paddr_to_iopte(paddr, lvl, cfg); 446 447 __arm_v7s_set_pte(ptep, pte, num_entries, cfg); 448 return 0; 449 } 450 451 static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table, 452 arm_v7s_iopte *ptep, 453 arm_v7s_iopte curr, 454 struct io_pgtable_cfg *cfg) 455 { 456 arm_v7s_iopte old, new; 457 458 new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE; 459 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) 460 new |= ARM_V7S_ATTR_NS_TABLE; 461 462 /* 463 * Ensure the table itself is visible before its PTE can be. 464 * Whilst we could get away with cmpxchg64_release below, this 465 * doesn't have any ordering semantics when !CONFIG_SMP. 466 */ 467 dma_wmb(); 468 469 old = cmpxchg_relaxed(ptep, curr, new); 470 __arm_v7s_pte_sync(ptep, 1, cfg); 471 472 return old; 473 } 474 475 static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova, 476 phys_addr_t paddr, size_t size, int prot, 477 int lvl, arm_v7s_iopte *ptep, gfp_t gfp) 478 { 479 struct io_pgtable_cfg *cfg = &data->iop.cfg; 480 arm_v7s_iopte pte, *cptep; 481 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); 482 483 /* Find our entry at the current level */ 484 ptep += ARM_V7S_LVL_IDX(iova, lvl, cfg); 485 486 /* If we can install a leaf entry at this level, then do so */ 487 if (num_entries) 488 return arm_v7s_init_pte(data, iova, paddr, prot, 489 lvl, num_entries, ptep); 490 491 /* We can't allocate tables at the final level */ 492 if (WARN_ON(lvl == 2)) 493 return -EINVAL; 494 495 /* Grab a pointer to the next level */ 496 pte = READ_ONCE(*ptep); 497 if (!pte) { 498 cptep = __arm_v7s_alloc_table(lvl + 1, gfp, data); 499 if (!cptep) 500 return -ENOMEM; 501 502 pte = arm_v7s_install_table(cptep, ptep, 0, cfg); 503 if (pte) 504 __arm_v7s_free_table(cptep, lvl + 1, data); 505 } else { 506 /* We've no easy way of knowing if it's synced yet, so... */ 507 __arm_v7s_pte_sync(ptep, 1, cfg); 508 } 509 510 if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) { 511 cptep = iopte_deref(pte, lvl, data); 512 } else if (pte) { 513 /* We require an unmap first */ 514 WARN_ON(!selftest_running); 515 return -EEXIST; 516 } 517 518 /* Rinse, repeat */ 519 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep, gfp); 520 } 521 522 static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova, 523 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 524 { 525 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 526 int ret; 527 528 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) || 529 paddr >= (1ULL << data->iop.cfg.oas))) 530 return -ERANGE; 531 532 /* If no access, then nothing to do */ 533 if (!(prot & (IOMMU_READ | IOMMU_WRITE))) 534 return 0; 535 536 ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd, gfp); 537 /* 538 * Synchronise all PTE updates for the new mapping before there's 539 * a chance for anything to kick off a table walk for the new iova. 540 */ 541 wmb(); 542 543 return ret; 544 } 545 546 static void arm_v7s_free_pgtable(struct io_pgtable *iop) 547 { 548 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop); 549 int i; 550 551 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1, &data->iop.cfg); i++) { 552 arm_v7s_iopte pte = data->pgd[i]; 553 554 if (ARM_V7S_PTE_IS_TABLE(pte, 1)) 555 __arm_v7s_free_table(iopte_deref(pte, 1, data), 556 2, data); 557 } 558 __arm_v7s_free_table(data->pgd, 1, data); 559 kmem_cache_destroy(data->l2_tables); 560 kfree(data); 561 } 562 563 static arm_v7s_iopte arm_v7s_split_cont(struct arm_v7s_io_pgtable *data, 564 unsigned long iova, int idx, int lvl, 565 arm_v7s_iopte *ptep) 566 { 567 struct io_pgtable *iop = &data->iop; 568 arm_v7s_iopte pte; 569 size_t size = ARM_V7S_BLOCK_SIZE(lvl); 570 int i; 571 572 /* Check that we didn't lose a race to get the lock */ 573 pte = *ptep; 574 if (!arm_v7s_pte_is_cont(pte, lvl)) 575 return pte; 576 577 ptep -= idx & (ARM_V7S_CONT_PAGES - 1); 578 pte = arm_v7s_cont_to_pte(pte, lvl); 579 for (i = 0; i < ARM_V7S_CONT_PAGES; i++) 580 ptep[i] = pte + i * size; 581 582 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg); 583 584 size *= ARM_V7S_CONT_PAGES; 585 io_pgtable_tlb_flush_walk(iop, iova, size, size); 586 return pte; 587 } 588 589 static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data, 590 struct iommu_iotlb_gather *gather, 591 unsigned long iova, size_t size, 592 arm_v7s_iopte blk_pte, 593 arm_v7s_iopte *ptep) 594 { 595 struct io_pgtable_cfg *cfg = &data->iop.cfg; 596 arm_v7s_iopte pte, *tablep; 597 int i, unmap_idx, num_entries, num_ptes; 598 599 tablep = __arm_v7s_alloc_table(2, GFP_ATOMIC, data); 600 if (!tablep) 601 return 0; /* Bytes unmapped */ 602 603 num_ptes = ARM_V7S_PTES_PER_LVL(2, cfg); 604 num_entries = size >> ARM_V7S_LVL_SHIFT(2); 605 unmap_idx = ARM_V7S_LVL_IDX(iova, 2, cfg); 606 607 pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg); 608 if (num_entries > 1) 609 pte = arm_v7s_pte_to_cont(pte, 2); 610 611 for (i = 0; i < num_ptes; i += num_entries, pte += size) { 612 /* Unmap! */ 613 if (i == unmap_idx) 614 continue; 615 616 __arm_v7s_set_pte(&tablep[i], pte, num_entries, cfg); 617 } 618 619 pte = arm_v7s_install_table(tablep, ptep, blk_pte, cfg); 620 if (pte != blk_pte) { 621 __arm_v7s_free_table(tablep, 2, data); 622 623 if (!ARM_V7S_PTE_IS_TABLE(pte, 1)) 624 return 0; 625 626 tablep = iopte_deref(pte, 1, data); 627 return __arm_v7s_unmap(data, gather, iova, size, 2, tablep); 628 } 629 630 io_pgtable_tlb_add_page(&data->iop, gather, iova, size); 631 return size; 632 } 633 634 static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data, 635 struct iommu_iotlb_gather *gather, 636 unsigned long iova, size_t size, int lvl, 637 arm_v7s_iopte *ptep) 638 { 639 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES]; 640 struct io_pgtable *iop = &data->iop; 641 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); 642 643 /* Something went horribly wrong and we ran out of page table */ 644 if (WARN_ON(lvl > 2)) 645 return 0; 646 647 idx = ARM_V7S_LVL_IDX(iova, lvl, &iop->cfg); 648 ptep += idx; 649 do { 650 pte[i] = READ_ONCE(ptep[i]); 651 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(pte[i]))) 652 return 0; 653 } while (++i < num_entries); 654 655 /* 656 * If we've hit a contiguous 'large page' entry at this level, it 657 * needs splitting first, unless we're unmapping the whole lot. 658 * 659 * For splitting, we can't rewrite 16 PTEs atomically, and since we 660 * can't necessarily assume TEX remap we don't have a software bit to 661 * mark live entries being split. In practice (i.e. DMA API code), we 662 * will never be splitting large pages anyway, so just wrap this edge 663 * case in a lock for the sake of correctness and be done with it. 664 */ 665 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) { 666 unsigned long flags; 667 668 spin_lock_irqsave(&data->split_lock, flags); 669 pte[0] = arm_v7s_split_cont(data, iova, idx, lvl, ptep); 670 spin_unlock_irqrestore(&data->split_lock, flags); 671 } 672 673 /* If the size matches this level, we're in the right place */ 674 if (num_entries) { 675 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl); 676 677 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg); 678 679 for (i = 0; i < num_entries; i++) { 680 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) { 681 /* Also flush any partial walks */ 682 io_pgtable_tlb_flush_walk(iop, iova, blk_size, 683 ARM_V7S_BLOCK_SIZE(lvl + 1)); 684 ptep = iopte_deref(pte[i], lvl, data); 685 __arm_v7s_free_table(ptep, lvl + 1, data); 686 } else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) { 687 /* 688 * Order the PTE update against queueing the IOVA, to 689 * guarantee that a flush callback from a different CPU 690 * has observed it before the TLBIALL can be issued. 691 */ 692 smp_wmb(); 693 } else { 694 io_pgtable_tlb_add_page(iop, gather, iova, blk_size); 695 } 696 iova += blk_size; 697 } 698 return size; 699 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) { 700 /* 701 * Insert a table at the next level to map the old region, 702 * minus the part we want to unmap 703 */ 704 return arm_v7s_split_blk_unmap(data, gather, iova, size, pte[0], 705 ptep); 706 } 707 708 /* Keep on walkin' */ 709 ptep = iopte_deref(pte[0], lvl, data); 710 return __arm_v7s_unmap(data, gather, iova, size, lvl + 1, ptep); 711 } 712 713 static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova, 714 size_t size, struct iommu_iotlb_gather *gather) 715 { 716 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 717 718 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias))) 719 return 0; 720 721 return __arm_v7s_unmap(data, gather, iova, size, 1, data->pgd); 722 } 723 724 static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, 725 unsigned long iova) 726 { 727 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 728 arm_v7s_iopte *ptep = data->pgd, pte; 729 int lvl = 0; 730 u32 mask; 731 732 do { 733 ptep += ARM_V7S_LVL_IDX(iova, ++lvl, &data->iop.cfg); 734 pte = READ_ONCE(*ptep); 735 ptep = iopte_deref(pte, lvl, data); 736 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl)); 737 738 if (!ARM_V7S_PTE_IS_VALID(pte)) 739 return 0; 740 741 mask = ARM_V7S_LVL_MASK(lvl); 742 if (arm_v7s_pte_is_cont(pte, lvl)) 743 mask *= ARM_V7S_CONT_PAGES; 744 return iopte_to_paddr(pte, lvl, &data->iop.cfg) | (iova & ~mask); 745 } 746 747 static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, 748 void *cookie) 749 { 750 struct arm_v7s_io_pgtable *data; 751 752 if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) 753 return NULL; 754 755 if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS)) 756 return NULL; 757 758 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | 759 IO_PGTABLE_QUIRK_NO_PERMS | 760 IO_PGTABLE_QUIRK_ARM_MTK_EXT | 761 IO_PGTABLE_QUIRK_NON_STRICT)) 762 return NULL; 763 764 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ 765 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT && 766 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS)) 767 return NULL; 768 769 data = kmalloc(sizeof(*data), GFP_KERNEL); 770 if (!data) 771 return NULL; 772 773 spin_lock_init(&data->split_lock); 774 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", 775 ARM_V7S_TABLE_SIZE(2, cfg), 776 ARM_V7S_TABLE_SIZE(2, cfg), 777 ARM_V7S_TABLE_SLAB_FLAGS, NULL); 778 if (!data->l2_tables) 779 goto out_free_data; 780 781 data->iop.ops = (struct io_pgtable_ops) { 782 .map = arm_v7s_map, 783 .unmap = arm_v7s_unmap, 784 .iova_to_phys = arm_v7s_iova_to_phys, 785 }; 786 787 /* We have to do this early for __arm_v7s_alloc_table to work... */ 788 data->iop.cfg = *cfg; 789 790 /* 791 * Unless the IOMMU driver indicates supersection support by 792 * having SZ_16M set in the initial bitmap, they won't be used. 793 */ 794 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M; 795 796 /* TCR: T0SZ=0, EAE=0 (if applicable) */ 797 cfg->arm_v7s_cfg.tcr = 0; 798 799 /* 800 * TEX remap: the indices used map to the closest equivalent types 801 * under the non-TEX-remap interpretation of those attribute bits, 802 * excepting various implementation-defined aspects of shareability. 803 */ 804 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) | 805 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) | 806 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) | 807 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 | 808 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7); 809 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) | 810 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA); 811 812 /* Looking good; allocate a pgd */ 813 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data); 814 if (!data->pgd) 815 goto out_free_data; 816 817 /* Ensure the empty pgd is visible before any actual TTBR write */ 818 wmb(); 819 820 /* TTBR */ 821 cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S | 822 (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS | 823 ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) | 824 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) : 825 (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) | 826 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC))); 827 return &data->iop; 828 829 out_free_data: 830 kmem_cache_destroy(data->l2_tables); 831 kfree(data); 832 return NULL; 833 } 834 835 struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = { 836 .alloc = arm_v7s_alloc_pgtable, 837 .free = arm_v7s_free_pgtable, 838 }; 839 840 #ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST 841 842 static struct io_pgtable_cfg *cfg_cookie __initdata; 843 844 static void __init dummy_tlb_flush_all(void *cookie) 845 { 846 WARN_ON(cookie != cfg_cookie); 847 } 848 849 static void __init dummy_tlb_flush(unsigned long iova, size_t size, 850 size_t granule, void *cookie) 851 { 852 WARN_ON(cookie != cfg_cookie); 853 WARN_ON(!(size & cfg_cookie->pgsize_bitmap)); 854 } 855 856 static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather, 857 unsigned long iova, size_t granule, 858 void *cookie) 859 { 860 dummy_tlb_flush(iova, granule, granule, cookie); 861 } 862 863 static const struct iommu_flush_ops dummy_tlb_ops __initconst = { 864 .tlb_flush_all = dummy_tlb_flush_all, 865 .tlb_flush_walk = dummy_tlb_flush, 866 .tlb_add_page = dummy_tlb_add_page, 867 }; 868 869 #define __FAIL(ops) ({ \ 870 WARN(1, "selftest: test failed\n"); \ 871 selftest_running = false; \ 872 -EFAULT; \ 873 }) 874 875 static int __init arm_v7s_do_selftests(void) 876 { 877 struct io_pgtable_ops *ops; 878 struct io_pgtable_cfg cfg = { 879 .tlb = &dummy_tlb_ops, 880 .oas = 32, 881 .ias = 32, 882 .coherent_walk = true, 883 .quirks = IO_PGTABLE_QUIRK_ARM_NS, 884 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 885 }; 886 unsigned int iova, size, iova_start; 887 unsigned int i, loopnr = 0; 888 889 selftest_running = true; 890 891 cfg_cookie = &cfg; 892 893 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg); 894 if (!ops) { 895 pr_err("selftest: failed to allocate io pgtable ops\n"); 896 return -EINVAL; 897 } 898 899 /* 900 * Initial sanity checks. 901 * Empty page tables shouldn't provide any translations. 902 */ 903 if (ops->iova_to_phys(ops, 42)) 904 return __FAIL(ops); 905 906 if (ops->iova_to_phys(ops, SZ_1G + 42)) 907 return __FAIL(ops); 908 909 if (ops->iova_to_phys(ops, SZ_2G + 42)) 910 return __FAIL(ops); 911 912 /* 913 * Distinct mappings of different granule sizes. 914 */ 915 iova = 0; 916 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) { 917 size = 1UL << i; 918 if (ops->map(ops, iova, iova, size, IOMMU_READ | 919 IOMMU_WRITE | 920 IOMMU_NOEXEC | 921 IOMMU_CACHE, GFP_KERNEL)) 922 return __FAIL(ops); 923 924 /* Overlapping mappings */ 925 if (!ops->map(ops, iova, iova + size, size, 926 IOMMU_READ | IOMMU_NOEXEC, GFP_KERNEL)) 927 return __FAIL(ops); 928 929 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) 930 return __FAIL(ops); 931 932 iova += SZ_16M; 933 loopnr++; 934 } 935 936 /* Partial unmap */ 937 i = 1; 938 size = 1UL << __ffs(cfg.pgsize_bitmap); 939 while (i < loopnr) { 940 iova_start = i * SZ_16M; 941 if (ops->unmap(ops, iova_start + size, size, NULL) != size) 942 return __FAIL(ops); 943 944 /* Remap of partial unmap */ 945 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ, GFP_KERNEL)) 946 return __FAIL(ops); 947 948 if (ops->iova_to_phys(ops, iova_start + size + 42) 949 != (size + 42)) 950 return __FAIL(ops); 951 i++; 952 } 953 954 /* Full unmap */ 955 iova = 0; 956 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) { 957 size = 1UL << i; 958 959 if (ops->unmap(ops, iova, size, NULL) != size) 960 return __FAIL(ops); 961 962 if (ops->iova_to_phys(ops, iova + 42)) 963 return __FAIL(ops); 964 965 /* Remap full block */ 966 if (ops->map(ops, iova, iova, size, IOMMU_WRITE, GFP_KERNEL)) 967 return __FAIL(ops); 968 969 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) 970 return __FAIL(ops); 971 972 iova += SZ_16M; 973 } 974 975 free_io_pgtable_ops(ops); 976 977 selftest_running = false; 978 979 pr_info("self test ok\n"); 980 return 0; 981 } 982 subsys_initcall(arm_v7s_do_selftests); 983 #endif 984