1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * perf.h - performance monitor header 4 * 5 * Copyright (C) 2021 Intel Corporation 6 * 7 * Author: Lu Baolu <baolu.lu@linux.intel.com> 8 */ 9 10 enum latency_type { 11 DMAR_LATENCY_INV_IOTLB = 0, 12 DMAR_LATENCY_INV_DEVTLB, 13 DMAR_LATENCY_INV_IEC, 14 DMAR_LATENCY_PRQ, 15 DMAR_LATENCY_NUM 16 }; 17 18 enum latency_count { 19 COUNTS_10e2 = 0, /* < 0.1us */ 20 COUNTS_10e3, /* 0.1us ~ 1us */ 21 COUNTS_10e4, /* 1us ~ 10us */ 22 COUNTS_10e5, /* 10us ~ 100us */ 23 COUNTS_10e6, /* 100us ~ 1ms */ 24 COUNTS_10e7, /* 1ms ~ 10ms */ 25 COUNTS_10e8_plus, /* 10ms and plus*/ 26 COUNTS_MIN, 27 COUNTS_MAX, 28 COUNTS_SUM, 29 COUNTS_NUM 30 }; 31 32 struct latency_statistic { 33 bool enabled; 34 u64 counter[COUNTS_NUM]; 35 u64 samples; 36 }; 37 38 #ifdef CONFIG_DMAR_PERF 39 int dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type); 40 void dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type); 41 bool dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type); 42 void dmar_latency_update(struct intel_iommu *iommu, enum latency_type type, 43 u64 latency); 44 int dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size); 45 #else 46 static inline int 47 dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type) 48 { 49 return -EINVAL; 50 } 51 52 static inline void 53 dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type) 54 { 55 } 56 57 static inline bool 58 dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type) 59 { 60 return false; 61 } 62 63 static inline void 64 dmar_latency_update(struct intel_iommu *iommu, enum latency_type type, u64 latency) 65 { 66 } 67 68 static inline int 69 dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size) 70 { 71 return 0; 72 } 73 #endif /* CONFIG_DMAR_PERF */ 74