1 // SPDX-License-Identifier: GPL-2.0 2 3 #define pr_fmt(fmt) "DMAR-IR: " fmt 4 5 #include <linux/interrupt.h> 6 #include <linux/dmar.h> 7 #include <linux/spinlock.h> 8 #include <linux/slab.h> 9 #include <linux/jiffies.h> 10 #include <linux/hpet.h> 11 #include <linux/pci.h> 12 #include <linux/irq.h> 13 #include <linux/acpi.h> 14 #include <linux/irqdomain.h> 15 #include <linux/crash_dump.h> 16 #include <asm/io_apic.h> 17 #include <asm/apic.h> 18 #include <asm/smp.h> 19 #include <asm/cpu.h> 20 #include <asm/irq_remapping.h> 21 #include <asm/pci-direct.h> 22 23 #include "iommu.h" 24 #include "../irq_remapping.h" 25 #include "cap_audit.h" 26 27 enum irq_mode { 28 IRQ_REMAPPING, 29 IRQ_POSTING, 30 }; 31 32 struct ioapic_scope { 33 struct intel_iommu *iommu; 34 unsigned int id; 35 unsigned int bus; /* PCI bus number */ 36 unsigned int devfn; /* PCI devfn number */ 37 }; 38 39 struct hpet_scope { 40 struct intel_iommu *iommu; 41 u8 id; 42 unsigned int bus; 43 unsigned int devfn; 44 }; 45 46 struct irq_2_iommu { 47 struct intel_iommu *iommu; 48 u16 irte_index; 49 u16 sub_handle; 50 u8 irte_mask; 51 enum irq_mode mode; 52 }; 53 54 struct intel_ir_data { 55 struct irq_2_iommu irq_2_iommu; 56 struct irte irte_entry; 57 union { 58 struct msi_msg msi_entry; 59 }; 60 }; 61 62 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) 63 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8) 64 65 static int __read_mostly eim_mode; 66 static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; 67 static struct hpet_scope ir_hpet[MAX_HPET_TBS]; 68 69 /* 70 * Lock ordering: 71 * ->dmar_global_lock 72 * ->irq_2_ir_lock 73 * ->qi->q_lock 74 * ->iommu->register_lock 75 * Note: 76 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called 77 * in single-threaded environment with interrupt disabled, so no need to tabke 78 * the dmar_global_lock. 79 */ 80 DEFINE_RAW_SPINLOCK(irq_2_ir_lock); 81 static const struct irq_domain_ops intel_ir_domain_ops; 82 83 static void iommu_disable_irq_remapping(struct intel_iommu *iommu); 84 static int __init parse_ioapics_under_ir(void); 85 86 static bool ir_pre_enabled(struct intel_iommu *iommu) 87 { 88 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); 89 } 90 91 static void clear_ir_pre_enabled(struct intel_iommu *iommu) 92 { 93 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; 94 } 95 96 static void init_ir_status(struct intel_iommu *iommu) 97 { 98 u32 gsts; 99 100 gsts = readl(iommu->reg + DMAR_GSTS_REG); 101 if (gsts & DMA_GSTS_IRES) 102 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED; 103 } 104 105 static int alloc_irte(struct intel_iommu *iommu, 106 struct irq_2_iommu *irq_iommu, u16 count) 107 { 108 struct ir_table *table = iommu->ir_table; 109 unsigned int mask = 0; 110 unsigned long flags; 111 int index; 112 113 if (!count || !irq_iommu) 114 return -1; 115 116 if (count > 1) { 117 count = __roundup_pow_of_two(count); 118 mask = ilog2(count); 119 } 120 121 if (mask > ecap_max_handle_mask(iommu->ecap)) { 122 pr_err("Requested mask %x exceeds the max invalidation handle" 123 " mask value %Lx\n", mask, 124 ecap_max_handle_mask(iommu->ecap)); 125 return -1; 126 } 127 128 raw_spin_lock_irqsave(&irq_2_ir_lock, flags); 129 index = bitmap_find_free_region(table->bitmap, 130 INTR_REMAP_TABLE_ENTRIES, mask); 131 if (index < 0) { 132 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); 133 } else { 134 irq_iommu->iommu = iommu; 135 irq_iommu->irte_index = index; 136 irq_iommu->sub_handle = 0; 137 irq_iommu->irte_mask = mask; 138 irq_iommu->mode = IRQ_REMAPPING; 139 } 140 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); 141 142 return index; 143 } 144 145 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) 146 { 147 struct qi_desc desc; 148 149 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) 150 | QI_IEC_SELECTIVE; 151 desc.qw1 = 0; 152 desc.qw2 = 0; 153 desc.qw3 = 0; 154 155 return qi_submit_sync(iommu, &desc, 1, 0); 156 } 157 158 static int modify_irte(struct irq_2_iommu *irq_iommu, 159 struct irte *irte_modified) 160 { 161 struct intel_iommu *iommu; 162 unsigned long flags; 163 struct irte *irte; 164 int rc, index; 165 166 if (!irq_iommu) 167 return -1; 168 169 raw_spin_lock_irqsave(&irq_2_ir_lock, flags); 170 171 iommu = irq_iommu->iommu; 172 173 index = irq_iommu->irte_index + irq_iommu->sub_handle; 174 irte = &iommu->ir_table->base[index]; 175 176 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE) 177 if ((irte->pst == 1) || (irte_modified->pst == 1)) { 178 bool ret; 179 180 ret = cmpxchg_double(&irte->low, &irte->high, 181 irte->low, irte->high, 182 irte_modified->low, irte_modified->high); 183 /* 184 * We use cmpxchg16 to atomically update the 128-bit IRTE, 185 * and it cannot be updated by the hardware or other processors 186 * behind us, so the return value of cmpxchg16 should be the 187 * same as the old value. 188 */ 189 WARN_ON(!ret); 190 } else 191 #endif 192 { 193 set_64bit(&irte->low, irte_modified->low); 194 set_64bit(&irte->high, irte_modified->high); 195 } 196 __iommu_flush_cache(iommu, irte, sizeof(*irte)); 197 198 rc = qi_flush_iec(iommu, index, 0); 199 200 /* Update iommu mode according to the IRTE mode */ 201 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING; 202 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); 203 204 return rc; 205 } 206 207 static struct intel_iommu *map_hpet_to_iommu(u8 hpet_id) 208 { 209 int i; 210 211 for (i = 0; i < MAX_HPET_TBS; i++) { 212 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) 213 return ir_hpet[i].iommu; 214 } 215 return NULL; 216 } 217 218 static struct intel_iommu *map_ioapic_to_iommu(int apic) 219 { 220 int i; 221 222 for (i = 0; i < MAX_IO_APICS; i++) { 223 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) 224 return ir_ioapic[i].iommu; 225 } 226 return NULL; 227 } 228 229 static struct irq_domain *map_dev_to_ir(struct pci_dev *dev) 230 { 231 struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev); 232 233 return drhd ? drhd->iommu->ir_msi_domain : NULL; 234 } 235 236 static int clear_entries(struct irq_2_iommu *irq_iommu) 237 { 238 struct irte *start, *entry, *end; 239 struct intel_iommu *iommu; 240 int index; 241 242 if (irq_iommu->sub_handle) 243 return 0; 244 245 iommu = irq_iommu->iommu; 246 index = irq_iommu->irte_index; 247 248 start = iommu->ir_table->base + index; 249 end = start + (1 << irq_iommu->irte_mask); 250 251 for (entry = start; entry < end; entry++) { 252 set_64bit(&entry->low, 0); 253 set_64bit(&entry->high, 0); 254 } 255 bitmap_release_region(iommu->ir_table->bitmap, index, 256 irq_iommu->irte_mask); 257 258 return qi_flush_iec(iommu, index, irq_iommu->irte_mask); 259 } 260 261 /* 262 * source validation type 263 */ 264 #define SVT_NO_VERIFY 0x0 /* no verification is required */ 265 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ 266 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ 267 268 /* 269 * source-id qualifier 270 */ 271 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ 272 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore 273 * the third least significant bit 274 */ 275 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore 276 * the second and third least significant bits 277 */ 278 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore 279 * the least three significant bits 280 */ 281 282 /* 283 * set SVT, SQ and SID fields of irte to verify 284 * source ids of interrupt requests 285 */ 286 static void set_irte_sid(struct irte *irte, unsigned int svt, 287 unsigned int sq, unsigned int sid) 288 { 289 if (disable_sourceid_checking) 290 svt = SVT_NO_VERIFY; 291 irte->svt = svt; 292 irte->sq = sq; 293 irte->sid = sid; 294 } 295 296 /* 297 * Set an IRTE to match only the bus number. Interrupt requests that reference 298 * this IRTE must have a requester-id whose bus number is between or equal 299 * to the start_bus and end_bus arguments. 300 */ 301 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus, 302 unsigned int end_bus) 303 { 304 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, 305 (start_bus << 8) | end_bus); 306 } 307 308 static int set_ioapic_sid(struct irte *irte, int apic) 309 { 310 int i; 311 u16 sid = 0; 312 313 if (!irte) 314 return -1; 315 316 down_read(&dmar_global_lock); 317 for (i = 0; i < MAX_IO_APICS; i++) { 318 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { 319 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; 320 break; 321 } 322 } 323 up_read(&dmar_global_lock); 324 325 if (sid == 0) { 326 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic); 327 return -1; 328 } 329 330 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); 331 332 return 0; 333 } 334 335 static int set_hpet_sid(struct irte *irte, u8 id) 336 { 337 int i; 338 u16 sid = 0; 339 340 if (!irte) 341 return -1; 342 343 down_read(&dmar_global_lock); 344 for (i = 0; i < MAX_HPET_TBS; i++) { 345 if (ir_hpet[i].iommu && ir_hpet[i].id == id) { 346 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; 347 break; 348 } 349 } 350 up_read(&dmar_global_lock); 351 352 if (sid == 0) { 353 pr_warn("Failed to set source-id of HPET block (%d)\n", id); 354 return -1; 355 } 356 357 /* 358 * Should really use SQ_ALL_16. Some platforms are broken. 359 * While we figure out the right quirks for these broken platforms, use 360 * SQ_13_IGNORE_3 for now. 361 */ 362 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); 363 364 return 0; 365 } 366 367 struct set_msi_sid_data { 368 struct pci_dev *pdev; 369 u16 alias; 370 int count; 371 int busmatch_count; 372 }; 373 374 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque) 375 { 376 struct set_msi_sid_data *data = opaque; 377 378 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias)) 379 data->busmatch_count++; 380 381 data->pdev = pdev; 382 data->alias = alias; 383 data->count++; 384 385 return 0; 386 } 387 388 static int set_msi_sid(struct irte *irte, struct pci_dev *dev) 389 { 390 struct set_msi_sid_data data; 391 392 if (!irte || !dev) 393 return -1; 394 395 data.count = 0; 396 data.busmatch_count = 0; 397 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data); 398 399 /* 400 * DMA alias provides us with a PCI device and alias. The only case 401 * where the it will return an alias on a different bus than the 402 * device is the case of a PCIe-to-PCI bridge, where the alias is for 403 * the subordinate bus. In this case we can only verify the bus. 404 * 405 * If there are multiple aliases, all with the same bus number, 406 * then all we can do is verify the bus. This is typical in NTB 407 * hardware which use proxy IDs where the device will generate traffic 408 * from multiple devfn numbers on the same bus. 409 * 410 * If the alias device is on a different bus than our source device 411 * then we have a topology based alias, use it. 412 * 413 * Otherwise, the alias is for a device DMA quirk and we cannot 414 * assume that MSI uses the same requester ID. Therefore use the 415 * original device. 416 */ 417 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number) 418 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias), 419 dev->bus->number); 420 else if (data.count >= 2 && data.busmatch_count == data.count) 421 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number); 422 else if (data.pdev->bus->number != dev->bus->number) 423 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias); 424 else 425 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, 426 pci_dev_id(dev)); 427 428 return 0; 429 } 430 431 static int iommu_load_old_irte(struct intel_iommu *iommu) 432 { 433 struct irte *old_ir_table; 434 phys_addr_t irt_phys; 435 unsigned int i; 436 size_t size; 437 u64 irta; 438 439 /* Check whether the old ir-table has the same size as ours */ 440 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG); 441 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK) 442 != INTR_REMAP_TABLE_REG_SIZE) 443 return -EINVAL; 444 445 irt_phys = irta & VTD_PAGE_MASK; 446 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte); 447 448 /* Map the old IR table */ 449 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB); 450 if (!old_ir_table) 451 return -ENOMEM; 452 453 /* Copy data over */ 454 memcpy(iommu->ir_table->base, old_ir_table, size); 455 456 __iommu_flush_cache(iommu, iommu->ir_table->base, size); 457 458 /* 459 * Now check the table for used entries and mark those as 460 * allocated in the bitmap 461 */ 462 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) { 463 if (iommu->ir_table->base[i].present) 464 bitmap_set(iommu->ir_table->bitmap, i, 1); 465 } 466 467 memunmap(old_ir_table); 468 469 return 0; 470 } 471 472 473 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) 474 { 475 unsigned long flags; 476 u64 addr; 477 u32 sts; 478 479 addr = virt_to_phys((void *)iommu->ir_table->base); 480 481 raw_spin_lock_irqsave(&iommu->register_lock, flags); 482 483 dmar_writeq(iommu->reg + DMAR_IRTA_REG, 484 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); 485 486 /* Set interrupt-remapping table pointer */ 487 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); 488 489 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, 490 readl, (sts & DMA_GSTS_IRTPS), sts); 491 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); 492 493 /* 494 * Global invalidation of interrupt entry cache to make sure the 495 * hardware uses the new irq remapping table. 496 */ 497 if (!cap_esirtps(iommu->cap)) 498 qi_global_iec(iommu); 499 } 500 501 static void iommu_enable_irq_remapping(struct intel_iommu *iommu) 502 { 503 unsigned long flags; 504 u32 sts; 505 506 raw_spin_lock_irqsave(&iommu->register_lock, flags); 507 508 /* Enable interrupt-remapping */ 509 iommu->gcmd |= DMA_GCMD_IRE; 510 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); 511 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, 512 readl, (sts & DMA_GSTS_IRES), sts); 513 514 /* Block compatibility-format MSIs */ 515 if (sts & DMA_GSTS_CFIS) { 516 iommu->gcmd &= ~DMA_GCMD_CFI; 517 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); 518 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, 519 readl, !(sts & DMA_GSTS_CFIS), sts); 520 } 521 522 /* 523 * With CFI clear in the Global Command register, we should be 524 * protected from dangerous (i.e. compatibility) interrupts 525 * regardless of x2apic status. Check just to be sure. 526 */ 527 if (sts & DMA_GSTS_CFIS) 528 WARN(1, KERN_WARNING 529 "Compatibility-format IRQs enabled despite intr remapping;\n" 530 "you are vulnerable to IRQ injection.\n"); 531 532 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); 533 } 534 535 static int intel_setup_irq_remapping(struct intel_iommu *iommu) 536 { 537 struct ir_table *ir_table; 538 struct fwnode_handle *fn; 539 unsigned long *bitmap; 540 struct page *pages; 541 542 if (iommu->ir_table) 543 return 0; 544 545 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL); 546 if (!ir_table) 547 return -ENOMEM; 548 549 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, 550 INTR_REMAP_PAGE_ORDER); 551 if (!pages) { 552 pr_err("IR%d: failed to allocate pages of order %d\n", 553 iommu->seq_id, INTR_REMAP_PAGE_ORDER); 554 goto out_free_table; 555 } 556 557 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC); 558 if (bitmap == NULL) { 559 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); 560 goto out_free_pages; 561 } 562 563 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id); 564 if (!fn) 565 goto out_free_bitmap; 566 567 iommu->ir_domain = 568 irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 569 0, INTR_REMAP_TABLE_ENTRIES, 570 fn, &intel_ir_domain_ops, 571 iommu); 572 if (!iommu->ir_domain) { 573 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); 574 goto out_free_fwnode; 575 } 576 iommu->ir_msi_domain = 577 arch_create_remap_msi_irq_domain(iommu->ir_domain, 578 "INTEL-IR-MSI", 579 iommu->seq_id); 580 581 ir_table->base = page_address(pages); 582 ir_table->bitmap = bitmap; 583 iommu->ir_table = ir_table; 584 585 /* 586 * If the queued invalidation is already initialized, 587 * shouldn't disable it. 588 */ 589 if (!iommu->qi) { 590 /* 591 * Clear previous faults. 592 */ 593 dmar_fault(-1, iommu); 594 dmar_disable_qi(iommu); 595 596 if (dmar_enable_qi(iommu)) { 597 pr_err("Failed to enable queued invalidation\n"); 598 goto out_free_ir_domain; 599 } 600 } 601 602 init_ir_status(iommu); 603 604 if (ir_pre_enabled(iommu)) { 605 if (!is_kdump_kernel()) { 606 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n", 607 iommu->name); 608 clear_ir_pre_enabled(iommu); 609 iommu_disable_irq_remapping(iommu); 610 } else if (iommu_load_old_irte(iommu)) 611 pr_err("Failed to copy IR table for %s from previous kernel\n", 612 iommu->name); 613 else 614 pr_info("Copied IR table for %s from previous kernel\n", 615 iommu->name); 616 } 617 618 iommu_set_irq_remapping(iommu, eim_mode); 619 620 return 0; 621 622 out_free_ir_domain: 623 if (iommu->ir_msi_domain) 624 irq_domain_remove(iommu->ir_msi_domain); 625 iommu->ir_msi_domain = NULL; 626 irq_domain_remove(iommu->ir_domain); 627 iommu->ir_domain = NULL; 628 out_free_fwnode: 629 irq_domain_free_fwnode(fn); 630 out_free_bitmap: 631 bitmap_free(bitmap); 632 out_free_pages: 633 __free_pages(pages, INTR_REMAP_PAGE_ORDER); 634 out_free_table: 635 kfree(ir_table); 636 637 iommu->ir_table = NULL; 638 639 return -ENOMEM; 640 } 641 642 static void intel_teardown_irq_remapping(struct intel_iommu *iommu) 643 { 644 struct fwnode_handle *fn; 645 646 if (iommu && iommu->ir_table) { 647 if (iommu->ir_msi_domain) { 648 fn = iommu->ir_msi_domain->fwnode; 649 650 irq_domain_remove(iommu->ir_msi_domain); 651 irq_domain_free_fwnode(fn); 652 iommu->ir_msi_domain = NULL; 653 } 654 if (iommu->ir_domain) { 655 fn = iommu->ir_domain->fwnode; 656 657 irq_domain_remove(iommu->ir_domain); 658 irq_domain_free_fwnode(fn); 659 iommu->ir_domain = NULL; 660 } 661 free_pages((unsigned long)iommu->ir_table->base, 662 INTR_REMAP_PAGE_ORDER); 663 bitmap_free(iommu->ir_table->bitmap); 664 kfree(iommu->ir_table); 665 iommu->ir_table = NULL; 666 } 667 } 668 669 /* 670 * Disable Interrupt Remapping. 671 */ 672 static void iommu_disable_irq_remapping(struct intel_iommu *iommu) 673 { 674 unsigned long flags; 675 u32 sts; 676 677 if (!ecap_ir_support(iommu->ecap)) 678 return; 679 680 /* 681 * global invalidation of interrupt entry cache before disabling 682 * interrupt-remapping. 683 */ 684 if (!cap_esirtps(iommu->cap)) 685 qi_global_iec(iommu); 686 687 raw_spin_lock_irqsave(&iommu->register_lock, flags); 688 689 sts = readl(iommu->reg + DMAR_GSTS_REG); 690 if (!(sts & DMA_GSTS_IRES)) 691 goto end; 692 693 iommu->gcmd &= ~DMA_GCMD_IRE; 694 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); 695 696 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, 697 readl, !(sts & DMA_GSTS_IRES), sts); 698 699 end: 700 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); 701 } 702 703 static int __init dmar_x2apic_optout(void) 704 { 705 struct acpi_table_dmar *dmar; 706 dmar = (struct acpi_table_dmar *)dmar_tbl; 707 if (!dmar || no_x2apic_optout) 708 return 0; 709 return dmar->flags & DMAR_X2APIC_OPT_OUT; 710 } 711 712 static void __init intel_cleanup_irq_remapping(void) 713 { 714 struct dmar_drhd_unit *drhd; 715 struct intel_iommu *iommu; 716 717 for_each_iommu(iommu, drhd) { 718 if (ecap_ir_support(iommu->ecap)) { 719 iommu_disable_irq_remapping(iommu); 720 intel_teardown_irq_remapping(iommu); 721 } 722 } 723 724 if (x2apic_supported()) 725 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); 726 } 727 728 static int __init intel_prepare_irq_remapping(void) 729 { 730 struct dmar_drhd_unit *drhd; 731 struct intel_iommu *iommu; 732 int eim = 0; 733 734 if (irq_remap_broken) { 735 pr_warn("This system BIOS has enabled interrupt remapping\n" 736 "on a chipset that contains an erratum making that\n" 737 "feature unstable. To maintain system stability\n" 738 "interrupt remapping is being disabled. Please\n" 739 "contact your BIOS vendor for an update\n"); 740 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 741 return -ENODEV; 742 } 743 744 if (dmar_table_init() < 0) 745 return -ENODEV; 746 747 if (intel_cap_audit(CAP_AUDIT_STATIC_IRQR, NULL)) 748 return -ENODEV; 749 750 if (!dmar_ir_support()) 751 return -ENODEV; 752 753 if (parse_ioapics_under_ir()) { 754 pr_info("Not enabling interrupt remapping\n"); 755 goto error; 756 } 757 758 /* First make sure all IOMMUs support IRQ remapping */ 759 for_each_iommu(iommu, drhd) 760 if (!ecap_ir_support(iommu->ecap)) 761 goto error; 762 763 /* Detect remapping mode: lapic or x2apic */ 764 if (x2apic_supported()) { 765 eim = !dmar_x2apic_optout(); 766 if (!eim) { 767 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit."); 768 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n"); 769 } 770 } 771 772 for_each_iommu(iommu, drhd) { 773 if (eim && !ecap_eim_support(iommu->ecap)) { 774 pr_info("%s does not support EIM\n", iommu->name); 775 eim = 0; 776 } 777 } 778 779 eim_mode = eim; 780 if (eim) 781 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n"); 782 783 /* Do the initializations early */ 784 for_each_iommu(iommu, drhd) { 785 if (intel_setup_irq_remapping(iommu)) { 786 pr_err("Failed to setup irq remapping for %s\n", 787 iommu->name); 788 goto error; 789 } 790 } 791 792 return 0; 793 794 error: 795 intel_cleanup_irq_remapping(); 796 return -ENODEV; 797 } 798 799 /* 800 * Set Posted-Interrupts capability. 801 */ 802 static inline void set_irq_posting_cap(void) 803 { 804 struct dmar_drhd_unit *drhd; 805 struct intel_iommu *iommu; 806 807 if (!disable_irq_post) { 808 /* 809 * If IRTE is in posted format, the 'pda' field goes across the 810 * 64-bit boundary, we need use cmpxchg16b to atomically update 811 * it. We only expose posted-interrupt when X86_FEATURE_CX16 812 * is supported. Actually, hardware platforms supporting PI 813 * should have X86_FEATURE_CX16 support, this has been confirmed 814 * with Intel hardware guys. 815 */ 816 if (boot_cpu_has(X86_FEATURE_CX16)) 817 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP; 818 819 for_each_iommu(iommu, drhd) 820 if (!cap_pi_support(iommu->cap)) { 821 intel_irq_remap_ops.capability &= 822 ~(1 << IRQ_POSTING_CAP); 823 break; 824 } 825 } 826 } 827 828 static int __init intel_enable_irq_remapping(void) 829 { 830 struct dmar_drhd_unit *drhd; 831 struct intel_iommu *iommu; 832 bool setup = false; 833 834 /* 835 * Setup Interrupt-remapping for all the DRHD's now. 836 */ 837 for_each_iommu(iommu, drhd) { 838 if (!ir_pre_enabled(iommu)) 839 iommu_enable_irq_remapping(iommu); 840 setup = true; 841 } 842 843 if (!setup) 844 goto error; 845 846 irq_remapping_enabled = 1; 847 848 set_irq_posting_cap(); 849 850 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic"); 851 852 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; 853 854 error: 855 intel_cleanup_irq_remapping(); 856 return -1; 857 } 858 859 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, 860 struct intel_iommu *iommu, 861 struct acpi_dmar_hardware_unit *drhd) 862 { 863 struct acpi_dmar_pci_path *path; 864 u8 bus; 865 int count, free = -1; 866 867 bus = scope->bus; 868 path = (struct acpi_dmar_pci_path *)(scope + 1); 869 count = (scope->length - sizeof(struct acpi_dmar_device_scope)) 870 / sizeof(struct acpi_dmar_pci_path); 871 872 while (--count > 0) { 873 /* 874 * Access PCI directly due to the PCI 875 * subsystem isn't initialized yet. 876 */ 877 bus = read_pci_config_byte(bus, path->device, path->function, 878 PCI_SECONDARY_BUS); 879 path++; 880 } 881 882 for (count = 0; count < MAX_HPET_TBS; count++) { 883 if (ir_hpet[count].iommu == iommu && 884 ir_hpet[count].id == scope->enumeration_id) 885 return 0; 886 else if (ir_hpet[count].iommu == NULL && free == -1) 887 free = count; 888 } 889 if (free == -1) { 890 pr_warn("Exceeded Max HPET blocks\n"); 891 return -ENOSPC; 892 } 893 894 ir_hpet[free].iommu = iommu; 895 ir_hpet[free].id = scope->enumeration_id; 896 ir_hpet[free].bus = bus; 897 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function); 898 pr_info("HPET id %d under DRHD base 0x%Lx\n", 899 scope->enumeration_id, drhd->address); 900 901 return 0; 902 } 903 904 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, 905 struct intel_iommu *iommu, 906 struct acpi_dmar_hardware_unit *drhd) 907 { 908 struct acpi_dmar_pci_path *path; 909 u8 bus; 910 int count, free = -1; 911 912 bus = scope->bus; 913 path = (struct acpi_dmar_pci_path *)(scope + 1); 914 count = (scope->length - sizeof(struct acpi_dmar_device_scope)) 915 / sizeof(struct acpi_dmar_pci_path); 916 917 while (--count > 0) { 918 /* 919 * Access PCI directly due to the PCI 920 * subsystem isn't initialized yet. 921 */ 922 bus = read_pci_config_byte(bus, path->device, path->function, 923 PCI_SECONDARY_BUS); 924 path++; 925 } 926 927 for (count = 0; count < MAX_IO_APICS; count++) { 928 if (ir_ioapic[count].iommu == iommu && 929 ir_ioapic[count].id == scope->enumeration_id) 930 return 0; 931 else if (ir_ioapic[count].iommu == NULL && free == -1) 932 free = count; 933 } 934 if (free == -1) { 935 pr_warn("Exceeded Max IO APICS\n"); 936 return -ENOSPC; 937 } 938 939 ir_ioapic[free].bus = bus; 940 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function); 941 ir_ioapic[free].iommu = iommu; 942 ir_ioapic[free].id = scope->enumeration_id; 943 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n", 944 scope->enumeration_id, drhd->address, iommu->seq_id); 945 946 return 0; 947 } 948 949 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, 950 struct intel_iommu *iommu) 951 { 952 int ret = 0; 953 struct acpi_dmar_hardware_unit *drhd; 954 struct acpi_dmar_device_scope *scope; 955 void *start, *end; 956 957 drhd = (struct acpi_dmar_hardware_unit *)header; 958 start = (void *)(drhd + 1); 959 end = ((void *)drhd) + header->length; 960 961 while (start < end && ret == 0) { 962 scope = start; 963 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) 964 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd); 965 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) 966 ret = ir_parse_one_hpet_scope(scope, iommu, drhd); 967 start += scope->length; 968 } 969 970 return ret; 971 } 972 973 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu) 974 { 975 int i; 976 977 for (i = 0; i < MAX_HPET_TBS; i++) 978 if (ir_hpet[i].iommu == iommu) 979 ir_hpet[i].iommu = NULL; 980 981 for (i = 0; i < MAX_IO_APICS; i++) 982 if (ir_ioapic[i].iommu == iommu) 983 ir_ioapic[i].iommu = NULL; 984 } 985 986 /* 987 * Finds the assocaition between IOAPIC's and its Interrupt-remapping 988 * hardware unit. 989 */ 990 static int __init parse_ioapics_under_ir(void) 991 { 992 struct dmar_drhd_unit *drhd; 993 struct intel_iommu *iommu; 994 bool ir_supported = false; 995 int ioapic_idx; 996 997 for_each_iommu(iommu, drhd) { 998 int ret; 999 1000 if (!ecap_ir_support(iommu->ecap)) 1001 continue; 1002 1003 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu); 1004 if (ret) 1005 return ret; 1006 1007 ir_supported = true; 1008 } 1009 1010 if (!ir_supported) 1011 return -ENODEV; 1012 1013 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { 1014 int ioapic_id = mpc_ioapic_id(ioapic_idx); 1015 if (!map_ioapic_to_iommu(ioapic_id)) { 1016 pr_err(FW_BUG "ioapic %d has no mapping iommu, " 1017 "interrupt remapping will be disabled\n", 1018 ioapic_id); 1019 return -1; 1020 } 1021 } 1022 1023 return 0; 1024 } 1025 1026 static int __init ir_dev_scope_init(void) 1027 { 1028 int ret; 1029 1030 if (!irq_remapping_enabled) 1031 return 0; 1032 1033 down_write(&dmar_global_lock); 1034 ret = dmar_dev_scope_init(); 1035 up_write(&dmar_global_lock); 1036 1037 return ret; 1038 } 1039 rootfs_initcall(ir_dev_scope_init); 1040 1041 static void disable_irq_remapping(void) 1042 { 1043 struct dmar_drhd_unit *drhd; 1044 struct intel_iommu *iommu = NULL; 1045 1046 /* 1047 * Disable Interrupt-remapping for all the DRHD's now. 1048 */ 1049 for_each_iommu(iommu, drhd) { 1050 if (!ecap_ir_support(iommu->ecap)) 1051 continue; 1052 1053 iommu_disable_irq_remapping(iommu); 1054 } 1055 1056 /* 1057 * Clear Posted-Interrupts capability. 1058 */ 1059 if (!disable_irq_post) 1060 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP); 1061 } 1062 1063 static int reenable_irq_remapping(int eim) 1064 { 1065 struct dmar_drhd_unit *drhd; 1066 bool setup = false; 1067 struct intel_iommu *iommu = NULL; 1068 1069 for_each_iommu(iommu, drhd) 1070 if (iommu->qi) 1071 dmar_reenable_qi(iommu); 1072 1073 /* 1074 * Setup Interrupt-remapping for all the DRHD's now. 1075 */ 1076 for_each_iommu(iommu, drhd) { 1077 if (!ecap_ir_support(iommu->ecap)) 1078 continue; 1079 1080 /* Set up interrupt remapping for iommu.*/ 1081 iommu_set_irq_remapping(iommu, eim); 1082 iommu_enable_irq_remapping(iommu); 1083 setup = true; 1084 } 1085 1086 if (!setup) 1087 goto error; 1088 1089 set_irq_posting_cap(); 1090 1091 return 0; 1092 1093 error: 1094 /* 1095 * handle error condition gracefully here! 1096 */ 1097 return -1; 1098 } 1099 1100 /* 1101 * Store the MSI remapping domain pointer in the device if enabled. 1102 * 1103 * This is called from dmar_pci_bus_add_dev() so it works even when DMA 1104 * remapping is disabled. Only update the pointer if the device is not 1105 * already handled by a non default PCI/MSI interrupt domain. This protects 1106 * e.g. VMD devices. 1107 */ 1108 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info) 1109 { 1110 if (!irq_remapping_enabled || pci_dev_has_special_msi_domain(info->dev)) 1111 return; 1112 1113 dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev)); 1114 } 1115 1116 static void prepare_irte(struct irte *irte, int vector, unsigned int dest) 1117 { 1118 memset(irte, 0, sizeof(*irte)); 1119 1120 irte->present = 1; 1121 irte->dst_mode = apic->dest_mode_logical; 1122 /* 1123 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the 1124 * actual level or edge trigger will be setup in the IO-APIC 1125 * RTE. This will help simplify level triggered irq migration. 1126 * For more details, see the comments (in io_apic.c) explainig IO-APIC 1127 * irq migration in the presence of interrupt-remapping. 1128 */ 1129 irte->trigger_mode = 0; 1130 irte->dlvry_mode = apic->delivery_mode; 1131 irte->vector = vector; 1132 irte->dest_id = IRTE_DEST(dest); 1133 irte->redir_hint = 1; 1134 } 1135 1136 struct irq_remap_ops intel_irq_remap_ops = { 1137 .prepare = intel_prepare_irq_remapping, 1138 .enable = intel_enable_irq_remapping, 1139 .disable = disable_irq_remapping, 1140 .reenable = reenable_irq_remapping, 1141 .enable_faulting = enable_drhd_fault_handling, 1142 }; 1143 1144 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force) 1145 { 1146 struct intel_ir_data *ir_data = irqd->chip_data; 1147 struct irte *irte = &ir_data->irte_entry; 1148 struct irq_cfg *cfg = irqd_cfg(irqd); 1149 1150 /* 1151 * Atomically updates the IRTE with the new destination, vector 1152 * and flushes the interrupt entry cache. 1153 */ 1154 irte->vector = cfg->vector; 1155 irte->dest_id = IRTE_DEST(cfg->dest_apicid); 1156 1157 /* Update the hardware only if the interrupt is in remapped mode. */ 1158 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING) 1159 modify_irte(&ir_data->irq_2_iommu, irte); 1160 } 1161 1162 /* 1163 * Migrate the IO-APIC irq in the presence of intr-remapping. 1164 * 1165 * For both level and edge triggered, irq migration is a simple atomic 1166 * update(of vector and cpu destination) of IRTE and flush the hardware cache. 1167 * 1168 * For level triggered, we eliminate the io-apic RTE modification (with the 1169 * updated vector information), by using a virtual vector (io-apic pin number). 1170 * Real vector that is used for interrupting cpu will be coming from 1171 * the interrupt-remapping table entry. 1172 * 1173 * As the migration is a simple atomic update of IRTE, the same mechanism 1174 * is used to migrate MSI irq's in the presence of interrupt-remapping. 1175 */ 1176 static int 1177 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, 1178 bool force) 1179 { 1180 struct irq_data *parent = data->parent_data; 1181 struct irq_cfg *cfg = irqd_cfg(data); 1182 int ret; 1183 1184 ret = parent->chip->irq_set_affinity(parent, mask, force); 1185 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 1186 return ret; 1187 1188 intel_ir_reconfigure_irte(data, false); 1189 /* 1190 * After this point, all the interrupts will start arriving 1191 * at the new destination. So, time to cleanup the previous 1192 * vector allocation. 1193 */ 1194 send_cleanup_vector(cfg); 1195 1196 return IRQ_SET_MASK_OK_DONE; 1197 } 1198 1199 static void intel_ir_compose_msi_msg(struct irq_data *irq_data, 1200 struct msi_msg *msg) 1201 { 1202 struct intel_ir_data *ir_data = irq_data->chip_data; 1203 1204 *msg = ir_data->msi_entry; 1205 } 1206 1207 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info) 1208 { 1209 struct intel_ir_data *ir_data = data->chip_data; 1210 struct vcpu_data *vcpu_pi_info = info; 1211 1212 /* stop posting interrupts, back to remapping mode */ 1213 if (!vcpu_pi_info) { 1214 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry); 1215 } else { 1216 struct irte irte_pi; 1217 1218 /* 1219 * We are not caching the posted interrupt entry. We 1220 * copy the data from the remapped entry and modify 1221 * the fields which are relevant for posted mode. The 1222 * cached remapped entry is used for switching back to 1223 * remapped mode. 1224 */ 1225 memset(&irte_pi, 0, sizeof(irte_pi)); 1226 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry); 1227 1228 /* Update the posted mode fields */ 1229 irte_pi.p_pst = 1; 1230 irte_pi.p_urgent = 0; 1231 irte_pi.p_vector = vcpu_pi_info->vector; 1232 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >> 1233 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT); 1234 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) & 1235 ~(-1UL << PDA_HIGH_BIT); 1236 1237 modify_irte(&ir_data->irq_2_iommu, &irte_pi); 1238 } 1239 1240 return 0; 1241 } 1242 1243 static struct irq_chip intel_ir_chip = { 1244 .name = "INTEL-IR", 1245 .irq_ack = apic_ack_irq, 1246 .irq_set_affinity = intel_ir_set_affinity, 1247 .irq_compose_msi_msg = intel_ir_compose_msi_msg, 1248 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity, 1249 }; 1250 1251 static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle) 1252 { 1253 memset(msg, 0, sizeof(*msg)); 1254 1255 msg->arch_addr_lo.dmar_base_address = X86_MSI_BASE_ADDRESS_LOW; 1256 msg->arch_addr_lo.dmar_subhandle_valid = true; 1257 msg->arch_addr_lo.dmar_format = true; 1258 msg->arch_addr_lo.dmar_index_0_14 = index & 0x7FFF; 1259 msg->arch_addr_lo.dmar_index_15 = !!(index & 0x8000); 1260 1261 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; 1262 1263 msg->arch_data.dmar_subhandle = subhandle; 1264 } 1265 1266 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, 1267 struct irq_cfg *irq_cfg, 1268 struct irq_alloc_info *info, 1269 int index, int sub_handle) 1270 { 1271 struct irte *irte = &data->irte_entry; 1272 1273 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); 1274 1275 switch (info->type) { 1276 case X86_IRQ_ALLOC_TYPE_IOAPIC: 1277 /* Set source-id of interrupt request */ 1278 set_ioapic_sid(irte, info->devid); 1279 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", 1280 info->devid, irte->present, irte->fpd, 1281 irte->dst_mode, irte->redir_hint, 1282 irte->trigger_mode, irte->dlvry_mode, 1283 irte->avail, irte->vector, irte->dest_id, 1284 irte->sid, irte->sq, irte->svt); 1285 sub_handle = info->ioapic.pin; 1286 break; 1287 case X86_IRQ_ALLOC_TYPE_HPET: 1288 set_hpet_sid(irte, info->devid); 1289 break; 1290 case X86_IRQ_ALLOC_TYPE_PCI_MSI: 1291 case X86_IRQ_ALLOC_TYPE_PCI_MSIX: 1292 set_msi_sid(irte, 1293 pci_real_dma_dev(msi_desc_to_pci_dev(info->desc))); 1294 break; 1295 default: 1296 BUG_ON(1); 1297 break; 1298 } 1299 fill_msi_msg(&data->msi_entry, index, sub_handle); 1300 } 1301 1302 static void intel_free_irq_resources(struct irq_domain *domain, 1303 unsigned int virq, unsigned int nr_irqs) 1304 { 1305 struct irq_data *irq_data; 1306 struct intel_ir_data *data; 1307 struct irq_2_iommu *irq_iommu; 1308 unsigned long flags; 1309 int i; 1310 for (i = 0; i < nr_irqs; i++) { 1311 irq_data = irq_domain_get_irq_data(domain, virq + i); 1312 if (irq_data && irq_data->chip_data) { 1313 data = irq_data->chip_data; 1314 irq_iommu = &data->irq_2_iommu; 1315 raw_spin_lock_irqsave(&irq_2_ir_lock, flags); 1316 clear_entries(irq_iommu); 1317 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); 1318 irq_domain_reset_irq_data(irq_data); 1319 kfree(data); 1320 } 1321 } 1322 } 1323 1324 static int intel_irq_remapping_alloc(struct irq_domain *domain, 1325 unsigned int virq, unsigned int nr_irqs, 1326 void *arg) 1327 { 1328 struct intel_iommu *iommu = domain->host_data; 1329 struct irq_alloc_info *info = arg; 1330 struct intel_ir_data *data, *ird; 1331 struct irq_data *irq_data; 1332 struct irq_cfg *irq_cfg; 1333 int i, ret, index; 1334 1335 if (!info || !iommu) 1336 return -EINVAL; 1337 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI && 1338 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX) 1339 return -EINVAL; 1340 1341 /* 1342 * With IRQ remapping enabled, don't need contiguous CPU vectors 1343 * to support multiple MSI interrupts. 1344 */ 1345 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) 1346 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; 1347 1348 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 1349 if (ret < 0) 1350 return ret; 1351 1352 ret = -ENOMEM; 1353 data = kzalloc(sizeof(*data), GFP_KERNEL); 1354 if (!data) 1355 goto out_free_parent; 1356 1357 down_read(&dmar_global_lock); 1358 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs); 1359 up_read(&dmar_global_lock); 1360 if (index < 0) { 1361 pr_warn("Failed to allocate IRTE\n"); 1362 kfree(data); 1363 goto out_free_parent; 1364 } 1365 1366 for (i = 0; i < nr_irqs; i++) { 1367 irq_data = irq_domain_get_irq_data(domain, virq + i); 1368 irq_cfg = irqd_cfg(irq_data); 1369 if (!irq_data || !irq_cfg) { 1370 if (!i) 1371 kfree(data); 1372 ret = -EINVAL; 1373 goto out_free_data; 1374 } 1375 1376 if (i > 0) { 1377 ird = kzalloc(sizeof(*ird), GFP_KERNEL); 1378 if (!ird) 1379 goto out_free_data; 1380 /* Initialize the common data */ 1381 ird->irq_2_iommu = data->irq_2_iommu; 1382 ird->irq_2_iommu.sub_handle = i; 1383 } else { 1384 ird = data; 1385 } 1386 1387 irq_data->hwirq = (index << 16) + i; 1388 irq_data->chip_data = ird; 1389 irq_data->chip = &intel_ir_chip; 1390 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i); 1391 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); 1392 } 1393 return 0; 1394 1395 out_free_data: 1396 intel_free_irq_resources(domain, virq, i); 1397 out_free_parent: 1398 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1399 return ret; 1400 } 1401 1402 static void intel_irq_remapping_free(struct irq_domain *domain, 1403 unsigned int virq, unsigned int nr_irqs) 1404 { 1405 intel_free_irq_resources(domain, virq, nr_irqs); 1406 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1407 } 1408 1409 static int intel_irq_remapping_activate(struct irq_domain *domain, 1410 struct irq_data *irq_data, bool reserve) 1411 { 1412 intel_ir_reconfigure_irte(irq_data, true); 1413 return 0; 1414 } 1415 1416 static void intel_irq_remapping_deactivate(struct irq_domain *domain, 1417 struct irq_data *irq_data) 1418 { 1419 struct intel_ir_data *data = irq_data->chip_data; 1420 struct irte entry; 1421 1422 memset(&entry, 0, sizeof(entry)); 1423 modify_irte(&data->irq_2_iommu, &entry); 1424 } 1425 1426 static int intel_irq_remapping_select(struct irq_domain *d, 1427 struct irq_fwspec *fwspec, 1428 enum irq_domain_bus_token bus_token) 1429 { 1430 struct intel_iommu *iommu = NULL; 1431 1432 if (x86_fwspec_is_ioapic(fwspec)) 1433 iommu = map_ioapic_to_iommu(fwspec->param[0]); 1434 else if (x86_fwspec_is_hpet(fwspec)) 1435 iommu = map_hpet_to_iommu(fwspec->param[0]); 1436 1437 return iommu && d == iommu->ir_domain; 1438 } 1439 1440 static const struct irq_domain_ops intel_ir_domain_ops = { 1441 .select = intel_irq_remapping_select, 1442 .alloc = intel_irq_remapping_alloc, 1443 .free = intel_irq_remapping_free, 1444 .activate = intel_irq_remapping_activate, 1445 .deactivate = intel_irq_remapping_deactivate, 1446 }; 1447 1448 /* 1449 * Support of Interrupt Remapping Unit Hotplug 1450 */ 1451 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu) 1452 { 1453 int ret; 1454 int eim = x2apic_enabled(); 1455 1456 ret = intel_cap_audit(CAP_AUDIT_HOTPLUG_IRQR, iommu); 1457 if (ret) 1458 return ret; 1459 1460 if (eim && !ecap_eim_support(iommu->ecap)) { 1461 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n", 1462 iommu->reg_phys, iommu->ecap); 1463 return -ENODEV; 1464 } 1465 1466 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) { 1467 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n", 1468 iommu->reg_phys); 1469 return -ENODEV; 1470 } 1471 1472 /* TODO: check all IOAPICs are covered by IOMMU */ 1473 1474 /* Setup Interrupt-remapping now. */ 1475 ret = intel_setup_irq_remapping(iommu); 1476 if (ret) { 1477 pr_err("Failed to setup irq remapping for %s\n", 1478 iommu->name); 1479 intel_teardown_irq_remapping(iommu); 1480 ir_remove_ioapic_hpet_scope(iommu); 1481 } else { 1482 iommu_enable_irq_remapping(iommu); 1483 } 1484 1485 return ret; 1486 } 1487 1488 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) 1489 { 1490 int ret = 0; 1491 struct intel_iommu *iommu = dmaru->iommu; 1492 1493 if (!irq_remapping_enabled) 1494 return 0; 1495 if (iommu == NULL) 1496 return -EINVAL; 1497 if (!ecap_ir_support(iommu->ecap)) 1498 return 0; 1499 if (irq_remapping_cap(IRQ_POSTING_CAP) && 1500 !cap_pi_support(iommu->cap)) 1501 return -EBUSY; 1502 1503 if (insert) { 1504 if (!iommu->ir_table) 1505 ret = dmar_ir_add(dmaru, iommu); 1506 } else { 1507 if (iommu->ir_table) { 1508 if (!bitmap_empty(iommu->ir_table->bitmap, 1509 INTR_REMAP_TABLE_ENTRIES)) { 1510 ret = -EBUSY; 1511 } else { 1512 iommu_disable_irq_remapping(iommu); 1513 intel_teardown_irq_remapping(iommu); 1514 ir_remove_ioapic_hpet_scope(iommu); 1515 } 1516 } 1517 } 1518 1519 return ret; 1520 } 1521