1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2013 Freescale Semiconductor, Inc. 5 */ 6 7 #ifndef __FSL_PAMU_DOMAIN_H 8 #define __FSL_PAMU_DOMAIN_H 9 10 #include "fsl_pamu.h" 11 12 struct dma_window { 13 phys_addr_t paddr; 14 u64 size; 15 int valid; 16 int prot; 17 }; 18 19 struct fsl_dma_domain { 20 /* 21 * Number of windows assocaited with this domain. 22 * During domain initialization, it is set to the 23 * the maximum number of subwindows allowed for a LIODN. 24 * Minimum value for this is 1 indicating a single PAMU 25 * window, without any sub windows. Value can be set/ 26 * queried by set_attr/get_attr API for DOMAIN_ATTR_WINDOWS. 27 * Value can only be set once the geometry has been configured. 28 */ 29 u32 win_cnt; 30 /* 31 * win_arr contains information of the configured 32 * windows for a domain. This is allocated only 33 * when the number of windows for the domain are 34 * set. 35 */ 36 struct dma_window *win_arr; 37 /* list of devices associated with the domain */ 38 struct list_head devices; 39 /* dma_domain states: 40 * mapped - A particular mapping has been created 41 * within the configured geometry. 42 * enabled - DMA has been enabled for the given 43 * domain. This translates to setting of the 44 * valid bit for the primary PAACE in the PAMU 45 * PAACT table. Domain geometry should be set and 46 * it must have a valid mapping before DMA can be 47 * enabled for it. 48 * 49 */ 50 int mapped; 51 int enabled; 52 /* stash_id obtained from the stash attribute details */ 53 u32 stash_id; 54 struct pamu_stash_attribute dma_stash; 55 u32 snoop_id; 56 struct iommu_domain iommu_domain; 57 spinlock_t domain_lock; 58 }; 59 60 /* domain-device relationship */ 61 struct device_domain_info { 62 struct list_head link; /* link to domain siblings */ 63 struct device *dev; 64 u32 liodn; 65 struct fsl_dma_domain *domain; /* pointer to domain */ 66 }; 67 #endif /* __FSL_PAMU_DOMAIN_H */ 68