1 /* 2 * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG 11 #define DEBUG 12 #endif 13 14 #include <linux/clk.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/iommu.h> 19 #include <linux/interrupt.h> 20 #include <linux/list.h> 21 #include <linux/of.h> 22 #include <linux/of_iommu.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/slab.h> 27 #include <linux/dma-iommu.h> 28 29 typedef u32 sysmmu_iova_t; 30 typedef u32 sysmmu_pte_t; 31 32 /* We do not consider super section mapping (16MB) */ 33 #define SECT_ORDER 20 34 #define LPAGE_ORDER 16 35 #define SPAGE_ORDER 12 36 37 #define SECT_SIZE (1 << SECT_ORDER) 38 #define LPAGE_SIZE (1 << LPAGE_ORDER) 39 #define SPAGE_SIZE (1 << SPAGE_ORDER) 40 41 #define SECT_MASK (~(SECT_SIZE - 1)) 42 #define LPAGE_MASK (~(LPAGE_SIZE - 1)) 43 #define SPAGE_MASK (~(SPAGE_SIZE - 1)) 44 45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ 46 ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) 47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) 48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) 49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ 50 ((*(sent) & 3) == 1)) 51 #define lv1ent_section(sent) ((*(sent) & 3) == 2) 52 53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0) 54 #define lv2ent_small(pent) ((*(pent) & 2) == 2) 55 #define lv2ent_large(pent) ((*(pent) & 3) == 1) 56 57 /* 58 * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces 59 * v5.0 introduced support for 36bit physical address space by shifting 60 * all page entry values by 4 bits. 61 * All SYSMMU controllers in the system support the address spaces of the same 62 * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper 63 * value (0 or 4). 64 */ 65 static short PG_ENT_SHIFT = -1; 66 #define SYSMMU_PG_ENT_SHIFT 0 67 #define SYSMMU_V5_PG_ENT_SHIFT 4 68 69 static const sysmmu_pte_t *LV1_PROT; 70 static const sysmmu_pte_t SYSMMU_LV1_PROT[] = { 71 ((0 << 15) | (0 << 10)), /* no access */ 72 ((1 << 15) | (1 << 10)), /* IOMMU_READ only */ 73 ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */ 74 ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */ 75 }; 76 static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = { 77 (0 << 4), /* no access */ 78 (1 << 4), /* IOMMU_READ only */ 79 (2 << 4), /* IOMMU_WRITE only */ 80 (3 << 4), /* IOMMU_READ | IOMMU_WRITE */ 81 }; 82 83 static const sysmmu_pte_t *LV2_PROT; 84 static const sysmmu_pte_t SYSMMU_LV2_PROT[] = { 85 ((0 << 9) | (0 << 4)), /* no access */ 86 ((1 << 9) | (1 << 4)), /* IOMMU_READ only */ 87 ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */ 88 ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */ 89 }; 90 static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = { 91 (0 << 2), /* no access */ 92 (1 << 2), /* IOMMU_READ only */ 93 (2 << 2), /* IOMMU_WRITE only */ 94 (3 << 2), /* IOMMU_READ | IOMMU_WRITE */ 95 }; 96 97 #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE) 98 99 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT) 100 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK) 101 #define section_offs(iova) (iova & (SECT_SIZE - 1)) 102 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK) 103 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1)) 104 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK) 105 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1)) 106 107 #define NUM_LV1ENTRIES 4096 108 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) 109 110 static u32 lv1ent_offset(sysmmu_iova_t iova) 111 { 112 return iova >> SECT_ORDER; 113 } 114 115 static u32 lv2ent_offset(sysmmu_iova_t iova) 116 { 117 return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); 118 } 119 120 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) 121 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) 122 123 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) 124 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0)) 125 126 #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2) 127 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1) 128 #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1) 129 #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2) 130 131 #define CTRL_ENABLE 0x5 132 #define CTRL_BLOCK 0x7 133 #define CTRL_DISABLE 0x0 134 135 #define CFG_LRU 0x1 136 #define CFG_EAP (1 << 2) 137 #define CFG_QOS(n) ((n & 0xF) << 7) 138 #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ 139 #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ 140 #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ 141 142 /* common registers */ 143 #define REG_MMU_CTRL 0x000 144 #define REG_MMU_CFG 0x004 145 #define REG_MMU_STATUS 0x008 146 #define REG_MMU_VERSION 0x034 147 148 #define MMU_MAJ_VER(val) ((val) >> 7) 149 #define MMU_MIN_VER(val) ((val) & 0x7F) 150 #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ 151 152 #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) 153 154 /* v1.x - v3.x registers */ 155 #define REG_MMU_FLUSH 0x00C 156 #define REG_MMU_FLUSH_ENTRY 0x010 157 #define REG_PT_BASE_ADDR 0x014 158 #define REG_INT_STATUS 0x018 159 #define REG_INT_CLEAR 0x01C 160 161 #define REG_PAGE_FAULT_ADDR 0x024 162 #define REG_AW_FAULT_ADDR 0x028 163 #define REG_AR_FAULT_ADDR 0x02C 164 #define REG_DEFAULT_SLAVE_ADDR 0x030 165 166 /* v5.x registers */ 167 #define REG_V5_PT_BASE_PFN 0x00C 168 #define REG_V5_MMU_FLUSH_ALL 0x010 169 #define REG_V5_MMU_FLUSH_ENTRY 0x014 170 #define REG_V5_MMU_FLUSH_RANGE 0x018 171 #define REG_V5_MMU_FLUSH_START 0x020 172 #define REG_V5_MMU_FLUSH_END 0x024 173 #define REG_V5_INT_STATUS 0x060 174 #define REG_V5_INT_CLEAR 0x064 175 #define REG_V5_FAULT_AR_VA 0x070 176 #define REG_V5_FAULT_AW_VA 0x080 177 178 #define has_sysmmu(dev) (dev->archdata.iommu != NULL) 179 180 static struct device *dma_dev; 181 static struct kmem_cache *lv2table_kmem_cache; 182 static sysmmu_pte_t *zero_lv2_table; 183 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) 184 185 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) 186 { 187 return pgtable + lv1ent_offset(iova); 188 } 189 190 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) 191 { 192 return (sysmmu_pte_t *)phys_to_virt( 193 lv2table_base(sent)) + lv2ent_offset(iova); 194 } 195 196 /* 197 * IOMMU fault information register 198 */ 199 struct sysmmu_fault_info { 200 unsigned int bit; /* bit number in STATUS register */ 201 unsigned short addr_reg; /* register to read VA fault address */ 202 const char *name; /* human readable fault name */ 203 unsigned int type; /* fault type for report_iommu_fault */ 204 }; 205 206 static const struct sysmmu_fault_info sysmmu_faults[] = { 207 { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ }, 208 { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ }, 209 { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, 210 { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ }, 211 { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, 212 { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, 213 { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, 214 { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, 215 }; 216 217 static const struct sysmmu_fault_info sysmmu_v5_faults[] = { 218 { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ }, 219 { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ }, 220 { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ }, 221 { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, 222 { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, 223 { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE }, 224 { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE }, 225 { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, 226 { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, 227 { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, 228 }; 229 230 /* 231 * This structure is attached to dev.archdata.iommu of the master device 232 * on device add, contains a list of SYSMMU controllers defined by device tree, 233 * which are bound to given master device. It is usually referenced by 'owner' 234 * pointer. 235 */ 236 struct exynos_iommu_owner { 237 struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ 238 struct iommu_domain *domain; /* domain this device is attached */ 239 struct mutex rpm_lock; /* for runtime pm of all sysmmus */ 240 }; 241 242 /* 243 * This structure exynos specific generalization of struct iommu_domain. 244 * It contains list of SYSMMU controllers from all master devices, which has 245 * been attached to this domain and page tables of IO address space defined by 246 * it. It is usually referenced by 'domain' pointer. 247 */ 248 struct exynos_iommu_domain { 249 struct list_head clients; /* list of sysmmu_drvdata.domain_node */ 250 sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ 251 short *lv2entcnt; /* free lv2 entry counter for each section */ 252 spinlock_t lock; /* lock for modyfying list of clients */ 253 spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ 254 struct iommu_domain domain; /* generic domain data structure */ 255 }; 256 257 /* 258 * This structure hold all data of a single SYSMMU controller, this includes 259 * hw resources like registers and clocks, pointers and list nodes to connect 260 * it to all other structures, internal state and parameters read from device 261 * tree. It is usually referenced by 'data' pointer. 262 */ 263 struct sysmmu_drvdata { 264 struct device *sysmmu; /* SYSMMU controller device */ 265 struct device *master; /* master device (owner) */ 266 struct device_link *link; /* runtime PM link to master */ 267 void __iomem *sfrbase; /* our registers */ 268 struct clk *clk; /* SYSMMU's clock */ 269 struct clk *aclk; /* SYSMMU's aclk clock */ 270 struct clk *pclk; /* SYSMMU's pclk clock */ 271 struct clk *clk_master; /* master's device clock */ 272 spinlock_t lock; /* lock for modyfying state */ 273 bool active; /* current status */ 274 struct exynos_iommu_domain *domain; /* domain we belong to */ 275 struct list_head domain_node; /* node for domain clients list */ 276 struct list_head owner_node; /* node for owner controllers list */ 277 phys_addr_t pgtable; /* assigned page table structure */ 278 unsigned int version; /* our version */ 279 280 struct iommu_device iommu; /* IOMMU core handle */ 281 }; 282 283 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) 284 { 285 return container_of(dom, struct exynos_iommu_domain, domain); 286 } 287 288 static void sysmmu_unblock(struct sysmmu_drvdata *data) 289 { 290 writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); 291 } 292 293 static bool sysmmu_block(struct sysmmu_drvdata *data) 294 { 295 int i = 120; 296 297 writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); 298 while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1)) 299 --i; 300 301 if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) { 302 sysmmu_unblock(data); 303 return false; 304 } 305 306 return true; 307 } 308 309 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) 310 { 311 if (MMU_MAJ_VER(data->version) < 5) 312 writel(0x1, data->sfrbase + REG_MMU_FLUSH); 313 else 314 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); 315 } 316 317 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, 318 sysmmu_iova_t iova, unsigned int num_inv) 319 { 320 unsigned int i; 321 322 if (MMU_MAJ_VER(data->version) < 5) { 323 for (i = 0; i < num_inv; i++) { 324 writel((iova & SPAGE_MASK) | 1, 325 data->sfrbase + REG_MMU_FLUSH_ENTRY); 326 iova += SPAGE_SIZE; 327 } 328 } else { 329 if (num_inv == 1) { 330 writel((iova & SPAGE_MASK) | 1, 331 data->sfrbase + REG_V5_MMU_FLUSH_ENTRY); 332 } else { 333 writel((iova & SPAGE_MASK), 334 data->sfrbase + REG_V5_MMU_FLUSH_START); 335 writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, 336 data->sfrbase + REG_V5_MMU_FLUSH_END); 337 writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE); 338 } 339 } 340 } 341 342 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) 343 { 344 if (MMU_MAJ_VER(data->version) < 5) 345 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); 346 else 347 writel(pgd >> PAGE_SHIFT, 348 data->sfrbase + REG_V5_PT_BASE_PFN); 349 350 __sysmmu_tlb_invalidate(data); 351 } 352 353 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data) 354 { 355 BUG_ON(clk_prepare_enable(data->clk_master)); 356 BUG_ON(clk_prepare_enable(data->clk)); 357 BUG_ON(clk_prepare_enable(data->pclk)); 358 BUG_ON(clk_prepare_enable(data->aclk)); 359 } 360 361 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) 362 { 363 clk_disable_unprepare(data->aclk); 364 clk_disable_unprepare(data->pclk); 365 clk_disable_unprepare(data->clk); 366 clk_disable_unprepare(data->clk_master); 367 } 368 369 static void __sysmmu_get_version(struct sysmmu_drvdata *data) 370 { 371 u32 ver; 372 373 __sysmmu_enable_clocks(data); 374 375 ver = readl(data->sfrbase + REG_MMU_VERSION); 376 377 /* controllers on some SoCs don't report proper version */ 378 if (ver == 0x80000001u) 379 data->version = MAKE_MMU_VER(1, 0); 380 else 381 data->version = MMU_RAW_VER(ver); 382 383 dev_dbg(data->sysmmu, "hardware version: %d.%d\n", 384 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); 385 386 __sysmmu_disable_clocks(data); 387 } 388 389 static void show_fault_information(struct sysmmu_drvdata *data, 390 const struct sysmmu_fault_info *finfo, 391 sysmmu_iova_t fault_addr) 392 { 393 sysmmu_pte_t *ent; 394 395 dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n", 396 dev_name(data->master), finfo->name, fault_addr); 397 dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable); 398 ent = section_entry(phys_to_virt(data->pgtable), fault_addr); 399 dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent); 400 if (lv1ent_page(ent)) { 401 ent = page_entry(ent, fault_addr); 402 dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent); 403 } 404 } 405 406 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) 407 { 408 /* SYSMMU is in blocked state when interrupt occurred. */ 409 struct sysmmu_drvdata *data = dev_id; 410 const struct sysmmu_fault_info *finfo; 411 unsigned int i, n, itype; 412 sysmmu_iova_t fault_addr = -1; 413 unsigned short reg_status, reg_clear; 414 int ret = -ENOSYS; 415 416 WARN_ON(!data->active); 417 418 if (MMU_MAJ_VER(data->version) < 5) { 419 reg_status = REG_INT_STATUS; 420 reg_clear = REG_INT_CLEAR; 421 finfo = sysmmu_faults; 422 n = ARRAY_SIZE(sysmmu_faults); 423 } else { 424 reg_status = REG_V5_INT_STATUS; 425 reg_clear = REG_V5_INT_CLEAR; 426 finfo = sysmmu_v5_faults; 427 n = ARRAY_SIZE(sysmmu_v5_faults); 428 } 429 430 spin_lock(&data->lock); 431 432 clk_enable(data->clk_master); 433 434 itype = __ffs(readl(data->sfrbase + reg_status)); 435 for (i = 0; i < n; i++, finfo++) 436 if (finfo->bit == itype) 437 break; 438 /* unknown/unsupported fault */ 439 BUG_ON(i == n); 440 441 /* print debug message */ 442 fault_addr = readl(data->sfrbase + finfo->addr_reg); 443 show_fault_information(data, finfo, fault_addr); 444 445 if (data->domain) 446 ret = report_iommu_fault(&data->domain->domain, 447 data->master, fault_addr, finfo->type); 448 /* fault is not recovered by fault handler */ 449 BUG_ON(ret != 0); 450 451 writel(1 << itype, data->sfrbase + reg_clear); 452 453 sysmmu_unblock(data); 454 455 clk_disable(data->clk_master); 456 457 spin_unlock(&data->lock); 458 459 return IRQ_HANDLED; 460 } 461 462 static void __sysmmu_disable(struct sysmmu_drvdata *data) 463 { 464 unsigned long flags; 465 466 clk_enable(data->clk_master); 467 468 spin_lock_irqsave(&data->lock, flags); 469 writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); 470 writel(0, data->sfrbase + REG_MMU_CFG); 471 data->active = false; 472 spin_unlock_irqrestore(&data->lock, flags); 473 474 __sysmmu_disable_clocks(data); 475 } 476 477 static void __sysmmu_init_config(struct sysmmu_drvdata *data) 478 { 479 unsigned int cfg; 480 481 if (data->version <= MAKE_MMU_VER(3, 1)) 482 cfg = CFG_LRU | CFG_QOS(15); 483 else if (data->version <= MAKE_MMU_VER(3, 2)) 484 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL; 485 else 486 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN; 487 488 cfg |= CFG_EAP; /* enable access protection bits check */ 489 490 writel(cfg, data->sfrbase + REG_MMU_CFG); 491 } 492 493 static void __sysmmu_enable(struct sysmmu_drvdata *data) 494 { 495 unsigned long flags; 496 497 __sysmmu_enable_clocks(data); 498 499 spin_lock_irqsave(&data->lock, flags); 500 writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); 501 __sysmmu_init_config(data); 502 __sysmmu_set_ptbase(data, data->pgtable); 503 writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); 504 data->active = true; 505 spin_unlock_irqrestore(&data->lock, flags); 506 507 /* 508 * SYSMMU driver keeps master's clock enabled only for the short 509 * time, while accessing the registers. For performing address 510 * translation during DMA transaction it relies on the client 511 * driver to enable it. 512 */ 513 clk_disable(data->clk_master); 514 } 515 516 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, 517 sysmmu_iova_t iova) 518 { 519 unsigned long flags; 520 521 spin_lock_irqsave(&data->lock, flags); 522 if (data->active && data->version >= MAKE_MMU_VER(3, 3)) { 523 clk_enable(data->clk_master); 524 if (sysmmu_block(data)) { 525 if (data->version >= MAKE_MMU_VER(5, 0)) 526 __sysmmu_tlb_invalidate(data); 527 else 528 __sysmmu_tlb_invalidate_entry(data, iova, 1); 529 sysmmu_unblock(data); 530 } 531 clk_disable(data->clk_master); 532 } 533 spin_unlock_irqrestore(&data->lock, flags); 534 } 535 536 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, 537 sysmmu_iova_t iova, size_t size) 538 { 539 unsigned long flags; 540 541 spin_lock_irqsave(&data->lock, flags); 542 if (data->active) { 543 unsigned int num_inv = 1; 544 545 clk_enable(data->clk_master); 546 547 /* 548 * L2TLB invalidation required 549 * 4KB page: 1 invalidation 550 * 64KB page: 16 invalidations 551 * 1MB page: 64 invalidations 552 * because it is set-associative TLB 553 * with 8-way and 64 sets. 554 * 1MB page can be cached in one of all sets. 555 * 64KB page can be one of 16 consecutive sets. 556 */ 557 if (MMU_MAJ_VER(data->version) == 2) 558 num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); 559 560 if (sysmmu_block(data)) { 561 __sysmmu_tlb_invalidate_entry(data, iova, num_inv); 562 sysmmu_unblock(data); 563 } 564 clk_disable(data->clk_master); 565 } 566 spin_unlock_irqrestore(&data->lock, flags); 567 } 568 569 static const struct iommu_ops exynos_iommu_ops; 570 571 static int __init exynos_sysmmu_probe(struct platform_device *pdev) 572 { 573 int irq, ret; 574 struct device *dev = &pdev->dev; 575 struct sysmmu_drvdata *data; 576 struct resource *res; 577 578 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 579 if (!data) 580 return -ENOMEM; 581 582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 583 data->sfrbase = devm_ioremap_resource(dev, res); 584 if (IS_ERR(data->sfrbase)) 585 return PTR_ERR(data->sfrbase); 586 587 irq = platform_get_irq(pdev, 0); 588 if (irq <= 0) { 589 dev_err(dev, "Unable to find IRQ resource\n"); 590 return irq; 591 } 592 593 ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, 594 dev_name(dev), data); 595 if (ret) { 596 dev_err(dev, "Unabled to register handler of irq %d\n", irq); 597 return ret; 598 } 599 600 data->clk = devm_clk_get(dev, "sysmmu"); 601 if (PTR_ERR(data->clk) == -ENOENT) 602 data->clk = NULL; 603 else if (IS_ERR(data->clk)) 604 return PTR_ERR(data->clk); 605 606 data->aclk = devm_clk_get(dev, "aclk"); 607 if (PTR_ERR(data->aclk) == -ENOENT) 608 data->aclk = NULL; 609 else if (IS_ERR(data->aclk)) 610 return PTR_ERR(data->aclk); 611 612 data->pclk = devm_clk_get(dev, "pclk"); 613 if (PTR_ERR(data->pclk) == -ENOENT) 614 data->pclk = NULL; 615 else if (IS_ERR(data->pclk)) 616 return PTR_ERR(data->pclk); 617 618 if (!data->clk && (!data->aclk || !data->pclk)) { 619 dev_err(dev, "Failed to get device clock(s)!\n"); 620 return -ENOSYS; 621 } 622 623 data->clk_master = devm_clk_get(dev, "master"); 624 if (PTR_ERR(data->clk_master) == -ENOENT) 625 data->clk_master = NULL; 626 else if (IS_ERR(data->clk_master)) 627 return PTR_ERR(data->clk_master); 628 629 data->sysmmu = dev; 630 spin_lock_init(&data->lock); 631 632 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 633 dev_name(data->sysmmu)); 634 if (ret) 635 return ret; 636 637 iommu_device_set_ops(&data->iommu, &exynos_iommu_ops); 638 iommu_device_set_fwnode(&data->iommu, &dev->of_node->fwnode); 639 640 ret = iommu_device_register(&data->iommu); 641 if (ret) 642 return ret; 643 644 platform_set_drvdata(pdev, data); 645 646 __sysmmu_get_version(data); 647 if (PG_ENT_SHIFT < 0) { 648 if (MMU_MAJ_VER(data->version) < 5) { 649 PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; 650 LV1_PROT = SYSMMU_LV1_PROT; 651 LV2_PROT = SYSMMU_LV2_PROT; 652 } else { 653 PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT; 654 LV1_PROT = SYSMMU_V5_LV1_PROT; 655 LV2_PROT = SYSMMU_V5_LV2_PROT; 656 } 657 } 658 659 /* 660 * use the first registered sysmmu device for performing 661 * dma mapping operations on iommu page tables (cpu cache flush) 662 */ 663 if (!dma_dev) 664 dma_dev = &pdev->dev; 665 666 pm_runtime_enable(dev); 667 668 return 0; 669 } 670 671 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) 672 { 673 struct sysmmu_drvdata *data = dev_get_drvdata(dev); 674 struct device *master = data->master; 675 676 if (master) { 677 struct exynos_iommu_owner *owner = master->archdata.iommu; 678 679 mutex_lock(&owner->rpm_lock); 680 if (data->domain) { 681 dev_dbg(data->sysmmu, "saving state\n"); 682 __sysmmu_disable(data); 683 } 684 mutex_unlock(&owner->rpm_lock); 685 } 686 return 0; 687 } 688 689 static int __maybe_unused exynos_sysmmu_resume(struct device *dev) 690 { 691 struct sysmmu_drvdata *data = dev_get_drvdata(dev); 692 struct device *master = data->master; 693 694 if (master) { 695 struct exynos_iommu_owner *owner = master->archdata.iommu; 696 697 mutex_lock(&owner->rpm_lock); 698 if (data->domain) { 699 dev_dbg(data->sysmmu, "restoring state\n"); 700 __sysmmu_enable(data); 701 } 702 mutex_unlock(&owner->rpm_lock); 703 } 704 return 0; 705 } 706 707 static const struct dev_pm_ops sysmmu_pm_ops = { 708 SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL) 709 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 710 pm_runtime_force_resume) 711 }; 712 713 static const struct of_device_id sysmmu_of_match[] = { 714 { .compatible = "samsung,exynos-sysmmu", }, 715 { }, 716 }; 717 718 static struct platform_driver exynos_sysmmu_driver __refdata = { 719 .probe = exynos_sysmmu_probe, 720 .driver = { 721 .name = "exynos-sysmmu", 722 .of_match_table = sysmmu_of_match, 723 .pm = &sysmmu_pm_ops, 724 .suppress_bind_attrs = true, 725 } 726 }; 727 728 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) 729 { 730 dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), 731 DMA_TO_DEVICE); 732 *ent = cpu_to_le32(val); 733 dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), 734 DMA_TO_DEVICE); 735 } 736 737 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) 738 { 739 struct exynos_iommu_domain *domain; 740 dma_addr_t handle; 741 int i; 742 743 /* Check if correct PTE offsets are initialized */ 744 BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev); 745 746 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 747 if (!domain) 748 return NULL; 749 750 if (type == IOMMU_DOMAIN_DMA) { 751 if (iommu_get_dma_cookie(&domain->domain) != 0) 752 goto err_pgtable; 753 } else if (type != IOMMU_DOMAIN_UNMANAGED) { 754 goto err_pgtable; 755 } 756 757 domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); 758 if (!domain->pgtable) 759 goto err_dma_cookie; 760 761 domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); 762 if (!domain->lv2entcnt) 763 goto err_counter; 764 765 /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ 766 for (i = 0; i < NUM_LV1ENTRIES; i++) 767 domain->pgtable[i] = ZERO_LV2LINK; 768 769 handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, 770 DMA_TO_DEVICE); 771 /* For mapping page table entries we rely on dma == phys */ 772 BUG_ON(handle != virt_to_phys(domain->pgtable)); 773 if (dma_mapping_error(dma_dev, handle)) 774 goto err_lv2ent; 775 776 spin_lock_init(&domain->lock); 777 spin_lock_init(&domain->pgtablelock); 778 INIT_LIST_HEAD(&domain->clients); 779 780 domain->domain.geometry.aperture_start = 0; 781 domain->domain.geometry.aperture_end = ~0UL; 782 domain->domain.geometry.force_aperture = true; 783 784 return &domain->domain; 785 786 err_lv2ent: 787 free_pages((unsigned long)domain->lv2entcnt, 1); 788 err_counter: 789 free_pages((unsigned long)domain->pgtable, 2); 790 err_dma_cookie: 791 if (type == IOMMU_DOMAIN_DMA) 792 iommu_put_dma_cookie(&domain->domain); 793 err_pgtable: 794 kfree(domain); 795 return NULL; 796 } 797 798 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) 799 { 800 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 801 struct sysmmu_drvdata *data, *next; 802 unsigned long flags; 803 int i; 804 805 WARN_ON(!list_empty(&domain->clients)); 806 807 spin_lock_irqsave(&domain->lock, flags); 808 809 list_for_each_entry_safe(data, next, &domain->clients, domain_node) { 810 spin_lock(&data->lock); 811 __sysmmu_disable(data); 812 data->pgtable = 0; 813 data->domain = NULL; 814 list_del_init(&data->domain_node); 815 spin_unlock(&data->lock); 816 } 817 818 spin_unlock_irqrestore(&domain->lock, flags); 819 820 if (iommu_domain->type == IOMMU_DOMAIN_DMA) 821 iommu_put_dma_cookie(iommu_domain); 822 823 dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, 824 DMA_TO_DEVICE); 825 826 for (i = 0; i < NUM_LV1ENTRIES; i++) 827 if (lv1ent_page(domain->pgtable + i)) { 828 phys_addr_t base = lv2table_base(domain->pgtable + i); 829 830 dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, 831 DMA_TO_DEVICE); 832 kmem_cache_free(lv2table_kmem_cache, 833 phys_to_virt(base)); 834 } 835 836 free_pages((unsigned long)domain->pgtable, 2); 837 free_pages((unsigned long)domain->lv2entcnt, 1); 838 kfree(domain); 839 } 840 841 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, 842 struct device *dev) 843 { 844 struct exynos_iommu_owner *owner = dev->archdata.iommu; 845 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 846 phys_addr_t pagetable = virt_to_phys(domain->pgtable); 847 struct sysmmu_drvdata *data, *next; 848 unsigned long flags; 849 850 if (!has_sysmmu(dev) || owner->domain != iommu_domain) 851 return; 852 853 mutex_lock(&owner->rpm_lock); 854 855 list_for_each_entry(data, &owner->controllers, owner_node) { 856 pm_runtime_get_noresume(data->sysmmu); 857 if (pm_runtime_active(data->sysmmu)) 858 __sysmmu_disable(data); 859 pm_runtime_put(data->sysmmu); 860 } 861 862 spin_lock_irqsave(&domain->lock, flags); 863 list_for_each_entry_safe(data, next, &domain->clients, domain_node) { 864 spin_lock(&data->lock); 865 data->pgtable = 0; 866 data->domain = NULL; 867 list_del_init(&data->domain_node); 868 spin_unlock(&data->lock); 869 } 870 owner->domain = NULL; 871 spin_unlock_irqrestore(&domain->lock, flags); 872 873 mutex_unlock(&owner->rpm_lock); 874 875 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__, 876 &pagetable); 877 } 878 879 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, 880 struct device *dev) 881 { 882 struct exynos_iommu_owner *owner = dev->archdata.iommu; 883 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 884 struct sysmmu_drvdata *data; 885 phys_addr_t pagetable = virt_to_phys(domain->pgtable); 886 unsigned long flags; 887 888 if (!has_sysmmu(dev)) 889 return -ENODEV; 890 891 if (owner->domain) 892 exynos_iommu_detach_device(owner->domain, dev); 893 894 mutex_lock(&owner->rpm_lock); 895 896 spin_lock_irqsave(&domain->lock, flags); 897 list_for_each_entry(data, &owner->controllers, owner_node) { 898 spin_lock(&data->lock); 899 data->pgtable = pagetable; 900 data->domain = domain; 901 list_add_tail(&data->domain_node, &domain->clients); 902 spin_unlock(&data->lock); 903 } 904 owner->domain = iommu_domain; 905 spin_unlock_irqrestore(&domain->lock, flags); 906 907 list_for_each_entry(data, &owner->controllers, owner_node) { 908 pm_runtime_get_noresume(data->sysmmu); 909 if (pm_runtime_active(data->sysmmu)) 910 __sysmmu_enable(data); 911 pm_runtime_put(data->sysmmu); 912 } 913 914 mutex_unlock(&owner->rpm_lock); 915 916 dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__, 917 &pagetable); 918 919 return 0; 920 } 921 922 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, 923 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) 924 { 925 if (lv1ent_section(sent)) { 926 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); 927 return ERR_PTR(-EADDRINUSE); 928 } 929 930 if (lv1ent_fault(sent)) { 931 dma_addr_t handle; 932 sysmmu_pte_t *pent; 933 bool need_flush_flpd_cache = lv1ent_zero(sent); 934 935 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); 936 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1)); 937 if (!pent) 938 return ERR_PTR(-ENOMEM); 939 940 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); 941 kmemleak_ignore(pent); 942 *pgcounter = NUM_LV2ENTRIES; 943 handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE, 944 DMA_TO_DEVICE); 945 if (dma_mapping_error(dma_dev, handle)) { 946 kmem_cache_free(lv2table_kmem_cache, pent); 947 return ERR_PTR(-EADDRINUSE); 948 } 949 950 /* 951 * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, 952 * FLPD cache may cache the address of zero_l2_table. This 953 * function replaces the zero_l2_table with new L2 page table 954 * to write valid mappings. 955 * Accessing the valid area may cause page fault since FLPD 956 * cache may still cache zero_l2_table for the valid area 957 * instead of new L2 page table that has the mapping 958 * information of the valid area. 959 * Thus any replacement of zero_l2_table with other valid L2 960 * page table must involve FLPD cache invalidation for System 961 * MMU v3.3. 962 * FLPD cache invalidation is performed with TLB invalidation 963 * by VPN without blocking. It is safe to invalidate TLB without 964 * blocking because the target address of TLB invalidation is 965 * not currently mapped. 966 */ 967 if (need_flush_flpd_cache) { 968 struct sysmmu_drvdata *data; 969 970 spin_lock(&domain->lock); 971 list_for_each_entry(data, &domain->clients, domain_node) 972 sysmmu_tlb_invalidate_flpdcache(data, iova); 973 spin_unlock(&domain->lock); 974 } 975 } 976 977 return page_entry(sent, iova); 978 } 979 980 static int lv1set_section(struct exynos_iommu_domain *domain, 981 sysmmu_pte_t *sent, sysmmu_iova_t iova, 982 phys_addr_t paddr, int prot, short *pgcnt) 983 { 984 if (lv1ent_section(sent)) { 985 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", 986 iova); 987 return -EADDRINUSE; 988 } 989 990 if (lv1ent_page(sent)) { 991 if (*pgcnt != NUM_LV2ENTRIES) { 992 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", 993 iova); 994 return -EADDRINUSE; 995 } 996 997 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); 998 *pgcnt = 0; 999 } 1000 1001 update_pte(sent, mk_lv1ent_sect(paddr, prot)); 1002 1003 spin_lock(&domain->lock); 1004 if (lv1ent_page_zero(sent)) { 1005 struct sysmmu_drvdata *data; 1006 /* 1007 * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD 1008 * entry by speculative prefetch of SLPD which has no mapping. 1009 */ 1010 list_for_each_entry(data, &domain->clients, domain_node) 1011 sysmmu_tlb_invalidate_flpdcache(data, iova); 1012 } 1013 spin_unlock(&domain->lock); 1014 1015 return 0; 1016 } 1017 1018 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, 1019 int prot, short *pgcnt) 1020 { 1021 if (size == SPAGE_SIZE) { 1022 if (WARN_ON(!lv2ent_fault(pent))) 1023 return -EADDRINUSE; 1024 1025 update_pte(pent, mk_lv2ent_spage(paddr, prot)); 1026 *pgcnt -= 1; 1027 } else { /* size == LPAGE_SIZE */ 1028 int i; 1029 dma_addr_t pent_base = virt_to_phys(pent); 1030 1031 dma_sync_single_for_cpu(dma_dev, pent_base, 1032 sizeof(*pent) * SPAGES_PER_LPAGE, 1033 DMA_TO_DEVICE); 1034 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { 1035 if (WARN_ON(!lv2ent_fault(pent))) { 1036 if (i > 0) 1037 memset(pent - i, 0, sizeof(*pent) * i); 1038 return -EADDRINUSE; 1039 } 1040 1041 *pent = mk_lv2ent_lpage(paddr, prot); 1042 } 1043 dma_sync_single_for_device(dma_dev, pent_base, 1044 sizeof(*pent) * SPAGES_PER_LPAGE, 1045 DMA_TO_DEVICE); 1046 *pgcnt -= SPAGES_PER_LPAGE; 1047 } 1048 1049 return 0; 1050 } 1051 1052 /* 1053 * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: 1054 * 1055 * System MMU v3.x has advanced logic to improve address translation 1056 * performance with caching more page table entries by a page table walk. 1057 * However, the logic has a bug that while caching faulty page table entries, 1058 * System MMU reports page fault if the cached fault entry is hit even though 1059 * the fault entry is updated to a valid entry after the entry is cached. 1060 * To prevent caching faulty page table entries which may be updated to valid 1061 * entries later, the virtual memory manager should care about the workaround 1062 * for the problem. The following describes the workaround. 1063 * 1064 * Any two consecutive I/O virtual address regions must have a hole of 128KiB 1065 * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). 1066 * 1067 * Precisely, any start address of I/O virtual region must be aligned with 1068 * the following sizes for System MMU v3.1 and v3.2. 1069 * System MMU v3.1: 128KiB 1070 * System MMU v3.2: 256KiB 1071 * 1072 * Because System MMU v3.3 caches page table entries more aggressively, it needs 1073 * more workarounds. 1074 * - Any two consecutive I/O virtual regions must have a hole of size larger 1075 * than or equal to 128KiB. 1076 * - Start address of an I/O virtual region must be aligned by 128KiB. 1077 */ 1078 static int exynos_iommu_map(struct iommu_domain *iommu_domain, 1079 unsigned long l_iova, phys_addr_t paddr, size_t size, 1080 int prot) 1081 { 1082 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 1083 sysmmu_pte_t *entry; 1084 sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; 1085 unsigned long flags; 1086 int ret = -ENOMEM; 1087 1088 BUG_ON(domain->pgtable == NULL); 1089 prot &= SYSMMU_SUPPORTED_PROT_BITS; 1090 1091 spin_lock_irqsave(&domain->pgtablelock, flags); 1092 1093 entry = section_entry(domain->pgtable, iova); 1094 1095 if (size == SECT_SIZE) { 1096 ret = lv1set_section(domain, entry, iova, paddr, prot, 1097 &domain->lv2entcnt[lv1ent_offset(iova)]); 1098 } else { 1099 sysmmu_pte_t *pent; 1100 1101 pent = alloc_lv2entry(domain, entry, iova, 1102 &domain->lv2entcnt[lv1ent_offset(iova)]); 1103 1104 if (IS_ERR(pent)) 1105 ret = PTR_ERR(pent); 1106 else 1107 ret = lv2set_page(pent, paddr, size, prot, 1108 &domain->lv2entcnt[lv1ent_offset(iova)]); 1109 } 1110 1111 if (ret) 1112 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", 1113 __func__, ret, size, iova); 1114 1115 spin_unlock_irqrestore(&domain->pgtablelock, flags); 1116 1117 return ret; 1118 } 1119 1120 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, 1121 sysmmu_iova_t iova, size_t size) 1122 { 1123 struct sysmmu_drvdata *data; 1124 unsigned long flags; 1125 1126 spin_lock_irqsave(&domain->lock, flags); 1127 1128 list_for_each_entry(data, &domain->clients, domain_node) 1129 sysmmu_tlb_invalidate_entry(data, iova, size); 1130 1131 spin_unlock_irqrestore(&domain->lock, flags); 1132 } 1133 1134 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, 1135 unsigned long l_iova, size_t size) 1136 { 1137 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 1138 sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; 1139 sysmmu_pte_t *ent; 1140 size_t err_pgsize; 1141 unsigned long flags; 1142 1143 BUG_ON(domain->pgtable == NULL); 1144 1145 spin_lock_irqsave(&domain->pgtablelock, flags); 1146 1147 ent = section_entry(domain->pgtable, iova); 1148 1149 if (lv1ent_section(ent)) { 1150 if (WARN_ON(size < SECT_SIZE)) { 1151 err_pgsize = SECT_SIZE; 1152 goto err; 1153 } 1154 1155 /* workaround for h/w bug in System MMU v3.3 */ 1156 update_pte(ent, ZERO_LV2LINK); 1157 size = SECT_SIZE; 1158 goto done; 1159 } 1160 1161 if (unlikely(lv1ent_fault(ent))) { 1162 if (size > SECT_SIZE) 1163 size = SECT_SIZE; 1164 goto done; 1165 } 1166 1167 /* lv1ent_page(sent) == true here */ 1168 1169 ent = page_entry(ent, iova); 1170 1171 if (unlikely(lv2ent_fault(ent))) { 1172 size = SPAGE_SIZE; 1173 goto done; 1174 } 1175 1176 if (lv2ent_small(ent)) { 1177 update_pte(ent, 0); 1178 size = SPAGE_SIZE; 1179 domain->lv2entcnt[lv1ent_offset(iova)] += 1; 1180 goto done; 1181 } 1182 1183 /* lv1ent_large(ent) == true here */ 1184 if (WARN_ON(size < LPAGE_SIZE)) { 1185 err_pgsize = LPAGE_SIZE; 1186 goto err; 1187 } 1188 1189 dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), 1190 sizeof(*ent) * SPAGES_PER_LPAGE, 1191 DMA_TO_DEVICE); 1192 memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); 1193 dma_sync_single_for_device(dma_dev, virt_to_phys(ent), 1194 sizeof(*ent) * SPAGES_PER_LPAGE, 1195 DMA_TO_DEVICE); 1196 size = LPAGE_SIZE; 1197 domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; 1198 done: 1199 spin_unlock_irqrestore(&domain->pgtablelock, flags); 1200 1201 exynos_iommu_tlb_invalidate_entry(domain, iova, size); 1202 1203 return size; 1204 err: 1205 spin_unlock_irqrestore(&domain->pgtablelock, flags); 1206 1207 pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", 1208 __func__, size, iova, err_pgsize); 1209 1210 return 0; 1211 } 1212 1213 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, 1214 dma_addr_t iova) 1215 { 1216 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 1217 sysmmu_pte_t *entry; 1218 unsigned long flags; 1219 phys_addr_t phys = 0; 1220 1221 spin_lock_irqsave(&domain->pgtablelock, flags); 1222 1223 entry = section_entry(domain->pgtable, iova); 1224 1225 if (lv1ent_section(entry)) { 1226 phys = section_phys(entry) + section_offs(iova); 1227 } else if (lv1ent_page(entry)) { 1228 entry = page_entry(entry, iova); 1229 1230 if (lv2ent_large(entry)) 1231 phys = lpage_phys(entry) + lpage_offs(iova); 1232 else if (lv2ent_small(entry)) 1233 phys = spage_phys(entry) + spage_offs(iova); 1234 } 1235 1236 spin_unlock_irqrestore(&domain->pgtablelock, flags); 1237 1238 return phys; 1239 } 1240 1241 static struct iommu_group *get_device_iommu_group(struct device *dev) 1242 { 1243 struct iommu_group *group; 1244 1245 group = iommu_group_get(dev); 1246 if (!group) 1247 group = iommu_group_alloc(); 1248 1249 return group; 1250 } 1251 1252 static int exynos_iommu_add_device(struct device *dev) 1253 { 1254 struct exynos_iommu_owner *owner = dev->archdata.iommu; 1255 struct sysmmu_drvdata *data; 1256 struct iommu_group *group; 1257 1258 if (!has_sysmmu(dev)) 1259 return -ENODEV; 1260 1261 group = iommu_group_get_for_dev(dev); 1262 1263 if (IS_ERR(group)) 1264 return PTR_ERR(group); 1265 1266 list_for_each_entry(data, &owner->controllers, owner_node) { 1267 /* 1268 * SYSMMU will be runtime activated via device link 1269 * (dependency) to its master device, so there are no 1270 * direct calls to pm_runtime_get/put in this driver. 1271 */ 1272 data->link = device_link_add(dev, data->sysmmu, 1273 DL_FLAG_PM_RUNTIME); 1274 } 1275 iommu_group_put(group); 1276 1277 return 0; 1278 } 1279 1280 static void exynos_iommu_remove_device(struct device *dev) 1281 { 1282 struct exynos_iommu_owner *owner = dev->archdata.iommu; 1283 struct sysmmu_drvdata *data; 1284 1285 if (!has_sysmmu(dev)) 1286 return; 1287 1288 if (owner->domain) { 1289 struct iommu_group *group = iommu_group_get(dev); 1290 1291 if (group) { 1292 WARN_ON(owner->domain != 1293 iommu_group_default_domain(group)); 1294 exynos_iommu_detach_device(owner->domain, dev); 1295 iommu_group_put(group); 1296 } 1297 } 1298 iommu_group_remove_device(dev); 1299 1300 list_for_each_entry(data, &owner->controllers, owner_node) 1301 device_link_del(data->link); 1302 } 1303 1304 static int exynos_iommu_of_xlate(struct device *dev, 1305 struct of_phandle_args *spec) 1306 { 1307 struct exynos_iommu_owner *owner = dev->archdata.iommu; 1308 struct platform_device *sysmmu = of_find_device_by_node(spec->np); 1309 struct sysmmu_drvdata *data, *entry; 1310 1311 if (!sysmmu) 1312 return -ENODEV; 1313 1314 data = platform_get_drvdata(sysmmu); 1315 if (!data) 1316 return -ENODEV; 1317 1318 if (!owner) { 1319 owner = kzalloc(sizeof(*owner), GFP_KERNEL); 1320 if (!owner) 1321 return -ENOMEM; 1322 1323 INIT_LIST_HEAD(&owner->controllers); 1324 mutex_init(&owner->rpm_lock); 1325 dev->archdata.iommu = owner; 1326 } 1327 1328 list_for_each_entry(entry, &owner->controllers, owner_node) 1329 if (entry == data) 1330 return 0; 1331 1332 list_add_tail(&data->owner_node, &owner->controllers); 1333 data->master = dev; 1334 1335 return 0; 1336 } 1337 1338 static const struct iommu_ops exynos_iommu_ops = { 1339 .domain_alloc = exynos_iommu_domain_alloc, 1340 .domain_free = exynos_iommu_domain_free, 1341 .attach_dev = exynos_iommu_attach_device, 1342 .detach_dev = exynos_iommu_detach_device, 1343 .map = exynos_iommu_map, 1344 .unmap = exynos_iommu_unmap, 1345 .map_sg = default_iommu_map_sg, 1346 .iova_to_phys = exynos_iommu_iova_to_phys, 1347 .device_group = get_device_iommu_group, 1348 .add_device = exynos_iommu_add_device, 1349 .remove_device = exynos_iommu_remove_device, 1350 .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, 1351 .of_xlate = exynos_iommu_of_xlate, 1352 }; 1353 1354 static int __init exynos_iommu_init(void) 1355 { 1356 int ret; 1357 1358 lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", 1359 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); 1360 if (!lv2table_kmem_cache) { 1361 pr_err("%s: Failed to create kmem cache\n", __func__); 1362 return -ENOMEM; 1363 } 1364 1365 ret = platform_driver_register(&exynos_sysmmu_driver); 1366 if (ret) { 1367 pr_err("%s: Failed to register driver\n", __func__); 1368 goto err_reg_driver; 1369 } 1370 1371 zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); 1372 if (zero_lv2_table == NULL) { 1373 pr_err("%s: Failed to allocate zero level2 page table\n", 1374 __func__); 1375 ret = -ENOMEM; 1376 goto err_zero_lv2; 1377 } 1378 1379 ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); 1380 if (ret) { 1381 pr_err("%s: Failed to register exynos-iommu driver.\n", 1382 __func__); 1383 goto err_set_iommu; 1384 } 1385 1386 return 0; 1387 err_set_iommu: 1388 kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); 1389 err_zero_lv2: 1390 platform_driver_unregister(&exynos_sysmmu_driver); 1391 err_reg_driver: 1392 kmem_cache_destroy(lv2table_kmem_cache); 1393 return ret; 1394 } 1395 core_initcall(exynos_iommu_init); 1396 1397 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu", NULL); 1398