1 /* 2 * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG 11 #define DEBUG 12 #endif 13 14 #include <linux/clk.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/iommu.h> 19 #include <linux/interrupt.h> 20 #include <linux/list.h> 21 #include <linux/of.h> 22 #include <linux/of_iommu.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/slab.h> 27 #include <linux/dma-iommu.h> 28 29 typedef u32 sysmmu_iova_t; 30 typedef u32 sysmmu_pte_t; 31 32 /* We do not consider super section mapping (16MB) */ 33 #define SECT_ORDER 20 34 #define LPAGE_ORDER 16 35 #define SPAGE_ORDER 12 36 37 #define SECT_SIZE (1 << SECT_ORDER) 38 #define LPAGE_SIZE (1 << LPAGE_ORDER) 39 #define SPAGE_SIZE (1 << SPAGE_ORDER) 40 41 #define SECT_MASK (~(SECT_SIZE - 1)) 42 #define LPAGE_MASK (~(LPAGE_SIZE - 1)) 43 #define SPAGE_MASK (~(SPAGE_SIZE - 1)) 44 45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ 46 ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) 47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) 48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) 49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ 50 ((*(sent) & 3) == 1)) 51 #define lv1ent_section(sent) ((*(sent) & 3) == 2) 52 53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0) 54 #define lv2ent_small(pent) ((*(pent) & 2) == 2) 55 #define lv2ent_large(pent) ((*(pent) & 3) == 1) 56 57 #ifdef CONFIG_BIG_ENDIAN 58 #warning "revisit driver if we can enable big-endian ptes" 59 #endif 60 61 /* 62 * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces 63 * v5.0 introduced support for 36bit physical address space by shifting 64 * all page entry values by 4 bits. 65 * All SYSMMU controllers in the system support the address spaces of the same 66 * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper 67 * value (0 or 4). 68 */ 69 static short PG_ENT_SHIFT = -1; 70 #define SYSMMU_PG_ENT_SHIFT 0 71 #define SYSMMU_V5_PG_ENT_SHIFT 4 72 73 static const sysmmu_pte_t *LV1_PROT; 74 static const sysmmu_pte_t SYSMMU_LV1_PROT[] = { 75 ((0 << 15) | (0 << 10)), /* no access */ 76 ((1 << 15) | (1 << 10)), /* IOMMU_READ only */ 77 ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */ 78 ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */ 79 }; 80 static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = { 81 (0 << 4), /* no access */ 82 (1 << 4), /* IOMMU_READ only */ 83 (2 << 4), /* IOMMU_WRITE only */ 84 (3 << 4), /* IOMMU_READ | IOMMU_WRITE */ 85 }; 86 87 static const sysmmu_pte_t *LV2_PROT; 88 static const sysmmu_pte_t SYSMMU_LV2_PROT[] = { 89 ((0 << 9) | (0 << 4)), /* no access */ 90 ((1 << 9) | (1 << 4)), /* IOMMU_READ only */ 91 ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */ 92 ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */ 93 }; 94 static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = { 95 (0 << 2), /* no access */ 96 (1 << 2), /* IOMMU_READ only */ 97 (2 << 2), /* IOMMU_WRITE only */ 98 (3 << 2), /* IOMMU_READ | IOMMU_WRITE */ 99 }; 100 101 #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE) 102 103 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT) 104 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK) 105 #define section_offs(iova) (iova & (SECT_SIZE - 1)) 106 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK) 107 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1)) 108 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK) 109 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1)) 110 111 #define NUM_LV1ENTRIES 4096 112 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) 113 114 static u32 lv1ent_offset(sysmmu_iova_t iova) 115 { 116 return iova >> SECT_ORDER; 117 } 118 119 static u32 lv2ent_offset(sysmmu_iova_t iova) 120 { 121 return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); 122 } 123 124 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) 125 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) 126 127 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) 128 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0)) 129 130 #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2) 131 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1) 132 #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1) 133 #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2) 134 135 #define CTRL_ENABLE 0x5 136 #define CTRL_BLOCK 0x7 137 #define CTRL_DISABLE 0x0 138 139 #define CFG_LRU 0x1 140 #define CFG_EAP (1 << 2) 141 #define CFG_QOS(n) ((n & 0xF) << 7) 142 #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ 143 #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ 144 #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ 145 146 /* common registers */ 147 #define REG_MMU_CTRL 0x000 148 #define REG_MMU_CFG 0x004 149 #define REG_MMU_STATUS 0x008 150 #define REG_MMU_VERSION 0x034 151 152 #define MMU_MAJ_VER(val) ((val) >> 7) 153 #define MMU_MIN_VER(val) ((val) & 0x7F) 154 #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ 155 156 #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) 157 158 /* v1.x - v3.x registers */ 159 #define REG_MMU_FLUSH 0x00C 160 #define REG_MMU_FLUSH_ENTRY 0x010 161 #define REG_PT_BASE_ADDR 0x014 162 #define REG_INT_STATUS 0x018 163 #define REG_INT_CLEAR 0x01C 164 165 #define REG_PAGE_FAULT_ADDR 0x024 166 #define REG_AW_FAULT_ADDR 0x028 167 #define REG_AR_FAULT_ADDR 0x02C 168 #define REG_DEFAULT_SLAVE_ADDR 0x030 169 170 /* v5.x registers */ 171 #define REG_V5_PT_BASE_PFN 0x00C 172 #define REG_V5_MMU_FLUSH_ALL 0x010 173 #define REG_V5_MMU_FLUSH_ENTRY 0x014 174 #define REG_V5_MMU_FLUSH_RANGE 0x018 175 #define REG_V5_MMU_FLUSH_START 0x020 176 #define REG_V5_MMU_FLUSH_END 0x024 177 #define REG_V5_INT_STATUS 0x060 178 #define REG_V5_INT_CLEAR 0x064 179 #define REG_V5_FAULT_AR_VA 0x070 180 #define REG_V5_FAULT_AW_VA 0x080 181 182 #define has_sysmmu(dev) (dev->archdata.iommu != NULL) 183 184 static struct device *dma_dev; 185 static struct kmem_cache *lv2table_kmem_cache; 186 static sysmmu_pte_t *zero_lv2_table; 187 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) 188 189 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) 190 { 191 return pgtable + lv1ent_offset(iova); 192 } 193 194 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) 195 { 196 return (sysmmu_pte_t *)phys_to_virt( 197 lv2table_base(sent)) + lv2ent_offset(iova); 198 } 199 200 /* 201 * IOMMU fault information register 202 */ 203 struct sysmmu_fault_info { 204 unsigned int bit; /* bit number in STATUS register */ 205 unsigned short addr_reg; /* register to read VA fault address */ 206 const char *name; /* human readable fault name */ 207 unsigned int type; /* fault type for report_iommu_fault */ 208 }; 209 210 static const struct sysmmu_fault_info sysmmu_faults[] = { 211 { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ }, 212 { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ }, 213 { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, 214 { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ }, 215 { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, 216 { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, 217 { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, 218 { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, 219 }; 220 221 static const struct sysmmu_fault_info sysmmu_v5_faults[] = { 222 { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ }, 223 { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ }, 224 { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ }, 225 { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, 226 { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, 227 { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE }, 228 { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE }, 229 { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, 230 { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, 231 { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, 232 }; 233 234 /* 235 * This structure is attached to dev.archdata.iommu of the master device 236 * on device add, contains a list of SYSMMU controllers defined by device tree, 237 * which are bound to given master device. It is usually referenced by 'owner' 238 * pointer. 239 */ 240 struct exynos_iommu_owner { 241 struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ 242 struct iommu_domain *domain; /* domain this device is attached */ 243 struct mutex rpm_lock; /* for runtime pm of all sysmmus */ 244 }; 245 246 /* 247 * This structure exynos specific generalization of struct iommu_domain. 248 * It contains list of SYSMMU controllers from all master devices, which has 249 * been attached to this domain and page tables of IO address space defined by 250 * it. It is usually referenced by 'domain' pointer. 251 */ 252 struct exynos_iommu_domain { 253 struct list_head clients; /* list of sysmmu_drvdata.domain_node */ 254 sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ 255 short *lv2entcnt; /* free lv2 entry counter for each section */ 256 spinlock_t lock; /* lock for modyfying list of clients */ 257 spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ 258 struct iommu_domain domain; /* generic domain data structure */ 259 }; 260 261 /* 262 * This structure hold all data of a single SYSMMU controller, this includes 263 * hw resources like registers and clocks, pointers and list nodes to connect 264 * it to all other structures, internal state and parameters read from device 265 * tree. It is usually referenced by 'data' pointer. 266 */ 267 struct sysmmu_drvdata { 268 struct device *sysmmu; /* SYSMMU controller device */ 269 struct device *master; /* master device (owner) */ 270 void __iomem *sfrbase; /* our registers */ 271 struct clk *clk; /* SYSMMU's clock */ 272 struct clk *aclk; /* SYSMMU's aclk clock */ 273 struct clk *pclk; /* SYSMMU's pclk clock */ 274 struct clk *clk_master; /* master's device clock */ 275 spinlock_t lock; /* lock for modyfying state */ 276 bool active; /* current status */ 277 struct exynos_iommu_domain *domain; /* domain we belong to */ 278 struct list_head domain_node; /* node for domain clients list */ 279 struct list_head owner_node; /* node for owner controllers list */ 280 phys_addr_t pgtable; /* assigned page table structure */ 281 unsigned int version; /* our version */ 282 283 struct iommu_device iommu; /* IOMMU core handle */ 284 }; 285 286 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) 287 { 288 return container_of(dom, struct exynos_iommu_domain, domain); 289 } 290 291 static void sysmmu_unblock(struct sysmmu_drvdata *data) 292 { 293 writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); 294 } 295 296 static bool sysmmu_block(struct sysmmu_drvdata *data) 297 { 298 int i = 120; 299 300 writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); 301 while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1)) 302 --i; 303 304 if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) { 305 sysmmu_unblock(data); 306 return false; 307 } 308 309 return true; 310 } 311 312 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) 313 { 314 if (MMU_MAJ_VER(data->version) < 5) 315 writel(0x1, data->sfrbase + REG_MMU_FLUSH); 316 else 317 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); 318 } 319 320 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, 321 sysmmu_iova_t iova, unsigned int num_inv) 322 { 323 unsigned int i; 324 325 if (MMU_MAJ_VER(data->version) < 5) { 326 for (i = 0; i < num_inv; i++) { 327 writel((iova & SPAGE_MASK) | 1, 328 data->sfrbase + REG_MMU_FLUSH_ENTRY); 329 iova += SPAGE_SIZE; 330 } 331 } else { 332 if (num_inv == 1) { 333 writel((iova & SPAGE_MASK) | 1, 334 data->sfrbase + REG_V5_MMU_FLUSH_ENTRY); 335 } else { 336 writel((iova & SPAGE_MASK), 337 data->sfrbase + REG_V5_MMU_FLUSH_START); 338 writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, 339 data->sfrbase + REG_V5_MMU_FLUSH_END); 340 writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE); 341 } 342 } 343 } 344 345 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) 346 { 347 if (MMU_MAJ_VER(data->version) < 5) 348 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); 349 else 350 writel(pgd >> PAGE_SHIFT, 351 data->sfrbase + REG_V5_PT_BASE_PFN); 352 353 __sysmmu_tlb_invalidate(data); 354 } 355 356 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data) 357 { 358 BUG_ON(clk_prepare_enable(data->clk_master)); 359 BUG_ON(clk_prepare_enable(data->clk)); 360 BUG_ON(clk_prepare_enable(data->pclk)); 361 BUG_ON(clk_prepare_enable(data->aclk)); 362 } 363 364 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) 365 { 366 clk_disable_unprepare(data->aclk); 367 clk_disable_unprepare(data->pclk); 368 clk_disable_unprepare(data->clk); 369 clk_disable_unprepare(data->clk_master); 370 } 371 372 static void __sysmmu_get_version(struct sysmmu_drvdata *data) 373 { 374 u32 ver; 375 376 __sysmmu_enable_clocks(data); 377 378 ver = readl(data->sfrbase + REG_MMU_VERSION); 379 380 /* controllers on some SoCs don't report proper version */ 381 if (ver == 0x80000001u) 382 data->version = MAKE_MMU_VER(1, 0); 383 else 384 data->version = MMU_RAW_VER(ver); 385 386 dev_dbg(data->sysmmu, "hardware version: %d.%d\n", 387 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); 388 389 __sysmmu_disable_clocks(data); 390 } 391 392 static void show_fault_information(struct sysmmu_drvdata *data, 393 const struct sysmmu_fault_info *finfo, 394 sysmmu_iova_t fault_addr) 395 { 396 sysmmu_pte_t *ent; 397 398 dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n", 399 dev_name(data->master), finfo->name, fault_addr); 400 dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable); 401 ent = section_entry(phys_to_virt(data->pgtable), fault_addr); 402 dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent); 403 if (lv1ent_page(ent)) { 404 ent = page_entry(ent, fault_addr); 405 dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent); 406 } 407 } 408 409 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) 410 { 411 /* SYSMMU is in blocked state when interrupt occurred. */ 412 struct sysmmu_drvdata *data = dev_id; 413 const struct sysmmu_fault_info *finfo; 414 unsigned int i, n, itype; 415 sysmmu_iova_t fault_addr = -1; 416 unsigned short reg_status, reg_clear; 417 int ret = -ENOSYS; 418 419 WARN_ON(!data->active); 420 421 if (MMU_MAJ_VER(data->version) < 5) { 422 reg_status = REG_INT_STATUS; 423 reg_clear = REG_INT_CLEAR; 424 finfo = sysmmu_faults; 425 n = ARRAY_SIZE(sysmmu_faults); 426 } else { 427 reg_status = REG_V5_INT_STATUS; 428 reg_clear = REG_V5_INT_CLEAR; 429 finfo = sysmmu_v5_faults; 430 n = ARRAY_SIZE(sysmmu_v5_faults); 431 } 432 433 spin_lock(&data->lock); 434 435 clk_enable(data->clk_master); 436 437 itype = __ffs(readl(data->sfrbase + reg_status)); 438 for (i = 0; i < n; i++, finfo++) 439 if (finfo->bit == itype) 440 break; 441 /* unknown/unsupported fault */ 442 BUG_ON(i == n); 443 444 /* print debug message */ 445 fault_addr = readl(data->sfrbase + finfo->addr_reg); 446 show_fault_information(data, finfo, fault_addr); 447 448 if (data->domain) 449 ret = report_iommu_fault(&data->domain->domain, 450 data->master, fault_addr, finfo->type); 451 /* fault is not recovered by fault handler */ 452 BUG_ON(ret != 0); 453 454 writel(1 << itype, data->sfrbase + reg_clear); 455 456 sysmmu_unblock(data); 457 458 clk_disable(data->clk_master); 459 460 spin_unlock(&data->lock); 461 462 return IRQ_HANDLED; 463 } 464 465 static void __sysmmu_disable(struct sysmmu_drvdata *data) 466 { 467 unsigned long flags; 468 469 clk_enable(data->clk_master); 470 471 spin_lock_irqsave(&data->lock, flags); 472 writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); 473 writel(0, data->sfrbase + REG_MMU_CFG); 474 data->active = false; 475 spin_unlock_irqrestore(&data->lock, flags); 476 477 __sysmmu_disable_clocks(data); 478 } 479 480 static void __sysmmu_init_config(struct sysmmu_drvdata *data) 481 { 482 unsigned int cfg; 483 484 if (data->version <= MAKE_MMU_VER(3, 1)) 485 cfg = CFG_LRU | CFG_QOS(15); 486 else if (data->version <= MAKE_MMU_VER(3, 2)) 487 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL; 488 else 489 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN; 490 491 cfg |= CFG_EAP; /* enable access protection bits check */ 492 493 writel(cfg, data->sfrbase + REG_MMU_CFG); 494 } 495 496 static void __sysmmu_enable(struct sysmmu_drvdata *data) 497 { 498 unsigned long flags; 499 500 __sysmmu_enable_clocks(data); 501 502 spin_lock_irqsave(&data->lock, flags); 503 writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); 504 __sysmmu_init_config(data); 505 __sysmmu_set_ptbase(data, data->pgtable); 506 writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); 507 data->active = true; 508 spin_unlock_irqrestore(&data->lock, flags); 509 510 /* 511 * SYSMMU driver keeps master's clock enabled only for the short 512 * time, while accessing the registers. For performing address 513 * translation during DMA transaction it relies on the client 514 * driver to enable it. 515 */ 516 clk_disable(data->clk_master); 517 } 518 519 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, 520 sysmmu_iova_t iova) 521 { 522 unsigned long flags; 523 524 spin_lock_irqsave(&data->lock, flags); 525 if (data->active && data->version >= MAKE_MMU_VER(3, 3)) { 526 clk_enable(data->clk_master); 527 if (sysmmu_block(data)) { 528 if (data->version >= MAKE_MMU_VER(5, 0)) 529 __sysmmu_tlb_invalidate(data); 530 else 531 __sysmmu_tlb_invalidate_entry(data, iova, 1); 532 sysmmu_unblock(data); 533 } 534 clk_disable(data->clk_master); 535 } 536 spin_unlock_irqrestore(&data->lock, flags); 537 } 538 539 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, 540 sysmmu_iova_t iova, size_t size) 541 { 542 unsigned long flags; 543 544 spin_lock_irqsave(&data->lock, flags); 545 if (data->active) { 546 unsigned int num_inv = 1; 547 548 clk_enable(data->clk_master); 549 550 /* 551 * L2TLB invalidation required 552 * 4KB page: 1 invalidation 553 * 64KB page: 16 invalidations 554 * 1MB page: 64 invalidations 555 * because it is set-associative TLB 556 * with 8-way and 64 sets. 557 * 1MB page can be cached in one of all sets. 558 * 64KB page can be one of 16 consecutive sets. 559 */ 560 if (MMU_MAJ_VER(data->version) == 2) 561 num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); 562 563 if (sysmmu_block(data)) { 564 __sysmmu_tlb_invalidate_entry(data, iova, num_inv); 565 sysmmu_unblock(data); 566 } 567 clk_disable(data->clk_master); 568 } 569 spin_unlock_irqrestore(&data->lock, flags); 570 } 571 572 static struct iommu_ops exynos_iommu_ops; 573 574 static int __init exynos_sysmmu_probe(struct platform_device *pdev) 575 { 576 int irq, ret; 577 struct device *dev = &pdev->dev; 578 struct sysmmu_drvdata *data; 579 struct resource *res; 580 581 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 582 if (!data) 583 return -ENOMEM; 584 585 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 586 data->sfrbase = devm_ioremap_resource(dev, res); 587 if (IS_ERR(data->sfrbase)) 588 return PTR_ERR(data->sfrbase); 589 590 irq = platform_get_irq(pdev, 0); 591 if (irq <= 0) { 592 dev_err(dev, "Unable to find IRQ resource\n"); 593 return irq; 594 } 595 596 ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, 597 dev_name(dev), data); 598 if (ret) { 599 dev_err(dev, "Unabled to register handler of irq %d\n", irq); 600 return ret; 601 } 602 603 data->clk = devm_clk_get(dev, "sysmmu"); 604 if (PTR_ERR(data->clk) == -ENOENT) 605 data->clk = NULL; 606 else if (IS_ERR(data->clk)) 607 return PTR_ERR(data->clk); 608 609 data->aclk = devm_clk_get(dev, "aclk"); 610 if (PTR_ERR(data->aclk) == -ENOENT) 611 data->aclk = NULL; 612 else if (IS_ERR(data->aclk)) 613 return PTR_ERR(data->aclk); 614 615 data->pclk = devm_clk_get(dev, "pclk"); 616 if (PTR_ERR(data->pclk) == -ENOENT) 617 data->pclk = NULL; 618 else if (IS_ERR(data->pclk)) 619 return PTR_ERR(data->pclk); 620 621 if (!data->clk && (!data->aclk || !data->pclk)) { 622 dev_err(dev, "Failed to get device clock(s)!\n"); 623 return -ENOSYS; 624 } 625 626 data->clk_master = devm_clk_get(dev, "master"); 627 if (PTR_ERR(data->clk_master) == -ENOENT) 628 data->clk_master = NULL; 629 else if (IS_ERR(data->clk_master)) 630 return PTR_ERR(data->clk_master); 631 632 data->sysmmu = dev; 633 spin_lock_init(&data->lock); 634 635 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 636 dev_name(data->sysmmu)); 637 if (ret) 638 return ret; 639 640 iommu_device_set_ops(&data->iommu, &exynos_iommu_ops); 641 iommu_device_set_fwnode(&data->iommu, &dev->of_node->fwnode); 642 643 ret = iommu_device_register(&data->iommu); 644 if (ret) 645 return ret; 646 647 platform_set_drvdata(pdev, data); 648 649 __sysmmu_get_version(data); 650 if (PG_ENT_SHIFT < 0) { 651 if (MMU_MAJ_VER(data->version) < 5) { 652 PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; 653 LV1_PROT = SYSMMU_LV1_PROT; 654 LV2_PROT = SYSMMU_LV2_PROT; 655 } else { 656 PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT; 657 LV1_PROT = SYSMMU_V5_LV1_PROT; 658 LV2_PROT = SYSMMU_V5_LV2_PROT; 659 } 660 } 661 662 pm_runtime_enable(dev); 663 664 return 0; 665 } 666 667 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) 668 { 669 struct sysmmu_drvdata *data = dev_get_drvdata(dev); 670 struct device *master = data->master; 671 672 if (master) { 673 struct exynos_iommu_owner *owner = master->archdata.iommu; 674 675 mutex_lock(&owner->rpm_lock); 676 if (data->domain) { 677 dev_dbg(data->sysmmu, "saving state\n"); 678 __sysmmu_disable(data); 679 } 680 mutex_unlock(&owner->rpm_lock); 681 } 682 return 0; 683 } 684 685 static int __maybe_unused exynos_sysmmu_resume(struct device *dev) 686 { 687 struct sysmmu_drvdata *data = dev_get_drvdata(dev); 688 struct device *master = data->master; 689 690 if (master) { 691 struct exynos_iommu_owner *owner = master->archdata.iommu; 692 693 mutex_lock(&owner->rpm_lock); 694 if (data->domain) { 695 dev_dbg(data->sysmmu, "restoring state\n"); 696 __sysmmu_enable(data); 697 } 698 mutex_unlock(&owner->rpm_lock); 699 } 700 return 0; 701 } 702 703 static const struct dev_pm_ops sysmmu_pm_ops = { 704 SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL) 705 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 706 pm_runtime_force_resume) 707 }; 708 709 static const struct of_device_id sysmmu_of_match[] __initconst = { 710 { .compatible = "samsung,exynos-sysmmu", }, 711 { }, 712 }; 713 714 static struct platform_driver exynos_sysmmu_driver __refdata = { 715 .probe = exynos_sysmmu_probe, 716 .driver = { 717 .name = "exynos-sysmmu", 718 .of_match_table = sysmmu_of_match, 719 .pm = &sysmmu_pm_ops, 720 .suppress_bind_attrs = true, 721 } 722 }; 723 724 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) 725 { 726 dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), 727 DMA_TO_DEVICE); 728 *ent = cpu_to_le32(val); 729 dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), 730 DMA_TO_DEVICE); 731 } 732 733 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) 734 { 735 struct exynos_iommu_domain *domain; 736 dma_addr_t handle; 737 int i; 738 739 /* Check if correct PTE offsets are initialized */ 740 BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev); 741 742 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 743 if (!domain) 744 return NULL; 745 746 if (type == IOMMU_DOMAIN_DMA) { 747 if (iommu_get_dma_cookie(&domain->domain) != 0) 748 goto err_pgtable; 749 } else if (type != IOMMU_DOMAIN_UNMANAGED) { 750 goto err_pgtable; 751 } 752 753 domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); 754 if (!domain->pgtable) 755 goto err_dma_cookie; 756 757 domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); 758 if (!domain->lv2entcnt) 759 goto err_counter; 760 761 /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ 762 for (i = 0; i < NUM_LV1ENTRIES; i++) 763 domain->pgtable[i] = ZERO_LV2LINK; 764 765 handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, 766 DMA_TO_DEVICE); 767 /* For mapping page table entries we rely on dma == phys */ 768 BUG_ON(handle != virt_to_phys(domain->pgtable)); 769 if (dma_mapping_error(dma_dev, handle)) 770 goto err_lv2ent; 771 772 spin_lock_init(&domain->lock); 773 spin_lock_init(&domain->pgtablelock); 774 INIT_LIST_HEAD(&domain->clients); 775 776 domain->domain.geometry.aperture_start = 0; 777 domain->domain.geometry.aperture_end = ~0UL; 778 domain->domain.geometry.force_aperture = true; 779 780 return &domain->domain; 781 782 err_lv2ent: 783 free_pages((unsigned long)domain->lv2entcnt, 1); 784 err_counter: 785 free_pages((unsigned long)domain->pgtable, 2); 786 err_dma_cookie: 787 if (type == IOMMU_DOMAIN_DMA) 788 iommu_put_dma_cookie(&domain->domain); 789 err_pgtable: 790 kfree(domain); 791 return NULL; 792 } 793 794 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) 795 { 796 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 797 struct sysmmu_drvdata *data, *next; 798 unsigned long flags; 799 int i; 800 801 WARN_ON(!list_empty(&domain->clients)); 802 803 spin_lock_irqsave(&domain->lock, flags); 804 805 list_for_each_entry_safe(data, next, &domain->clients, domain_node) { 806 spin_lock(&data->lock); 807 __sysmmu_disable(data); 808 data->pgtable = 0; 809 data->domain = NULL; 810 list_del_init(&data->domain_node); 811 spin_unlock(&data->lock); 812 } 813 814 spin_unlock_irqrestore(&domain->lock, flags); 815 816 if (iommu_domain->type == IOMMU_DOMAIN_DMA) 817 iommu_put_dma_cookie(iommu_domain); 818 819 dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, 820 DMA_TO_DEVICE); 821 822 for (i = 0; i < NUM_LV1ENTRIES; i++) 823 if (lv1ent_page(domain->pgtable + i)) { 824 phys_addr_t base = lv2table_base(domain->pgtable + i); 825 826 dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, 827 DMA_TO_DEVICE); 828 kmem_cache_free(lv2table_kmem_cache, 829 phys_to_virt(base)); 830 } 831 832 free_pages((unsigned long)domain->pgtable, 2); 833 free_pages((unsigned long)domain->lv2entcnt, 1); 834 kfree(domain); 835 } 836 837 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, 838 struct device *dev) 839 { 840 struct exynos_iommu_owner *owner = dev->archdata.iommu; 841 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 842 phys_addr_t pagetable = virt_to_phys(domain->pgtable); 843 struct sysmmu_drvdata *data, *next; 844 unsigned long flags; 845 846 if (!has_sysmmu(dev) || owner->domain != iommu_domain) 847 return; 848 849 mutex_lock(&owner->rpm_lock); 850 851 list_for_each_entry(data, &owner->controllers, owner_node) { 852 pm_runtime_get_noresume(data->sysmmu); 853 if (pm_runtime_active(data->sysmmu)) 854 __sysmmu_disable(data); 855 pm_runtime_put(data->sysmmu); 856 } 857 858 spin_lock_irqsave(&domain->lock, flags); 859 list_for_each_entry_safe(data, next, &domain->clients, domain_node) { 860 spin_lock(&data->lock); 861 data->pgtable = 0; 862 data->domain = NULL; 863 list_del_init(&data->domain_node); 864 spin_unlock(&data->lock); 865 } 866 owner->domain = NULL; 867 spin_unlock_irqrestore(&domain->lock, flags); 868 869 mutex_unlock(&owner->rpm_lock); 870 871 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__, 872 &pagetable); 873 } 874 875 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, 876 struct device *dev) 877 { 878 struct exynos_iommu_owner *owner = dev->archdata.iommu; 879 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 880 struct sysmmu_drvdata *data; 881 phys_addr_t pagetable = virt_to_phys(domain->pgtable); 882 unsigned long flags; 883 884 if (!has_sysmmu(dev)) 885 return -ENODEV; 886 887 if (owner->domain) 888 exynos_iommu_detach_device(owner->domain, dev); 889 890 mutex_lock(&owner->rpm_lock); 891 892 spin_lock_irqsave(&domain->lock, flags); 893 list_for_each_entry(data, &owner->controllers, owner_node) { 894 spin_lock(&data->lock); 895 data->pgtable = pagetable; 896 data->domain = domain; 897 list_add_tail(&data->domain_node, &domain->clients); 898 spin_unlock(&data->lock); 899 } 900 owner->domain = iommu_domain; 901 spin_unlock_irqrestore(&domain->lock, flags); 902 903 list_for_each_entry(data, &owner->controllers, owner_node) { 904 pm_runtime_get_noresume(data->sysmmu); 905 if (pm_runtime_active(data->sysmmu)) 906 __sysmmu_enable(data); 907 pm_runtime_put(data->sysmmu); 908 } 909 910 mutex_unlock(&owner->rpm_lock); 911 912 dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__, 913 &pagetable); 914 915 return 0; 916 } 917 918 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, 919 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) 920 { 921 if (lv1ent_section(sent)) { 922 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); 923 return ERR_PTR(-EADDRINUSE); 924 } 925 926 if (lv1ent_fault(sent)) { 927 dma_addr_t handle; 928 sysmmu_pte_t *pent; 929 bool need_flush_flpd_cache = lv1ent_zero(sent); 930 931 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); 932 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1)); 933 if (!pent) 934 return ERR_PTR(-ENOMEM); 935 936 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); 937 kmemleak_ignore(pent); 938 *pgcounter = NUM_LV2ENTRIES; 939 handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE, 940 DMA_TO_DEVICE); 941 if (dma_mapping_error(dma_dev, handle)) { 942 kmem_cache_free(lv2table_kmem_cache, pent); 943 return ERR_PTR(-EADDRINUSE); 944 } 945 946 /* 947 * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, 948 * FLPD cache may cache the address of zero_l2_table. This 949 * function replaces the zero_l2_table with new L2 page table 950 * to write valid mappings. 951 * Accessing the valid area may cause page fault since FLPD 952 * cache may still cache zero_l2_table for the valid area 953 * instead of new L2 page table that has the mapping 954 * information of the valid area. 955 * Thus any replacement of zero_l2_table with other valid L2 956 * page table must involve FLPD cache invalidation for System 957 * MMU v3.3. 958 * FLPD cache invalidation is performed with TLB invalidation 959 * by VPN without blocking. It is safe to invalidate TLB without 960 * blocking because the target address of TLB invalidation is 961 * not currently mapped. 962 */ 963 if (need_flush_flpd_cache) { 964 struct sysmmu_drvdata *data; 965 966 spin_lock(&domain->lock); 967 list_for_each_entry(data, &domain->clients, domain_node) 968 sysmmu_tlb_invalidate_flpdcache(data, iova); 969 spin_unlock(&domain->lock); 970 } 971 } 972 973 return page_entry(sent, iova); 974 } 975 976 static int lv1set_section(struct exynos_iommu_domain *domain, 977 sysmmu_pte_t *sent, sysmmu_iova_t iova, 978 phys_addr_t paddr, int prot, short *pgcnt) 979 { 980 if (lv1ent_section(sent)) { 981 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", 982 iova); 983 return -EADDRINUSE; 984 } 985 986 if (lv1ent_page(sent)) { 987 if (*pgcnt != NUM_LV2ENTRIES) { 988 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", 989 iova); 990 return -EADDRINUSE; 991 } 992 993 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); 994 *pgcnt = 0; 995 } 996 997 update_pte(sent, mk_lv1ent_sect(paddr, prot)); 998 999 spin_lock(&domain->lock); 1000 if (lv1ent_page_zero(sent)) { 1001 struct sysmmu_drvdata *data; 1002 /* 1003 * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD 1004 * entry by speculative prefetch of SLPD which has no mapping. 1005 */ 1006 list_for_each_entry(data, &domain->clients, domain_node) 1007 sysmmu_tlb_invalidate_flpdcache(data, iova); 1008 } 1009 spin_unlock(&domain->lock); 1010 1011 return 0; 1012 } 1013 1014 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, 1015 int prot, short *pgcnt) 1016 { 1017 if (size == SPAGE_SIZE) { 1018 if (WARN_ON(!lv2ent_fault(pent))) 1019 return -EADDRINUSE; 1020 1021 update_pte(pent, mk_lv2ent_spage(paddr, prot)); 1022 *pgcnt -= 1; 1023 } else { /* size == LPAGE_SIZE */ 1024 int i; 1025 dma_addr_t pent_base = virt_to_phys(pent); 1026 1027 dma_sync_single_for_cpu(dma_dev, pent_base, 1028 sizeof(*pent) * SPAGES_PER_LPAGE, 1029 DMA_TO_DEVICE); 1030 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { 1031 if (WARN_ON(!lv2ent_fault(pent))) { 1032 if (i > 0) 1033 memset(pent - i, 0, sizeof(*pent) * i); 1034 return -EADDRINUSE; 1035 } 1036 1037 *pent = mk_lv2ent_lpage(paddr, prot); 1038 } 1039 dma_sync_single_for_device(dma_dev, pent_base, 1040 sizeof(*pent) * SPAGES_PER_LPAGE, 1041 DMA_TO_DEVICE); 1042 *pgcnt -= SPAGES_PER_LPAGE; 1043 } 1044 1045 return 0; 1046 } 1047 1048 /* 1049 * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: 1050 * 1051 * System MMU v3.x has advanced logic to improve address translation 1052 * performance with caching more page table entries by a page table walk. 1053 * However, the logic has a bug that while caching faulty page table entries, 1054 * System MMU reports page fault if the cached fault entry is hit even though 1055 * the fault entry is updated to a valid entry after the entry is cached. 1056 * To prevent caching faulty page table entries which may be updated to valid 1057 * entries later, the virtual memory manager should care about the workaround 1058 * for the problem. The following describes the workaround. 1059 * 1060 * Any two consecutive I/O virtual address regions must have a hole of 128KiB 1061 * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). 1062 * 1063 * Precisely, any start address of I/O virtual region must be aligned with 1064 * the following sizes for System MMU v3.1 and v3.2. 1065 * System MMU v3.1: 128KiB 1066 * System MMU v3.2: 256KiB 1067 * 1068 * Because System MMU v3.3 caches page table entries more aggressively, it needs 1069 * more workarounds. 1070 * - Any two consecutive I/O virtual regions must have a hole of size larger 1071 * than or equal to 128KiB. 1072 * - Start address of an I/O virtual region must be aligned by 128KiB. 1073 */ 1074 static int exynos_iommu_map(struct iommu_domain *iommu_domain, 1075 unsigned long l_iova, phys_addr_t paddr, size_t size, 1076 int prot) 1077 { 1078 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 1079 sysmmu_pte_t *entry; 1080 sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; 1081 unsigned long flags; 1082 int ret = -ENOMEM; 1083 1084 BUG_ON(domain->pgtable == NULL); 1085 prot &= SYSMMU_SUPPORTED_PROT_BITS; 1086 1087 spin_lock_irqsave(&domain->pgtablelock, flags); 1088 1089 entry = section_entry(domain->pgtable, iova); 1090 1091 if (size == SECT_SIZE) { 1092 ret = lv1set_section(domain, entry, iova, paddr, prot, 1093 &domain->lv2entcnt[lv1ent_offset(iova)]); 1094 } else { 1095 sysmmu_pte_t *pent; 1096 1097 pent = alloc_lv2entry(domain, entry, iova, 1098 &domain->lv2entcnt[lv1ent_offset(iova)]); 1099 1100 if (IS_ERR(pent)) 1101 ret = PTR_ERR(pent); 1102 else 1103 ret = lv2set_page(pent, paddr, size, prot, 1104 &domain->lv2entcnt[lv1ent_offset(iova)]); 1105 } 1106 1107 if (ret) 1108 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", 1109 __func__, ret, size, iova); 1110 1111 spin_unlock_irqrestore(&domain->pgtablelock, flags); 1112 1113 return ret; 1114 } 1115 1116 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, 1117 sysmmu_iova_t iova, size_t size) 1118 { 1119 struct sysmmu_drvdata *data; 1120 unsigned long flags; 1121 1122 spin_lock_irqsave(&domain->lock, flags); 1123 1124 list_for_each_entry(data, &domain->clients, domain_node) 1125 sysmmu_tlb_invalidate_entry(data, iova, size); 1126 1127 spin_unlock_irqrestore(&domain->lock, flags); 1128 } 1129 1130 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, 1131 unsigned long l_iova, size_t size) 1132 { 1133 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 1134 sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; 1135 sysmmu_pte_t *ent; 1136 size_t err_pgsize; 1137 unsigned long flags; 1138 1139 BUG_ON(domain->pgtable == NULL); 1140 1141 spin_lock_irqsave(&domain->pgtablelock, flags); 1142 1143 ent = section_entry(domain->pgtable, iova); 1144 1145 if (lv1ent_section(ent)) { 1146 if (WARN_ON(size < SECT_SIZE)) { 1147 err_pgsize = SECT_SIZE; 1148 goto err; 1149 } 1150 1151 /* workaround for h/w bug in System MMU v3.3 */ 1152 update_pte(ent, ZERO_LV2LINK); 1153 size = SECT_SIZE; 1154 goto done; 1155 } 1156 1157 if (unlikely(lv1ent_fault(ent))) { 1158 if (size > SECT_SIZE) 1159 size = SECT_SIZE; 1160 goto done; 1161 } 1162 1163 /* lv1ent_page(sent) == true here */ 1164 1165 ent = page_entry(ent, iova); 1166 1167 if (unlikely(lv2ent_fault(ent))) { 1168 size = SPAGE_SIZE; 1169 goto done; 1170 } 1171 1172 if (lv2ent_small(ent)) { 1173 update_pte(ent, 0); 1174 size = SPAGE_SIZE; 1175 domain->lv2entcnt[lv1ent_offset(iova)] += 1; 1176 goto done; 1177 } 1178 1179 /* lv1ent_large(ent) == true here */ 1180 if (WARN_ON(size < LPAGE_SIZE)) { 1181 err_pgsize = LPAGE_SIZE; 1182 goto err; 1183 } 1184 1185 dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), 1186 sizeof(*ent) * SPAGES_PER_LPAGE, 1187 DMA_TO_DEVICE); 1188 memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); 1189 dma_sync_single_for_device(dma_dev, virt_to_phys(ent), 1190 sizeof(*ent) * SPAGES_PER_LPAGE, 1191 DMA_TO_DEVICE); 1192 size = LPAGE_SIZE; 1193 domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; 1194 done: 1195 spin_unlock_irqrestore(&domain->pgtablelock, flags); 1196 1197 exynos_iommu_tlb_invalidate_entry(domain, iova, size); 1198 1199 return size; 1200 err: 1201 spin_unlock_irqrestore(&domain->pgtablelock, flags); 1202 1203 pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", 1204 __func__, size, iova, err_pgsize); 1205 1206 return 0; 1207 } 1208 1209 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, 1210 dma_addr_t iova) 1211 { 1212 struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); 1213 sysmmu_pte_t *entry; 1214 unsigned long flags; 1215 phys_addr_t phys = 0; 1216 1217 spin_lock_irqsave(&domain->pgtablelock, flags); 1218 1219 entry = section_entry(domain->pgtable, iova); 1220 1221 if (lv1ent_section(entry)) { 1222 phys = section_phys(entry) + section_offs(iova); 1223 } else if (lv1ent_page(entry)) { 1224 entry = page_entry(entry, iova); 1225 1226 if (lv2ent_large(entry)) 1227 phys = lpage_phys(entry) + lpage_offs(iova); 1228 else if (lv2ent_small(entry)) 1229 phys = spage_phys(entry) + spage_offs(iova); 1230 } 1231 1232 spin_unlock_irqrestore(&domain->pgtablelock, flags); 1233 1234 return phys; 1235 } 1236 1237 static struct iommu_group *get_device_iommu_group(struct device *dev) 1238 { 1239 struct iommu_group *group; 1240 1241 group = iommu_group_get(dev); 1242 if (!group) 1243 group = iommu_group_alloc(); 1244 1245 return group; 1246 } 1247 1248 static int exynos_iommu_add_device(struct device *dev) 1249 { 1250 struct iommu_group *group; 1251 1252 if (!has_sysmmu(dev)) 1253 return -ENODEV; 1254 1255 group = iommu_group_get_for_dev(dev); 1256 1257 if (IS_ERR(group)) 1258 return PTR_ERR(group); 1259 1260 iommu_group_put(group); 1261 1262 return 0; 1263 } 1264 1265 static void exynos_iommu_remove_device(struct device *dev) 1266 { 1267 struct exynos_iommu_owner *owner = dev->archdata.iommu; 1268 1269 if (!has_sysmmu(dev)) 1270 return; 1271 1272 if (owner->domain) { 1273 struct iommu_group *group = iommu_group_get(dev); 1274 1275 if (group) { 1276 WARN_ON(owner->domain != 1277 iommu_group_default_domain(group)); 1278 exynos_iommu_detach_device(owner->domain, dev); 1279 iommu_group_put(group); 1280 } 1281 } 1282 iommu_group_remove_device(dev); 1283 } 1284 1285 static int exynos_iommu_of_xlate(struct device *dev, 1286 struct of_phandle_args *spec) 1287 { 1288 struct exynos_iommu_owner *owner = dev->archdata.iommu; 1289 struct platform_device *sysmmu = of_find_device_by_node(spec->np); 1290 struct sysmmu_drvdata *data, *entry; 1291 1292 if (!sysmmu) 1293 return -ENODEV; 1294 1295 data = platform_get_drvdata(sysmmu); 1296 if (!data) 1297 return -ENODEV; 1298 1299 if (!owner) { 1300 owner = kzalloc(sizeof(*owner), GFP_KERNEL); 1301 if (!owner) 1302 return -ENOMEM; 1303 1304 INIT_LIST_HEAD(&owner->controllers); 1305 mutex_init(&owner->rpm_lock); 1306 dev->archdata.iommu = owner; 1307 } 1308 1309 list_for_each_entry(entry, &owner->controllers, owner_node) 1310 if (entry == data) 1311 return 0; 1312 1313 list_add_tail(&data->owner_node, &owner->controllers); 1314 data->master = dev; 1315 1316 /* 1317 * SYSMMU will be runtime activated via device link (dependency) to its 1318 * master device, so there are no direct calls to pm_runtime_get/put 1319 * in this driver. 1320 */ 1321 device_link_add(dev, data->sysmmu, DL_FLAG_PM_RUNTIME); 1322 1323 return 0; 1324 } 1325 1326 static struct iommu_ops exynos_iommu_ops = { 1327 .domain_alloc = exynos_iommu_domain_alloc, 1328 .domain_free = exynos_iommu_domain_free, 1329 .attach_dev = exynos_iommu_attach_device, 1330 .detach_dev = exynos_iommu_detach_device, 1331 .map = exynos_iommu_map, 1332 .unmap = exynos_iommu_unmap, 1333 .map_sg = default_iommu_map_sg, 1334 .iova_to_phys = exynos_iommu_iova_to_phys, 1335 .device_group = get_device_iommu_group, 1336 .add_device = exynos_iommu_add_device, 1337 .remove_device = exynos_iommu_remove_device, 1338 .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, 1339 .of_xlate = exynos_iommu_of_xlate, 1340 }; 1341 1342 static bool init_done; 1343 1344 static int __init exynos_iommu_init(void) 1345 { 1346 int ret; 1347 1348 lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", 1349 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); 1350 if (!lv2table_kmem_cache) { 1351 pr_err("%s: Failed to create kmem cache\n", __func__); 1352 return -ENOMEM; 1353 } 1354 1355 ret = platform_driver_register(&exynos_sysmmu_driver); 1356 if (ret) { 1357 pr_err("%s: Failed to register driver\n", __func__); 1358 goto err_reg_driver; 1359 } 1360 1361 zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); 1362 if (zero_lv2_table == NULL) { 1363 pr_err("%s: Failed to allocate zero level2 page table\n", 1364 __func__); 1365 ret = -ENOMEM; 1366 goto err_zero_lv2; 1367 } 1368 1369 ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); 1370 if (ret) { 1371 pr_err("%s: Failed to register exynos-iommu driver.\n", 1372 __func__); 1373 goto err_set_iommu; 1374 } 1375 1376 init_done = true; 1377 1378 return 0; 1379 err_set_iommu: 1380 kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); 1381 err_zero_lv2: 1382 platform_driver_unregister(&exynos_sysmmu_driver); 1383 err_reg_driver: 1384 kmem_cache_destroy(lv2table_kmem_cache); 1385 return ret; 1386 } 1387 1388 static int __init exynos_iommu_of_setup(struct device_node *np) 1389 { 1390 struct platform_device *pdev; 1391 1392 if (!init_done) 1393 exynos_iommu_init(); 1394 1395 pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root); 1396 if (!pdev) 1397 return -ENODEV; 1398 1399 /* 1400 * use the first registered sysmmu device for performing 1401 * dma mapping operations on iommu page tables (cpu cache flush) 1402 */ 1403 if (!dma_dev) 1404 dma_dev = &pdev->dev; 1405 1406 return 0; 1407 } 1408 1409 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu", 1410 exynos_iommu_of_setup); 1411