1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * A fairly generic DMA-API to IOMMU-API glue layer. 4 * 5 * Copyright (C) 2014-2015 ARM Ltd. 6 * 7 * based in part on arch/arm/mm/dma-mapping.c: 8 * Copyright (C) 2000-2004 Russell King 9 */ 10 11 #include <linux/acpi_iort.h> 12 #include <linux/device.h> 13 #include <linux/dma-contiguous.h> 14 #include <linux/dma-iommu.h> 15 #include <linux/dma-noncoherent.h> 16 #include <linux/gfp.h> 17 #include <linux/huge_mm.h> 18 #include <linux/iommu.h> 19 #include <linux/iova.h> 20 #include <linux/irq.h> 21 #include <linux/mm.h> 22 #include <linux/pci.h> 23 #include <linux/scatterlist.h> 24 #include <linux/vmalloc.h> 25 26 struct iommu_dma_msi_page { 27 struct list_head list; 28 dma_addr_t iova; 29 phys_addr_t phys; 30 }; 31 32 enum iommu_dma_cookie_type { 33 IOMMU_DMA_IOVA_COOKIE, 34 IOMMU_DMA_MSI_COOKIE, 35 }; 36 37 struct iommu_dma_cookie { 38 enum iommu_dma_cookie_type type; 39 union { 40 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */ 41 struct iova_domain iovad; 42 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */ 43 dma_addr_t msi_iova; 44 }; 45 struct list_head msi_page_list; 46 spinlock_t msi_lock; 47 48 /* Domain for flush queue callback; NULL if flush queue not in use */ 49 struct iommu_domain *fq_domain; 50 }; 51 52 static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie) 53 { 54 if (cookie->type == IOMMU_DMA_IOVA_COOKIE) 55 return cookie->iovad.granule; 56 return PAGE_SIZE; 57 } 58 59 static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type) 60 { 61 struct iommu_dma_cookie *cookie; 62 63 cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); 64 if (cookie) { 65 spin_lock_init(&cookie->msi_lock); 66 INIT_LIST_HEAD(&cookie->msi_page_list); 67 cookie->type = type; 68 } 69 return cookie; 70 } 71 72 /** 73 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain 74 * @domain: IOMMU domain to prepare for DMA-API usage 75 * 76 * IOMMU drivers should normally call this from their domain_alloc 77 * callback when domain->type == IOMMU_DOMAIN_DMA. 78 */ 79 int iommu_get_dma_cookie(struct iommu_domain *domain) 80 { 81 if (domain->iova_cookie) 82 return -EEXIST; 83 84 domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE); 85 if (!domain->iova_cookie) 86 return -ENOMEM; 87 88 return 0; 89 } 90 EXPORT_SYMBOL(iommu_get_dma_cookie); 91 92 /** 93 * iommu_get_msi_cookie - Acquire just MSI remapping resources 94 * @domain: IOMMU domain to prepare 95 * @base: Start address of IOVA region for MSI mappings 96 * 97 * Users who manage their own IOVA allocation and do not want DMA API support, 98 * but would still like to take advantage of automatic MSI remapping, can use 99 * this to initialise their own domain appropriately. Users should reserve a 100 * contiguous IOVA region, starting at @base, large enough to accommodate the 101 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address 102 * used by the devices attached to @domain. 103 */ 104 int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) 105 { 106 struct iommu_dma_cookie *cookie; 107 108 if (domain->type != IOMMU_DOMAIN_UNMANAGED) 109 return -EINVAL; 110 111 if (domain->iova_cookie) 112 return -EEXIST; 113 114 cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE); 115 if (!cookie) 116 return -ENOMEM; 117 118 cookie->msi_iova = base; 119 domain->iova_cookie = cookie; 120 return 0; 121 } 122 EXPORT_SYMBOL(iommu_get_msi_cookie); 123 124 /** 125 * iommu_put_dma_cookie - Release a domain's DMA mapping resources 126 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or 127 * iommu_get_msi_cookie() 128 * 129 * IOMMU drivers should normally call this from their domain_free callback. 130 */ 131 void iommu_put_dma_cookie(struct iommu_domain *domain) 132 { 133 struct iommu_dma_cookie *cookie = domain->iova_cookie; 134 struct iommu_dma_msi_page *msi, *tmp; 135 136 if (!cookie) 137 return; 138 139 if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule) 140 put_iova_domain(&cookie->iovad); 141 142 list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) { 143 list_del(&msi->list); 144 kfree(msi); 145 } 146 kfree(cookie); 147 domain->iova_cookie = NULL; 148 } 149 EXPORT_SYMBOL(iommu_put_dma_cookie); 150 151 /** 152 * iommu_dma_get_resv_regions - Reserved region driver helper 153 * @dev: Device from iommu_get_resv_regions() 154 * @list: Reserved region list from iommu_get_resv_regions() 155 * 156 * IOMMU drivers can use this to implement their .get_resv_regions callback 157 * for general non-IOMMU-specific reservations. Currently, this covers GICv3 158 * ITS region reservation on ACPI based ARM platforms that may require HW MSI 159 * reservation. 160 */ 161 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) 162 { 163 164 if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) 165 iort_iommu_msi_get_resv_regions(dev, list); 166 167 } 168 EXPORT_SYMBOL(iommu_dma_get_resv_regions); 169 170 static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, 171 phys_addr_t start, phys_addr_t end) 172 { 173 struct iova_domain *iovad = &cookie->iovad; 174 struct iommu_dma_msi_page *msi_page; 175 int i, num_pages; 176 177 start -= iova_offset(iovad, start); 178 num_pages = iova_align(iovad, end - start) >> iova_shift(iovad); 179 180 msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL); 181 if (!msi_page) 182 return -ENOMEM; 183 184 for (i = 0; i < num_pages; i++) { 185 msi_page[i].phys = start; 186 msi_page[i].iova = start; 187 INIT_LIST_HEAD(&msi_page[i].list); 188 list_add(&msi_page[i].list, &cookie->msi_page_list); 189 start += iovad->granule; 190 } 191 192 return 0; 193 } 194 195 static int iova_reserve_pci_windows(struct pci_dev *dev, 196 struct iova_domain *iovad) 197 { 198 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); 199 struct resource_entry *window; 200 unsigned long lo, hi; 201 phys_addr_t start = 0, end; 202 203 resource_list_for_each_entry(window, &bridge->windows) { 204 if (resource_type(window->res) != IORESOURCE_MEM) 205 continue; 206 207 lo = iova_pfn(iovad, window->res->start - window->offset); 208 hi = iova_pfn(iovad, window->res->end - window->offset); 209 reserve_iova(iovad, lo, hi); 210 } 211 212 /* Get reserved DMA windows from host bridge */ 213 resource_list_for_each_entry(window, &bridge->dma_ranges) { 214 end = window->res->start - window->offset; 215 resv_iova: 216 if (end > start) { 217 lo = iova_pfn(iovad, start); 218 hi = iova_pfn(iovad, end); 219 reserve_iova(iovad, lo, hi); 220 } else { 221 /* dma_ranges list should be sorted */ 222 dev_err(&dev->dev, "Failed to reserve IOVA\n"); 223 return -EINVAL; 224 } 225 226 start = window->res->end - window->offset + 1; 227 /* If window is last entry */ 228 if (window->node.next == &bridge->dma_ranges && 229 end != ~(phys_addr_t)0) { 230 end = ~(phys_addr_t)0; 231 goto resv_iova; 232 } 233 } 234 235 return 0; 236 } 237 238 static int iova_reserve_iommu_regions(struct device *dev, 239 struct iommu_domain *domain) 240 { 241 struct iommu_dma_cookie *cookie = domain->iova_cookie; 242 struct iova_domain *iovad = &cookie->iovad; 243 struct iommu_resv_region *region; 244 LIST_HEAD(resv_regions); 245 int ret = 0; 246 247 if (dev_is_pci(dev)) { 248 ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad); 249 if (ret) 250 return ret; 251 } 252 253 iommu_get_resv_regions(dev, &resv_regions); 254 list_for_each_entry(region, &resv_regions, list) { 255 unsigned long lo, hi; 256 257 /* We ARE the software that manages these! */ 258 if (region->type == IOMMU_RESV_SW_MSI) 259 continue; 260 261 lo = iova_pfn(iovad, region->start); 262 hi = iova_pfn(iovad, region->start + region->length - 1); 263 reserve_iova(iovad, lo, hi); 264 265 if (region->type == IOMMU_RESV_MSI) 266 ret = cookie_init_hw_msi_region(cookie, region->start, 267 region->start + region->length); 268 if (ret) 269 break; 270 } 271 iommu_put_resv_regions(dev, &resv_regions); 272 273 return ret; 274 } 275 276 static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad) 277 { 278 struct iommu_dma_cookie *cookie; 279 struct iommu_domain *domain; 280 281 cookie = container_of(iovad, struct iommu_dma_cookie, iovad); 282 domain = cookie->fq_domain; 283 /* 284 * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE 285 * implies that ops->flush_iotlb_all must be non-NULL. 286 */ 287 domain->ops->flush_iotlb_all(domain); 288 } 289 290 /** 291 * iommu_dma_init_domain - Initialise a DMA mapping domain 292 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() 293 * @base: IOVA at which the mappable address space starts 294 * @size: Size of IOVA space 295 * @dev: Device the domain is being initialised for 296 * 297 * @base and @size should be exact multiples of IOMMU page granularity to 298 * avoid rounding surprises. If necessary, we reserve the page at address 0 299 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but 300 * any change which could make prior IOVAs invalid will fail. 301 */ 302 static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, 303 u64 size, struct device *dev) 304 { 305 struct iommu_dma_cookie *cookie = domain->iova_cookie; 306 struct iova_domain *iovad = &cookie->iovad; 307 unsigned long order, base_pfn; 308 int attr; 309 310 if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) 311 return -EINVAL; 312 313 /* Use the smallest supported page size for IOVA granularity */ 314 order = __ffs(domain->pgsize_bitmap); 315 base_pfn = max_t(unsigned long, 1, base >> order); 316 317 /* Check the domain allows at least some access to the device... */ 318 if (domain->geometry.force_aperture) { 319 if (base > domain->geometry.aperture_end || 320 base + size <= domain->geometry.aperture_start) { 321 pr_warn("specified DMA range outside IOMMU capability\n"); 322 return -EFAULT; 323 } 324 /* ...then finally give it a kicking to make sure it fits */ 325 base_pfn = max_t(unsigned long, base_pfn, 326 domain->geometry.aperture_start >> order); 327 } 328 329 /* start_pfn is always nonzero for an already-initialised domain */ 330 if (iovad->start_pfn) { 331 if (1UL << order != iovad->granule || 332 base_pfn != iovad->start_pfn) { 333 pr_warn("Incompatible range for DMA domain\n"); 334 return -EFAULT; 335 } 336 337 return 0; 338 } 339 340 init_iova_domain(iovad, 1UL << order, base_pfn); 341 342 if (!cookie->fq_domain && !iommu_domain_get_attr(domain, 343 DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && attr) { 344 cookie->fq_domain = domain; 345 init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, NULL); 346 } 347 348 if (!dev) 349 return 0; 350 351 return iova_reserve_iommu_regions(dev, domain); 352 } 353 354 /** 355 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API 356 * page flags. 357 * @dir: Direction of DMA transfer 358 * @coherent: Is the DMA master cache-coherent? 359 * @attrs: DMA attributes for the mapping 360 * 361 * Return: corresponding IOMMU API page protection flags 362 */ 363 static int dma_info_to_prot(enum dma_data_direction dir, bool coherent, 364 unsigned long attrs) 365 { 366 int prot = coherent ? IOMMU_CACHE : 0; 367 368 if (attrs & DMA_ATTR_PRIVILEGED) 369 prot |= IOMMU_PRIV; 370 371 switch (dir) { 372 case DMA_BIDIRECTIONAL: 373 return prot | IOMMU_READ | IOMMU_WRITE; 374 case DMA_TO_DEVICE: 375 return prot | IOMMU_READ; 376 case DMA_FROM_DEVICE: 377 return prot | IOMMU_WRITE; 378 default: 379 return 0; 380 } 381 } 382 383 static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain, 384 size_t size, dma_addr_t dma_limit, struct device *dev) 385 { 386 struct iommu_dma_cookie *cookie = domain->iova_cookie; 387 struct iova_domain *iovad = &cookie->iovad; 388 unsigned long shift, iova_len, iova = 0; 389 390 if (cookie->type == IOMMU_DMA_MSI_COOKIE) { 391 cookie->msi_iova += size; 392 return cookie->msi_iova - size; 393 } 394 395 shift = iova_shift(iovad); 396 iova_len = size >> shift; 397 /* 398 * Freeing non-power-of-two-sized allocations back into the IOVA caches 399 * will come back to bite us badly, so we have to waste a bit of space 400 * rounding up anything cacheable to make sure that can't happen. The 401 * order of the unadjusted size will still match upon freeing. 402 */ 403 if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1))) 404 iova_len = roundup_pow_of_two(iova_len); 405 406 if (dev->bus_dma_mask) 407 dma_limit &= dev->bus_dma_mask; 408 409 if (domain->geometry.force_aperture) 410 dma_limit = min(dma_limit, domain->geometry.aperture_end); 411 412 /* Try to get PCI devices a SAC address */ 413 if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev)) 414 iova = alloc_iova_fast(iovad, iova_len, 415 DMA_BIT_MASK(32) >> shift, false); 416 417 if (!iova) 418 iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift, 419 true); 420 421 return (dma_addr_t)iova << shift; 422 } 423 424 static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie, 425 dma_addr_t iova, size_t size) 426 { 427 struct iova_domain *iovad = &cookie->iovad; 428 429 /* The MSI case is only ever cleaning up its most recent allocation */ 430 if (cookie->type == IOMMU_DMA_MSI_COOKIE) 431 cookie->msi_iova -= size; 432 else if (cookie->fq_domain) /* non-strict mode */ 433 queue_iova(iovad, iova_pfn(iovad, iova), 434 size >> iova_shift(iovad), 0); 435 else 436 free_iova_fast(iovad, iova_pfn(iovad, iova), 437 size >> iova_shift(iovad)); 438 } 439 440 static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr, 441 size_t size) 442 { 443 struct iommu_domain *domain = iommu_get_dma_domain(dev); 444 struct iommu_dma_cookie *cookie = domain->iova_cookie; 445 struct iova_domain *iovad = &cookie->iovad; 446 size_t iova_off = iova_offset(iovad, dma_addr); 447 448 dma_addr -= iova_off; 449 size = iova_align(iovad, size + iova_off); 450 451 WARN_ON(iommu_unmap_fast(domain, dma_addr, size) != size); 452 if (!cookie->fq_domain) 453 iommu_tlb_sync(domain); 454 iommu_dma_free_iova(cookie, dma_addr, size); 455 } 456 457 static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys, 458 size_t size, int prot) 459 { 460 struct iommu_domain *domain = iommu_get_dma_domain(dev); 461 struct iommu_dma_cookie *cookie = domain->iova_cookie; 462 size_t iova_off = 0; 463 dma_addr_t iova; 464 465 if (cookie->type == IOMMU_DMA_IOVA_COOKIE) { 466 iova_off = iova_offset(&cookie->iovad, phys); 467 size = iova_align(&cookie->iovad, size + iova_off); 468 } 469 470 iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev); 471 if (!iova) 472 return DMA_MAPPING_ERROR; 473 474 if (iommu_map(domain, iova, phys - iova_off, size, prot)) { 475 iommu_dma_free_iova(cookie, iova, size); 476 return DMA_MAPPING_ERROR; 477 } 478 return iova + iova_off; 479 } 480 481 static void __iommu_dma_free_pages(struct page **pages, int count) 482 { 483 while (count--) 484 __free_page(pages[count]); 485 kvfree(pages); 486 } 487 488 static struct page **__iommu_dma_alloc_pages(struct device *dev, 489 unsigned int count, unsigned long order_mask, gfp_t gfp) 490 { 491 struct page **pages; 492 unsigned int i = 0, nid = dev_to_node(dev); 493 494 order_mask &= (2U << MAX_ORDER) - 1; 495 if (!order_mask) 496 return NULL; 497 498 pages = kvzalloc(count * sizeof(*pages), GFP_KERNEL); 499 if (!pages) 500 return NULL; 501 502 /* IOMMU can map any pages, so himem can also be used here */ 503 gfp |= __GFP_NOWARN | __GFP_HIGHMEM; 504 505 while (count) { 506 struct page *page = NULL; 507 unsigned int order_size; 508 509 /* 510 * Higher-order allocations are a convenience rather 511 * than a necessity, hence using __GFP_NORETRY until 512 * falling back to minimum-order allocations. 513 */ 514 for (order_mask &= (2U << __fls(count)) - 1; 515 order_mask; order_mask &= ~order_size) { 516 unsigned int order = __fls(order_mask); 517 gfp_t alloc_flags = gfp; 518 519 order_size = 1U << order; 520 if (order_mask > order_size) 521 alloc_flags |= __GFP_NORETRY; 522 page = alloc_pages_node(nid, alloc_flags, order); 523 if (!page) 524 continue; 525 if (!order) 526 break; 527 if (!PageCompound(page)) { 528 split_page(page, order); 529 break; 530 } else if (!split_huge_page(page)) { 531 break; 532 } 533 __free_pages(page, order); 534 } 535 if (!page) { 536 __iommu_dma_free_pages(pages, i); 537 return NULL; 538 } 539 count -= order_size; 540 while (order_size--) 541 pages[i++] = page++; 542 } 543 return pages; 544 } 545 546 static struct page **__iommu_dma_get_pages(void *cpu_addr) 547 { 548 struct vm_struct *area = find_vm_area(cpu_addr); 549 550 if (!area || !area->pages) 551 return NULL; 552 return area->pages; 553 } 554 555 /** 556 * iommu_dma_alloc_remap - Allocate and map a buffer contiguous in IOVA space 557 * @dev: Device to allocate memory for. Must be a real device 558 * attached to an iommu_dma_domain 559 * @size: Size of buffer in bytes 560 * @dma_handle: Out argument for allocated DMA handle 561 * @gfp: Allocation flags 562 * @attrs: DMA attributes for this allocation 563 * 564 * If @size is less than PAGE_SIZE, then a full CPU page will be allocated, 565 * but an IOMMU which supports smaller pages might not map the whole thing. 566 * 567 * Return: Mapped virtual address, or NULL on failure. 568 */ 569 static void *iommu_dma_alloc_remap(struct device *dev, size_t size, 570 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 571 { 572 struct iommu_domain *domain = iommu_get_dma_domain(dev); 573 struct iommu_dma_cookie *cookie = domain->iova_cookie; 574 struct iova_domain *iovad = &cookie->iovad; 575 bool coherent = dev_is_dma_coherent(dev); 576 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs); 577 pgprot_t prot = arch_dma_mmap_pgprot(dev, PAGE_KERNEL, attrs); 578 unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap; 579 struct page **pages; 580 struct sg_table sgt; 581 dma_addr_t iova; 582 void *vaddr; 583 584 *dma_handle = DMA_MAPPING_ERROR; 585 586 min_size = alloc_sizes & -alloc_sizes; 587 if (min_size < PAGE_SIZE) { 588 min_size = PAGE_SIZE; 589 alloc_sizes |= PAGE_SIZE; 590 } else { 591 size = ALIGN(size, min_size); 592 } 593 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES) 594 alloc_sizes = min_size; 595 596 count = PAGE_ALIGN(size) >> PAGE_SHIFT; 597 pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT, 598 gfp); 599 if (!pages) 600 return NULL; 601 602 size = iova_align(iovad, size); 603 iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev); 604 if (!iova) 605 goto out_free_pages; 606 607 if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL)) 608 goto out_free_iova; 609 610 if (!(ioprot & IOMMU_CACHE)) { 611 struct scatterlist *sg; 612 int i; 613 614 for_each_sg(sgt.sgl, sg, sgt.orig_nents, i) 615 arch_dma_prep_coherent(sg_page(sg), sg->length); 616 } 617 618 if (iommu_map_sg(domain, iova, sgt.sgl, sgt.orig_nents, ioprot) 619 < size) 620 goto out_free_sg; 621 622 vaddr = dma_common_pages_remap(pages, size, VM_USERMAP, prot, 623 __builtin_return_address(0)); 624 if (!vaddr) 625 goto out_unmap; 626 627 *dma_handle = iova; 628 sg_free_table(&sgt); 629 return vaddr; 630 631 out_unmap: 632 __iommu_dma_unmap(dev, iova, size); 633 out_free_sg: 634 sg_free_table(&sgt); 635 out_free_iova: 636 iommu_dma_free_iova(cookie, iova, size); 637 out_free_pages: 638 __iommu_dma_free_pages(pages, count); 639 return NULL; 640 } 641 642 /** 643 * __iommu_dma_mmap - Map a buffer into provided user VMA 644 * @pages: Array representing buffer from __iommu_dma_alloc() 645 * @size: Size of buffer in bytes 646 * @vma: VMA describing requested userspace mapping 647 * 648 * Maps the pages of the buffer in @pages into @vma. The caller is responsible 649 * for verifying the correct size and protection of @vma beforehand. 650 */ 651 static int __iommu_dma_mmap(struct page **pages, size_t size, 652 struct vm_area_struct *vma) 653 { 654 return vm_map_pages(vma, pages, PAGE_ALIGN(size) >> PAGE_SHIFT); 655 } 656 657 static void iommu_dma_sync_single_for_cpu(struct device *dev, 658 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) 659 { 660 phys_addr_t phys; 661 662 if (dev_is_dma_coherent(dev)) 663 return; 664 665 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle); 666 arch_sync_dma_for_cpu(dev, phys, size, dir); 667 } 668 669 static void iommu_dma_sync_single_for_device(struct device *dev, 670 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) 671 { 672 phys_addr_t phys; 673 674 if (dev_is_dma_coherent(dev)) 675 return; 676 677 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle); 678 arch_sync_dma_for_device(dev, phys, size, dir); 679 } 680 681 static void iommu_dma_sync_sg_for_cpu(struct device *dev, 682 struct scatterlist *sgl, int nelems, 683 enum dma_data_direction dir) 684 { 685 struct scatterlist *sg; 686 int i; 687 688 if (dev_is_dma_coherent(dev)) 689 return; 690 691 for_each_sg(sgl, sg, nelems, i) 692 arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir); 693 } 694 695 static void iommu_dma_sync_sg_for_device(struct device *dev, 696 struct scatterlist *sgl, int nelems, 697 enum dma_data_direction dir) 698 { 699 struct scatterlist *sg; 700 int i; 701 702 if (dev_is_dma_coherent(dev)) 703 return; 704 705 for_each_sg(sgl, sg, nelems, i) 706 arch_sync_dma_for_device(dev, sg_phys(sg), sg->length, dir); 707 } 708 709 static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page, 710 unsigned long offset, size_t size, enum dma_data_direction dir, 711 unsigned long attrs) 712 { 713 phys_addr_t phys = page_to_phys(page) + offset; 714 bool coherent = dev_is_dma_coherent(dev); 715 int prot = dma_info_to_prot(dir, coherent, attrs); 716 dma_addr_t dma_handle; 717 718 dma_handle =__iommu_dma_map(dev, phys, size, prot); 719 if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && 720 dma_handle != DMA_MAPPING_ERROR) 721 arch_sync_dma_for_device(dev, phys, size, dir); 722 return dma_handle; 723 } 724 725 static void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle, 726 size_t size, enum dma_data_direction dir, unsigned long attrs) 727 { 728 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 729 iommu_dma_sync_single_for_cpu(dev, dma_handle, size, dir); 730 __iommu_dma_unmap(dev, dma_handle, size); 731 } 732 733 /* 734 * Prepare a successfully-mapped scatterlist to give back to the caller. 735 * 736 * At this point the segments are already laid out by iommu_dma_map_sg() to 737 * avoid individually crossing any boundaries, so we merely need to check a 738 * segment's start address to avoid concatenating across one. 739 */ 740 static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents, 741 dma_addr_t dma_addr) 742 { 743 struct scatterlist *s, *cur = sg; 744 unsigned long seg_mask = dma_get_seg_boundary(dev); 745 unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev); 746 int i, count = 0; 747 748 for_each_sg(sg, s, nents, i) { 749 /* Restore this segment's original unaligned fields first */ 750 unsigned int s_iova_off = sg_dma_address(s); 751 unsigned int s_length = sg_dma_len(s); 752 unsigned int s_iova_len = s->length; 753 754 s->offset += s_iova_off; 755 s->length = s_length; 756 sg_dma_address(s) = DMA_MAPPING_ERROR; 757 sg_dma_len(s) = 0; 758 759 /* 760 * Now fill in the real DMA data. If... 761 * - there is a valid output segment to append to 762 * - and this segment starts on an IOVA page boundary 763 * - but doesn't fall at a segment boundary 764 * - and wouldn't make the resulting output segment too long 765 */ 766 if (cur_len && !s_iova_off && (dma_addr & seg_mask) && 767 (cur_len + s_length <= max_len)) { 768 /* ...then concatenate it with the previous one */ 769 cur_len += s_length; 770 } else { 771 /* Otherwise start the next output segment */ 772 if (i > 0) 773 cur = sg_next(cur); 774 cur_len = s_length; 775 count++; 776 777 sg_dma_address(cur) = dma_addr + s_iova_off; 778 } 779 780 sg_dma_len(cur) = cur_len; 781 dma_addr += s_iova_len; 782 783 if (s_length + s_iova_off < s_iova_len) 784 cur_len = 0; 785 } 786 return count; 787 } 788 789 /* 790 * If mapping failed, then just restore the original list, 791 * but making sure the DMA fields are invalidated. 792 */ 793 static void __invalidate_sg(struct scatterlist *sg, int nents) 794 { 795 struct scatterlist *s; 796 int i; 797 798 for_each_sg(sg, s, nents, i) { 799 if (sg_dma_address(s) != DMA_MAPPING_ERROR) 800 s->offset += sg_dma_address(s); 801 if (sg_dma_len(s)) 802 s->length = sg_dma_len(s); 803 sg_dma_address(s) = DMA_MAPPING_ERROR; 804 sg_dma_len(s) = 0; 805 } 806 } 807 808 /* 809 * The DMA API client is passing in a scatterlist which could describe 810 * any old buffer layout, but the IOMMU API requires everything to be 811 * aligned to IOMMU pages. Hence the need for this complicated bit of 812 * impedance-matching, to be able to hand off a suitably-aligned list, 813 * but still preserve the original offsets and sizes for the caller. 814 */ 815 static int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, 816 int nents, enum dma_data_direction dir, unsigned long attrs) 817 { 818 struct iommu_domain *domain = iommu_get_dma_domain(dev); 819 struct iommu_dma_cookie *cookie = domain->iova_cookie; 820 struct iova_domain *iovad = &cookie->iovad; 821 struct scatterlist *s, *prev = NULL; 822 int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs); 823 dma_addr_t iova; 824 size_t iova_len = 0; 825 unsigned long mask = dma_get_seg_boundary(dev); 826 int i; 827 828 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 829 iommu_dma_sync_sg_for_device(dev, sg, nents, dir); 830 831 /* 832 * Work out how much IOVA space we need, and align the segments to 833 * IOVA granules for the IOMMU driver to handle. With some clever 834 * trickery we can modify the list in-place, but reversibly, by 835 * stashing the unaligned parts in the as-yet-unused DMA fields. 836 */ 837 for_each_sg(sg, s, nents, i) { 838 size_t s_iova_off = iova_offset(iovad, s->offset); 839 size_t s_length = s->length; 840 size_t pad_len = (mask - iova_len + 1) & mask; 841 842 sg_dma_address(s) = s_iova_off; 843 sg_dma_len(s) = s_length; 844 s->offset -= s_iova_off; 845 s_length = iova_align(iovad, s_length + s_iova_off); 846 s->length = s_length; 847 848 /* 849 * Due to the alignment of our single IOVA allocation, we can 850 * depend on these assumptions about the segment boundary mask: 851 * - If mask size >= IOVA size, then the IOVA range cannot 852 * possibly fall across a boundary, so we don't care. 853 * - If mask size < IOVA size, then the IOVA range must start 854 * exactly on a boundary, therefore we can lay things out 855 * based purely on segment lengths without needing to know 856 * the actual addresses beforehand. 857 * - The mask must be a power of 2, so pad_len == 0 if 858 * iova_len == 0, thus we cannot dereference prev the first 859 * time through here (i.e. before it has a meaningful value). 860 */ 861 if (pad_len && pad_len < s_length - 1) { 862 prev->length += pad_len; 863 iova_len += pad_len; 864 } 865 866 iova_len += s_length; 867 prev = s; 868 } 869 870 iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev); 871 if (!iova) 872 goto out_restore_sg; 873 874 /* 875 * We'll leave any physical concatenation to the IOMMU driver's 876 * implementation - it knows better than we do. 877 */ 878 if (iommu_map_sg(domain, iova, sg, nents, prot) < iova_len) 879 goto out_free_iova; 880 881 return __finalise_sg(dev, sg, nents, iova); 882 883 out_free_iova: 884 iommu_dma_free_iova(cookie, iova, iova_len); 885 out_restore_sg: 886 __invalidate_sg(sg, nents); 887 return 0; 888 } 889 890 static void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, 891 int nents, enum dma_data_direction dir, unsigned long attrs) 892 { 893 dma_addr_t start, end; 894 struct scatterlist *tmp; 895 int i; 896 897 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 898 iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir); 899 900 /* 901 * The scatterlist segments are mapped into a single 902 * contiguous IOVA allocation, so this is incredibly easy. 903 */ 904 start = sg_dma_address(sg); 905 for_each_sg(sg_next(sg), tmp, nents - 1, i) { 906 if (sg_dma_len(tmp) == 0) 907 break; 908 sg = tmp; 909 } 910 end = sg_dma_address(sg) + sg_dma_len(sg); 911 __iommu_dma_unmap(dev, start, end - start); 912 } 913 914 static dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys, 915 size_t size, enum dma_data_direction dir, unsigned long attrs) 916 { 917 return __iommu_dma_map(dev, phys, size, 918 dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO); 919 } 920 921 static void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, 922 size_t size, enum dma_data_direction dir, unsigned long attrs) 923 { 924 __iommu_dma_unmap(dev, handle, size); 925 } 926 927 static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr) 928 { 929 size_t alloc_size = PAGE_ALIGN(size); 930 int count = alloc_size >> PAGE_SHIFT; 931 struct page *page = NULL, **pages = NULL; 932 933 /* Non-coherent atomic allocation? Easy */ 934 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 935 dma_free_from_pool(cpu_addr, alloc_size)) 936 return; 937 938 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) { 939 /* 940 * If it the address is remapped, then it's either non-coherent 941 * or highmem CMA, or an iommu_dma_alloc_remap() construction. 942 */ 943 pages = __iommu_dma_get_pages(cpu_addr); 944 if (!pages) 945 page = vmalloc_to_page(cpu_addr); 946 dma_common_free_remap(cpu_addr, alloc_size, VM_USERMAP); 947 } else { 948 /* Lowmem means a coherent atomic or CMA allocation */ 949 page = virt_to_page(cpu_addr); 950 } 951 952 if (pages) 953 __iommu_dma_free_pages(pages, count); 954 if (page) 955 dma_free_contiguous(dev, page, alloc_size); 956 } 957 958 static void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr, 959 dma_addr_t handle, unsigned long attrs) 960 { 961 __iommu_dma_unmap(dev, handle, size); 962 __iommu_dma_free(dev, size, cpu_addr); 963 } 964 965 static void *iommu_dma_alloc_pages(struct device *dev, size_t size, 966 struct page **pagep, gfp_t gfp, unsigned long attrs) 967 { 968 bool coherent = dev_is_dma_coherent(dev); 969 size_t alloc_size = PAGE_ALIGN(size); 970 struct page *page = NULL; 971 void *cpu_addr; 972 973 page = dma_alloc_contiguous(dev, alloc_size, gfp); 974 if (!page) 975 return NULL; 976 977 if (IS_ENABLED(CONFIG_DMA_REMAP) && (!coherent || PageHighMem(page))) { 978 pgprot_t prot = arch_dma_mmap_pgprot(dev, PAGE_KERNEL, attrs); 979 980 cpu_addr = dma_common_contiguous_remap(page, alloc_size, 981 VM_USERMAP, prot, __builtin_return_address(0)); 982 if (!cpu_addr) 983 goto out_free_pages; 984 985 if (!coherent) 986 arch_dma_prep_coherent(page, size); 987 } else { 988 cpu_addr = page_address(page); 989 } 990 991 *pagep = page; 992 memset(cpu_addr, 0, alloc_size); 993 return cpu_addr; 994 out_free_pages: 995 dma_free_contiguous(dev, page, alloc_size); 996 return NULL; 997 } 998 999 static void *iommu_dma_alloc(struct device *dev, size_t size, 1000 dma_addr_t *handle, gfp_t gfp, unsigned long attrs) 1001 { 1002 bool coherent = dev_is_dma_coherent(dev); 1003 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs); 1004 struct page *page = NULL; 1005 void *cpu_addr; 1006 1007 gfp |= __GFP_ZERO; 1008 1009 if (IS_ENABLED(CONFIG_DMA_REMAP) && gfpflags_allow_blocking(gfp) && 1010 !(attrs & DMA_ATTR_FORCE_CONTIGUOUS)) 1011 return iommu_dma_alloc_remap(dev, size, handle, gfp, attrs); 1012 1013 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 1014 !gfpflags_allow_blocking(gfp) && !coherent) 1015 cpu_addr = dma_alloc_from_pool(PAGE_ALIGN(size), &page, gfp); 1016 else 1017 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs); 1018 if (!cpu_addr) 1019 return NULL; 1020 1021 *handle = __iommu_dma_map(dev, page_to_phys(page), size, ioprot); 1022 if (*handle == DMA_MAPPING_ERROR) { 1023 __iommu_dma_free(dev, size, cpu_addr); 1024 return NULL; 1025 } 1026 1027 return cpu_addr; 1028 } 1029 1030 static int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma, 1031 void *cpu_addr, dma_addr_t dma_addr, size_t size, 1032 unsigned long attrs) 1033 { 1034 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 1035 unsigned long pfn, off = vma->vm_pgoff; 1036 int ret; 1037 1038 vma->vm_page_prot = arch_dma_mmap_pgprot(dev, vma->vm_page_prot, attrs); 1039 1040 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) 1041 return ret; 1042 1043 if (off >= nr_pages || vma_pages(vma) > nr_pages - off) 1044 return -ENXIO; 1045 1046 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) { 1047 struct page **pages = __iommu_dma_get_pages(cpu_addr); 1048 1049 if (pages) 1050 return __iommu_dma_mmap(pages, size, vma); 1051 pfn = vmalloc_to_pfn(cpu_addr); 1052 } else { 1053 pfn = page_to_pfn(virt_to_page(cpu_addr)); 1054 } 1055 1056 return remap_pfn_range(vma, vma->vm_start, pfn + off, 1057 vma->vm_end - vma->vm_start, 1058 vma->vm_page_prot); 1059 } 1060 1061 static int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt, 1062 void *cpu_addr, dma_addr_t dma_addr, size_t size, 1063 unsigned long attrs) 1064 { 1065 struct page *page; 1066 int ret; 1067 1068 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) { 1069 struct page **pages = __iommu_dma_get_pages(cpu_addr); 1070 1071 if (pages) { 1072 return sg_alloc_table_from_pages(sgt, pages, 1073 PAGE_ALIGN(size) >> PAGE_SHIFT, 1074 0, size, GFP_KERNEL); 1075 } 1076 1077 page = vmalloc_to_page(cpu_addr); 1078 } else { 1079 page = virt_to_page(cpu_addr); 1080 } 1081 1082 ret = sg_alloc_table(sgt, 1, GFP_KERNEL); 1083 if (!ret) 1084 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); 1085 return ret; 1086 } 1087 1088 static const struct dma_map_ops iommu_dma_ops = { 1089 .alloc = iommu_dma_alloc, 1090 .free = iommu_dma_free, 1091 .mmap = iommu_dma_mmap, 1092 .get_sgtable = iommu_dma_get_sgtable, 1093 .map_page = iommu_dma_map_page, 1094 .unmap_page = iommu_dma_unmap_page, 1095 .map_sg = iommu_dma_map_sg, 1096 .unmap_sg = iommu_dma_unmap_sg, 1097 .sync_single_for_cpu = iommu_dma_sync_single_for_cpu, 1098 .sync_single_for_device = iommu_dma_sync_single_for_device, 1099 .sync_sg_for_cpu = iommu_dma_sync_sg_for_cpu, 1100 .sync_sg_for_device = iommu_dma_sync_sg_for_device, 1101 .map_resource = iommu_dma_map_resource, 1102 .unmap_resource = iommu_dma_unmap_resource, 1103 }; 1104 1105 /* 1106 * The IOMMU core code allocates the default DMA domain, which the underlying 1107 * IOMMU driver needs to support via the dma-iommu layer. 1108 */ 1109 void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size) 1110 { 1111 struct iommu_domain *domain = iommu_get_domain_for_dev(dev); 1112 1113 if (!domain) 1114 goto out_err; 1115 1116 /* 1117 * The IOMMU core code allocates the default DMA domain, which the 1118 * underlying IOMMU driver needs to support via the dma-iommu layer. 1119 */ 1120 if (domain->type == IOMMU_DOMAIN_DMA) { 1121 if (iommu_dma_init_domain(domain, dma_base, size, dev)) 1122 goto out_err; 1123 dev->dma_ops = &iommu_dma_ops; 1124 } 1125 1126 return; 1127 out_err: 1128 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n", 1129 dev_name(dev)); 1130 } 1131 1132 static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev, 1133 phys_addr_t msi_addr, struct iommu_domain *domain) 1134 { 1135 struct iommu_dma_cookie *cookie = domain->iova_cookie; 1136 struct iommu_dma_msi_page *msi_page; 1137 dma_addr_t iova; 1138 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; 1139 size_t size = cookie_msi_granule(cookie); 1140 1141 msi_addr &= ~(phys_addr_t)(size - 1); 1142 list_for_each_entry(msi_page, &cookie->msi_page_list, list) 1143 if (msi_page->phys == msi_addr) 1144 return msi_page; 1145 1146 msi_page = kzalloc(sizeof(*msi_page), GFP_ATOMIC); 1147 if (!msi_page) 1148 return NULL; 1149 1150 iova = __iommu_dma_map(dev, msi_addr, size, prot); 1151 if (iova == DMA_MAPPING_ERROR) 1152 goto out_free_page; 1153 1154 INIT_LIST_HEAD(&msi_page->list); 1155 msi_page->phys = msi_addr; 1156 msi_page->iova = iova; 1157 list_add(&msi_page->list, &cookie->msi_page_list); 1158 return msi_page; 1159 1160 out_free_page: 1161 kfree(msi_page); 1162 return NULL; 1163 } 1164 1165 int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) 1166 { 1167 struct device *dev = msi_desc_to_dev(desc); 1168 struct iommu_domain *domain = iommu_get_domain_for_dev(dev); 1169 struct iommu_dma_cookie *cookie; 1170 struct iommu_dma_msi_page *msi_page; 1171 unsigned long flags; 1172 1173 if (!domain || !domain->iova_cookie) { 1174 desc->iommu_cookie = NULL; 1175 return 0; 1176 } 1177 1178 cookie = domain->iova_cookie; 1179 1180 /* 1181 * We disable IRQs to rule out a possible inversion against 1182 * irq_desc_lock if, say, someone tries to retarget the affinity 1183 * of an MSI from within an IPI handler. 1184 */ 1185 spin_lock_irqsave(&cookie->msi_lock, flags); 1186 msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain); 1187 spin_unlock_irqrestore(&cookie->msi_lock, flags); 1188 1189 msi_desc_set_iommu_cookie(desc, msi_page); 1190 1191 if (!msi_page) 1192 return -ENOMEM; 1193 return 0; 1194 } 1195 1196 void iommu_dma_compose_msi_msg(struct msi_desc *desc, 1197 struct msi_msg *msg) 1198 { 1199 struct device *dev = msi_desc_to_dev(desc); 1200 const struct iommu_domain *domain = iommu_get_domain_for_dev(dev); 1201 const struct iommu_dma_msi_page *msi_page; 1202 1203 msi_page = msi_desc_get_iommu_cookie(desc); 1204 1205 if (!domain || !domain->iova_cookie || WARN_ON(!msi_page)) 1206 return; 1207 1208 msg->address_hi = upper_32_bits(msi_page->iova); 1209 msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1; 1210 msg->address_lo += lower_32_bits(msi_page->iova); 1211 } 1212 1213 static int iommu_dma_init(void) 1214 { 1215 return iova_cache_get(); 1216 } 1217 arch_initcall(iommu_dma_init); 1218