1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c 4 * 5 * Copyright (C) 2013 ARM Limited 6 * Copyright (C) 2017 Red Hat 7 */ 8 9 #include <linux/atomic.h> 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dma-iommu.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/io-64-nonatomic-hi-lo.h> 19 #include <linux/io-pgtable.h> 20 #include <linux/iommu.h> 21 #include <linux/iopoll.h> 22 #include <linux/kconfig.h> 23 #include <linux/init.h> 24 #include <linux/mutex.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/of_iommu.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/qcom_scm.h> 33 #include <linux/slab.h> 34 #include <linux/spinlock.h> 35 36 #include "arm-smmu.h" 37 38 #define SMMU_INTR_SEL_NS 0x2000 39 40 enum qcom_iommu_clk { 41 CLK_IFACE, 42 CLK_BUS, 43 CLK_TBU, 44 CLK_NUM, 45 }; 46 47 struct qcom_iommu_ctx; 48 49 struct qcom_iommu_dev { 50 /* IOMMU core code handle */ 51 struct iommu_device iommu; 52 struct device *dev; 53 struct clk_bulk_data clks[CLK_NUM]; 54 void __iomem *local_base; 55 u32 sec_id; 56 u8 num_ctxs; 57 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */ 58 }; 59 60 struct qcom_iommu_ctx { 61 struct device *dev; 62 void __iomem *base; 63 bool secure_init; 64 u8 asid; /* asid and ctx bank # are 1:1 */ 65 struct iommu_domain *domain; 66 }; 67 68 struct qcom_iommu_domain { 69 struct io_pgtable_ops *pgtbl_ops; 70 spinlock_t pgtbl_lock; 71 struct mutex init_mutex; /* Protects iommu pointer */ 72 struct iommu_domain domain; 73 struct qcom_iommu_dev *iommu; 74 struct iommu_fwspec *fwspec; 75 }; 76 77 static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom) 78 { 79 return container_of(dom, struct qcom_iommu_domain, domain); 80 } 81 82 static const struct iommu_ops qcom_iommu_ops; 83 84 static struct qcom_iommu_dev * to_iommu(struct device *dev) 85 { 86 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 87 88 if (!fwspec || fwspec->ops != &qcom_iommu_ops) 89 return NULL; 90 91 return dev_iommu_priv_get(dev); 92 } 93 94 static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid) 95 { 96 struct qcom_iommu_dev *qcom_iommu = d->iommu; 97 if (!qcom_iommu) 98 return NULL; 99 return qcom_iommu->ctxs[asid - 1]; 100 } 101 102 static inline void 103 iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val) 104 { 105 writel_relaxed(val, ctx->base + reg); 106 } 107 108 static inline void 109 iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val) 110 { 111 writeq_relaxed(val, ctx->base + reg); 112 } 113 114 static inline u32 115 iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg) 116 { 117 return readl_relaxed(ctx->base + reg); 118 } 119 120 static inline u64 121 iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg) 122 { 123 return readq_relaxed(ctx->base + reg); 124 } 125 126 static void qcom_iommu_tlb_sync(void *cookie) 127 { 128 struct qcom_iommu_domain *qcom_domain = cookie; 129 struct iommu_fwspec *fwspec = qcom_domain->fwspec; 130 unsigned i; 131 132 for (i = 0; i < fwspec->num_ids; i++) { 133 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 134 unsigned int val, ret; 135 136 iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0); 137 138 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val, 139 (val & 0x1) == 0, 0, 5000000); 140 if (ret) 141 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n"); 142 } 143 } 144 145 static void qcom_iommu_tlb_inv_context(void *cookie) 146 { 147 struct qcom_iommu_domain *qcom_domain = cookie; 148 struct iommu_fwspec *fwspec = qcom_domain->fwspec; 149 unsigned i; 150 151 for (i = 0; i < fwspec->num_ids; i++) { 152 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 153 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid); 154 } 155 156 qcom_iommu_tlb_sync(cookie); 157 } 158 159 static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size, 160 size_t granule, bool leaf, void *cookie) 161 { 162 struct qcom_iommu_domain *qcom_domain = cookie; 163 struct iommu_fwspec *fwspec = qcom_domain->fwspec; 164 unsigned i, reg; 165 166 reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; 167 168 for (i = 0; i < fwspec->num_ids; i++) { 169 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 170 size_t s = size; 171 172 iova = (iova >> 12) << 12; 173 iova |= ctx->asid; 174 do { 175 iommu_writel(ctx, reg, iova); 176 iova += granule; 177 } while (s -= granule); 178 } 179 } 180 181 static void qcom_iommu_tlb_flush_walk(unsigned long iova, size_t size, 182 size_t granule, void *cookie) 183 { 184 qcom_iommu_tlb_inv_range_nosync(iova, size, granule, false, cookie); 185 qcom_iommu_tlb_sync(cookie); 186 } 187 188 static void qcom_iommu_tlb_add_page(struct iommu_iotlb_gather *gather, 189 unsigned long iova, size_t granule, 190 void *cookie) 191 { 192 qcom_iommu_tlb_inv_range_nosync(iova, granule, granule, true, cookie); 193 } 194 195 static const struct iommu_flush_ops qcom_flush_ops = { 196 .tlb_flush_all = qcom_iommu_tlb_inv_context, 197 .tlb_flush_walk = qcom_iommu_tlb_flush_walk, 198 .tlb_add_page = qcom_iommu_tlb_add_page, 199 }; 200 201 static irqreturn_t qcom_iommu_fault(int irq, void *dev) 202 { 203 struct qcom_iommu_ctx *ctx = dev; 204 u32 fsr, fsynr; 205 u64 iova; 206 207 fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR); 208 209 if (!(fsr & ARM_SMMU_FSR_FAULT)) 210 return IRQ_NONE; 211 212 fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0); 213 iova = iommu_readq(ctx, ARM_SMMU_CB_FAR); 214 215 if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) { 216 dev_err_ratelimited(ctx->dev, 217 "Unhandled context fault: fsr=0x%x, " 218 "iova=0x%016llx, fsynr=0x%x, cb=%d\n", 219 fsr, iova, fsynr, ctx->asid); 220 } 221 222 iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr); 223 iommu_writel(ctx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE); 224 225 return IRQ_HANDLED; 226 } 227 228 static int qcom_iommu_init_domain(struct iommu_domain *domain, 229 struct qcom_iommu_dev *qcom_iommu, 230 struct device *dev) 231 { 232 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 233 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 234 struct io_pgtable_ops *pgtbl_ops; 235 struct io_pgtable_cfg pgtbl_cfg; 236 int i, ret = 0; 237 u32 reg; 238 239 mutex_lock(&qcom_domain->init_mutex); 240 if (qcom_domain->iommu) 241 goto out_unlock; 242 243 pgtbl_cfg = (struct io_pgtable_cfg) { 244 .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap, 245 .ias = 32, 246 .oas = 40, 247 .tlb = &qcom_flush_ops, 248 .iommu_dev = qcom_iommu->dev, 249 }; 250 251 qcom_domain->iommu = qcom_iommu; 252 qcom_domain->fwspec = fwspec; 253 254 pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, qcom_domain); 255 if (!pgtbl_ops) { 256 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n"); 257 ret = -ENOMEM; 258 goto out_clear_iommu; 259 } 260 261 /* Update the domain's page sizes to reflect the page table format */ 262 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; 263 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1; 264 domain->geometry.force_aperture = true; 265 266 for (i = 0; i < fwspec->num_ids; i++) { 267 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 268 269 if (!ctx->secure_init) { 270 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); 271 if (ret) { 272 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret); 273 goto out_clear_iommu; 274 } 275 ctx->secure_init = true; 276 } 277 278 /* TTBRs */ 279 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 280 pgtbl_cfg.arm_lpae_s1_cfg.ttbr | 281 FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); 282 iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); 283 284 /* TCR */ 285 iommu_writel(ctx, ARM_SMMU_CB_TCR2, 286 arm_smmu_lpae_tcr2(&pgtbl_cfg)); 287 iommu_writel(ctx, ARM_SMMU_CB_TCR, 288 arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE); 289 290 /* MAIRs (stage-1 only) */ 291 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 292 pgtbl_cfg.arm_lpae_s1_cfg.mair); 293 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 294 pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32); 295 296 /* SCTLR */ 297 reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | 298 ARM_SMMU_SCTLR_AFE | ARM_SMMU_SCTLR_TRE | 299 ARM_SMMU_SCTLR_M | ARM_SMMU_SCTLR_S1_ASIDPNE | 300 ARM_SMMU_SCTLR_CFCFG; 301 302 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 303 reg |= ARM_SMMU_SCTLR_E; 304 305 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg); 306 307 ctx->domain = domain; 308 } 309 310 mutex_unlock(&qcom_domain->init_mutex); 311 312 /* Publish page table ops for map/unmap */ 313 qcom_domain->pgtbl_ops = pgtbl_ops; 314 315 return 0; 316 317 out_clear_iommu: 318 qcom_domain->iommu = NULL; 319 out_unlock: 320 mutex_unlock(&qcom_domain->init_mutex); 321 return ret; 322 } 323 324 static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type) 325 { 326 struct qcom_iommu_domain *qcom_domain; 327 328 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) 329 return NULL; 330 /* 331 * Allocate the domain and initialise some of its data structures. 332 * We can't really do anything meaningful until we've added a 333 * master. 334 */ 335 qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL); 336 if (!qcom_domain) 337 return NULL; 338 339 if (type == IOMMU_DOMAIN_DMA && 340 iommu_get_dma_cookie(&qcom_domain->domain)) { 341 kfree(qcom_domain); 342 return NULL; 343 } 344 345 mutex_init(&qcom_domain->init_mutex); 346 spin_lock_init(&qcom_domain->pgtbl_lock); 347 348 return &qcom_domain->domain; 349 } 350 351 static void qcom_iommu_domain_free(struct iommu_domain *domain) 352 { 353 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 354 355 iommu_put_dma_cookie(domain); 356 357 if (qcom_domain->iommu) { 358 /* 359 * NOTE: unmap can be called after client device is powered 360 * off, for example, with GPUs or anything involving dma-buf. 361 * So we cannot rely on the device_link. Make sure the IOMMU 362 * is on to avoid unclocked accesses in the TLB inv path: 363 */ 364 pm_runtime_get_sync(qcom_domain->iommu->dev); 365 free_io_pgtable_ops(qcom_domain->pgtbl_ops); 366 pm_runtime_put_sync(qcom_domain->iommu->dev); 367 } 368 369 kfree(qcom_domain); 370 } 371 372 static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) 373 { 374 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); 375 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 376 int ret; 377 378 if (!qcom_iommu) { 379 dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n"); 380 return -ENXIO; 381 } 382 383 /* Ensure that the domain is finalized */ 384 pm_runtime_get_sync(qcom_iommu->dev); 385 ret = qcom_iommu_init_domain(domain, qcom_iommu, dev); 386 pm_runtime_put_sync(qcom_iommu->dev); 387 if (ret < 0) 388 return ret; 389 390 /* 391 * Sanity check the domain. We don't support domains across 392 * different IOMMUs. 393 */ 394 if (qcom_domain->iommu != qcom_iommu) { 395 dev_err(dev, "cannot attach to IOMMU %s while already " 396 "attached to domain on IOMMU %s\n", 397 dev_name(qcom_domain->iommu->dev), 398 dev_name(qcom_iommu->dev)); 399 return -EINVAL; 400 } 401 402 return 0; 403 } 404 405 static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev) 406 { 407 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 408 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 409 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); 410 unsigned i; 411 412 if (WARN_ON(!qcom_domain->iommu)) 413 return; 414 415 pm_runtime_get_sync(qcom_iommu->dev); 416 for (i = 0; i < fwspec->num_ids; i++) { 417 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 418 419 /* Disable the context bank: */ 420 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); 421 422 ctx->domain = NULL; 423 } 424 pm_runtime_put_sync(qcom_iommu->dev); 425 } 426 427 static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova, 428 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 429 { 430 int ret; 431 unsigned long flags; 432 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 433 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; 434 435 if (!ops) 436 return -ENODEV; 437 438 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); 439 ret = ops->map(ops, iova, paddr, size, prot, GFP_ATOMIC); 440 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); 441 return ret; 442 } 443 444 static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 445 size_t size, struct iommu_iotlb_gather *gather) 446 { 447 size_t ret; 448 unsigned long flags; 449 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 450 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; 451 452 if (!ops) 453 return 0; 454 455 /* NOTE: unmap can be called after client device is powered off, 456 * for example, with GPUs or anything involving dma-buf. So we 457 * cannot rely on the device_link. Make sure the IOMMU is on to 458 * avoid unclocked accesses in the TLB inv path: 459 */ 460 pm_runtime_get_sync(qcom_domain->iommu->dev); 461 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); 462 ret = ops->unmap(ops, iova, size, gather); 463 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); 464 pm_runtime_put_sync(qcom_domain->iommu->dev); 465 466 return ret; 467 } 468 469 static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain) 470 { 471 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 472 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops, 473 struct io_pgtable, ops); 474 if (!qcom_domain->pgtbl_ops) 475 return; 476 477 pm_runtime_get_sync(qcom_domain->iommu->dev); 478 qcom_iommu_tlb_sync(pgtable->cookie); 479 pm_runtime_put_sync(qcom_domain->iommu->dev); 480 } 481 482 static void qcom_iommu_iotlb_sync(struct iommu_domain *domain, 483 struct iommu_iotlb_gather *gather) 484 { 485 qcom_iommu_flush_iotlb_all(domain); 486 } 487 488 static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain, 489 dma_addr_t iova) 490 { 491 phys_addr_t ret; 492 unsigned long flags; 493 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 494 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; 495 496 if (!ops) 497 return 0; 498 499 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); 500 ret = ops->iova_to_phys(ops, iova); 501 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); 502 503 return ret; 504 } 505 506 static bool qcom_iommu_capable(enum iommu_cap cap) 507 { 508 switch (cap) { 509 case IOMMU_CAP_CACHE_COHERENCY: 510 /* 511 * Return true here as the SMMU can always send out coherent 512 * requests. 513 */ 514 return true; 515 case IOMMU_CAP_NOEXEC: 516 return true; 517 default: 518 return false; 519 } 520 } 521 522 static struct iommu_device *qcom_iommu_probe_device(struct device *dev) 523 { 524 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); 525 struct device_link *link; 526 527 if (!qcom_iommu) 528 return ERR_PTR(-ENODEV); 529 530 /* 531 * Establish the link between iommu and master, so that the 532 * iommu gets runtime enabled/disabled as per the master's 533 * needs. 534 */ 535 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME); 536 if (!link) { 537 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n", 538 dev_name(qcom_iommu->dev), dev_name(dev)); 539 return ERR_PTR(-ENODEV); 540 } 541 542 return &qcom_iommu->iommu; 543 } 544 545 static void qcom_iommu_release_device(struct device *dev) 546 { 547 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); 548 549 if (!qcom_iommu) 550 return; 551 552 iommu_fwspec_free(dev); 553 } 554 555 static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 556 { 557 struct qcom_iommu_dev *qcom_iommu; 558 struct platform_device *iommu_pdev; 559 unsigned asid = args->args[0]; 560 561 if (args->args_count != 1) { 562 dev_err(dev, "incorrect number of iommu params found for %s " 563 "(found %d, expected 1)\n", 564 args->np->full_name, args->args_count); 565 return -EINVAL; 566 } 567 568 iommu_pdev = of_find_device_by_node(args->np); 569 if (WARN_ON(!iommu_pdev)) 570 return -EINVAL; 571 572 qcom_iommu = platform_get_drvdata(iommu_pdev); 573 574 /* make sure the asid specified in dt is valid, so we don't have 575 * to sanity check this elsewhere, since 'asid - 1' is used to 576 * index into qcom_iommu->ctxs: 577 */ 578 if (WARN_ON(asid < 1) || 579 WARN_ON(asid > qcom_iommu->num_ctxs)) { 580 put_device(&iommu_pdev->dev); 581 return -EINVAL; 582 } 583 584 if (!dev_iommu_priv_get(dev)) { 585 dev_iommu_priv_set(dev, qcom_iommu); 586 } else { 587 /* make sure devices iommus dt node isn't referring to 588 * multiple different iommu devices. Multiple context 589 * banks are ok, but multiple devices are not: 590 */ 591 if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev))) { 592 put_device(&iommu_pdev->dev); 593 return -EINVAL; 594 } 595 } 596 597 return iommu_fwspec_add_ids(dev, &asid, 1); 598 } 599 600 static const struct iommu_ops qcom_iommu_ops = { 601 .capable = qcom_iommu_capable, 602 .domain_alloc = qcom_iommu_domain_alloc, 603 .domain_free = qcom_iommu_domain_free, 604 .attach_dev = qcom_iommu_attach_dev, 605 .detach_dev = qcom_iommu_detach_dev, 606 .map = qcom_iommu_map, 607 .unmap = qcom_iommu_unmap, 608 .flush_iotlb_all = qcom_iommu_flush_iotlb_all, 609 .iotlb_sync = qcom_iommu_iotlb_sync, 610 .iova_to_phys = qcom_iommu_iova_to_phys, 611 .probe_device = qcom_iommu_probe_device, 612 .release_device = qcom_iommu_release_device, 613 .device_group = generic_device_group, 614 .of_xlate = qcom_iommu_of_xlate, 615 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 616 }; 617 618 static int qcom_iommu_sec_ptbl_init(struct device *dev) 619 { 620 size_t psize = 0; 621 unsigned int spare = 0; 622 void *cpu_addr; 623 dma_addr_t paddr; 624 unsigned long attrs; 625 static bool allocated = false; 626 int ret; 627 628 if (allocated) 629 return 0; 630 631 ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize); 632 if (ret) { 633 dev_err(dev, "failed to get iommu secure pgtable size (%d)\n", 634 ret); 635 return ret; 636 } 637 638 dev_info(dev, "iommu sec: pgtable size: %zu\n", psize); 639 640 attrs = DMA_ATTR_NO_KERNEL_MAPPING; 641 642 cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs); 643 if (!cpu_addr) { 644 dev_err(dev, "failed to allocate %zu bytes for pgtable\n", 645 psize); 646 return -ENOMEM; 647 } 648 649 ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare); 650 if (ret) { 651 dev_err(dev, "failed to init iommu pgtable (%d)\n", ret); 652 goto free_mem; 653 } 654 655 allocated = true; 656 return 0; 657 658 free_mem: 659 dma_free_attrs(dev, psize, cpu_addr, paddr, attrs); 660 return ret; 661 } 662 663 static int get_asid(const struct device_node *np) 664 { 665 u32 reg; 666 667 /* read the "reg" property directly to get the relative address 668 * of the context bank, and calculate the asid from that: 669 */ 670 if (of_property_read_u32_index(np, "reg", 0, ®)) 671 return -ENODEV; 672 673 return reg / 0x1000; /* context banks are 0x1000 apart */ 674 } 675 676 static int qcom_iommu_ctx_probe(struct platform_device *pdev) 677 { 678 struct qcom_iommu_ctx *ctx; 679 struct device *dev = &pdev->dev; 680 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent); 681 struct resource *res; 682 int ret, irq; 683 684 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 685 if (!ctx) 686 return -ENOMEM; 687 688 ctx->dev = dev; 689 platform_set_drvdata(pdev, ctx); 690 691 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 692 ctx->base = devm_ioremap_resource(dev, res); 693 if (IS_ERR(ctx->base)) 694 return PTR_ERR(ctx->base); 695 696 irq = platform_get_irq(pdev, 0); 697 if (irq < 0) 698 return -ENODEV; 699 700 /* clear IRQs before registering fault handler, just in case the 701 * boot-loader left us a surprise: 702 */ 703 iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR)); 704 705 ret = devm_request_irq(dev, irq, 706 qcom_iommu_fault, 707 IRQF_SHARED, 708 "qcom-iommu-fault", 709 ctx); 710 if (ret) { 711 dev_err(dev, "failed to request IRQ %u\n", irq); 712 return ret; 713 } 714 715 ret = get_asid(dev->of_node); 716 if (ret < 0) { 717 dev_err(dev, "missing reg property\n"); 718 return ret; 719 } 720 721 ctx->asid = ret; 722 723 dev_dbg(dev, "found asid %u\n", ctx->asid); 724 725 qcom_iommu->ctxs[ctx->asid - 1] = ctx; 726 727 return 0; 728 } 729 730 static int qcom_iommu_ctx_remove(struct platform_device *pdev) 731 { 732 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent); 733 struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev); 734 735 platform_set_drvdata(pdev, NULL); 736 737 qcom_iommu->ctxs[ctx->asid - 1] = NULL; 738 739 return 0; 740 } 741 742 static const struct of_device_id ctx_of_match[] = { 743 { .compatible = "qcom,msm-iommu-v1-ns" }, 744 { .compatible = "qcom,msm-iommu-v1-sec" }, 745 { /* sentinel */ } 746 }; 747 748 static struct platform_driver qcom_iommu_ctx_driver = { 749 .driver = { 750 .name = "qcom-iommu-ctx", 751 .of_match_table = ctx_of_match, 752 }, 753 .probe = qcom_iommu_ctx_probe, 754 .remove = qcom_iommu_ctx_remove, 755 }; 756 757 static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu) 758 { 759 struct device_node *child; 760 761 for_each_child_of_node(qcom_iommu->dev->of_node, child) 762 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) 763 return true; 764 765 return false; 766 } 767 768 static int qcom_iommu_device_probe(struct platform_device *pdev) 769 { 770 struct device_node *child; 771 struct qcom_iommu_dev *qcom_iommu; 772 struct device *dev = &pdev->dev; 773 struct resource *res; 774 struct clk *clk; 775 int ret, max_asid = 0; 776 777 /* find the max asid (which is 1:1 to ctx bank idx), so we know how 778 * many child ctx devices we have: 779 */ 780 for_each_child_of_node(dev->of_node, child) 781 max_asid = max(max_asid, get_asid(child)); 782 783 qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid), 784 GFP_KERNEL); 785 if (!qcom_iommu) 786 return -ENOMEM; 787 qcom_iommu->num_ctxs = max_asid; 788 qcom_iommu->dev = dev; 789 790 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 791 if (res) { 792 qcom_iommu->local_base = devm_ioremap_resource(dev, res); 793 if (IS_ERR(qcom_iommu->local_base)) 794 return PTR_ERR(qcom_iommu->local_base); 795 } 796 797 clk = devm_clk_get(dev, "iface"); 798 if (IS_ERR(clk)) { 799 dev_err(dev, "failed to get iface clock\n"); 800 return PTR_ERR(clk); 801 } 802 qcom_iommu->clks[CLK_IFACE].clk = clk; 803 804 clk = devm_clk_get(dev, "bus"); 805 if (IS_ERR(clk)) { 806 dev_err(dev, "failed to get bus clock\n"); 807 return PTR_ERR(clk); 808 } 809 qcom_iommu->clks[CLK_BUS].clk = clk; 810 811 clk = devm_clk_get_optional(dev, "tbu"); 812 if (IS_ERR(clk)) { 813 dev_err(dev, "failed to get tbu clock\n"); 814 return PTR_ERR(clk); 815 } 816 qcom_iommu->clks[CLK_TBU].clk = clk; 817 818 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id", 819 &qcom_iommu->sec_id)) { 820 dev_err(dev, "missing qcom,iommu-secure-id property\n"); 821 return -ENODEV; 822 } 823 824 if (qcom_iommu_has_secure_context(qcom_iommu)) { 825 ret = qcom_iommu_sec_ptbl_init(dev); 826 if (ret) { 827 dev_err(dev, "cannot init secure pg table(%d)\n", ret); 828 return ret; 829 } 830 } 831 832 platform_set_drvdata(pdev, qcom_iommu); 833 834 pm_runtime_enable(dev); 835 836 /* register context bank devices, which are child nodes: */ 837 ret = devm_of_platform_populate(dev); 838 if (ret) { 839 dev_err(dev, "Failed to populate iommu contexts\n"); 840 return ret; 841 } 842 843 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL, 844 dev_name(dev)); 845 if (ret) { 846 dev_err(dev, "Failed to register iommu in sysfs\n"); 847 return ret; 848 } 849 850 iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops); 851 iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode); 852 853 ret = iommu_device_register(&qcom_iommu->iommu); 854 if (ret) { 855 dev_err(dev, "Failed to register iommu\n"); 856 return ret; 857 } 858 859 bus_set_iommu(&platform_bus_type, &qcom_iommu_ops); 860 861 if (qcom_iommu->local_base) { 862 pm_runtime_get_sync(dev); 863 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS); 864 pm_runtime_put_sync(dev); 865 } 866 867 return 0; 868 } 869 870 static int qcom_iommu_device_remove(struct platform_device *pdev) 871 { 872 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev); 873 874 bus_set_iommu(&platform_bus_type, NULL); 875 876 pm_runtime_force_suspend(&pdev->dev); 877 platform_set_drvdata(pdev, NULL); 878 iommu_device_sysfs_remove(&qcom_iommu->iommu); 879 iommu_device_unregister(&qcom_iommu->iommu); 880 881 return 0; 882 } 883 884 static int __maybe_unused qcom_iommu_resume(struct device *dev) 885 { 886 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev); 887 888 return clk_bulk_prepare_enable(CLK_NUM, qcom_iommu->clks); 889 } 890 891 static int __maybe_unused qcom_iommu_suspend(struct device *dev) 892 { 893 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev); 894 895 clk_bulk_disable_unprepare(CLK_NUM, qcom_iommu->clks); 896 897 return 0; 898 } 899 900 static const struct dev_pm_ops qcom_iommu_pm_ops = { 901 SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL) 902 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 903 pm_runtime_force_resume) 904 }; 905 906 static const struct of_device_id qcom_iommu_of_match[] = { 907 { .compatible = "qcom,msm-iommu-v1" }, 908 { /* sentinel */ } 909 }; 910 911 static struct platform_driver qcom_iommu_driver = { 912 .driver = { 913 .name = "qcom-iommu", 914 .of_match_table = qcom_iommu_of_match, 915 .pm = &qcom_iommu_pm_ops, 916 }, 917 .probe = qcom_iommu_device_probe, 918 .remove = qcom_iommu_device_remove, 919 }; 920 921 static int __init qcom_iommu_init(void) 922 { 923 int ret; 924 925 ret = platform_driver_register(&qcom_iommu_ctx_driver); 926 if (ret) 927 return ret; 928 929 ret = platform_driver_register(&qcom_iommu_driver); 930 if (ret) 931 platform_driver_unregister(&qcom_iommu_ctx_driver); 932 933 return ret; 934 } 935 device_initcall(qcom_iommu_init); 936