1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * IOMMU API for ARM architected SMMU implementations. 4 * 5 * Copyright (C) 2013 ARM Limited 6 * 7 * Author: Will Deacon <will.deacon@arm.com> 8 */ 9 10 #ifndef _ARM_SMMU_H 11 #define _ARM_SMMU_H 12 13 #include <linux/atomic.h> 14 #include <linux/bitfield.h> 15 #include <linux/bits.h> 16 #include <linux/clk.h> 17 #include <linux/device.h> 18 #include <linux/io-64-nonatomic-hi-lo.h> 19 #include <linux/io-pgtable.h> 20 #include <linux/iommu.h> 21 #include <linux/irqreturn.h> 22 #include <linux/mutex.h> 23 #include <linux/spinlock.h> 24 #include <linux/types.h> 25 26 /* Configuration registers */ 27 #define ARM_SMMU_GR0_sCR0 0x0 28 #define ARM_SMMU_sCR0_VMID16EN BIT(31) 29 #define ARM_SMMU_sCR0_BSU GENMASK(15, 14) 30 #define ARM_SMMU_sCR0_FB BIT(13) 31 #define ARM_SMMU_sCR0_PTM BIT(12) 32 #define ARM_SMMU_sCR0_VMIDPNE BIT(11) 33 #define ARM_SMMU_sCR0_USFCFG BIT(10) 34 #define ARM_SMMU_sCR0_GCFGFIE BIT(5) 35 #define ARM_SMMU_sCR0_GCFGFRE BIT(4) 36 #define ARM_SMMU_sCR0_EXIDENABLE BIT(3) 37 #define ARM_SMMU_sCR0_GFIE BIT(2) 38 #define ARM_SMMU_sCR0_GFRE BIT(1) 39 #define ARM_SMMU_sCR0_CLIENTPD BIT(0) 40 41 /* Auxiliary Configuration register */ 42 #define ARM_SMMU_GR0_sACR 0x10 43 44 /* Identification registers */ 45 #define ARM_SMMU_GR0_ID0 0x20 46 #define ARM_SMMU_ID0_S1TS BIT(30) 47 #define ARM_SMMU_ID0_S2TS BIT(29) 48 #define ARM_SMMU_ID0_NTS BIT(28) 49 #define ARM_SMMU_ID0_SMS BIT(27) 50 #define ARM_SMMU_ID0_ATOSNS BIT(26) 51 #define ARM_SMMU_ID0_PTFS_NO_AARCH32 BIT(25) 52 #define ARM_SMMU_ID0_PTFS_NO_AARCH32S BIT(24) 53 #define ARM_SMMU_ID0_NUMIRPT GENMASK(23, 16) 54 #define ARM_SMMU_ID0_CTTW BIT(14) 55 #define ARM_SMMU_ID0_NUMSIDB GENMASK(12, 9) 56 #define ARM_SMMU_ID0_EXIDS BIT(8) 57 #define ARM_SMMU_ID0_NUMSMRG GENMASK(7, 0) 58 59 #define ARM_SMMU_GR0_ID1 0x24 60 #define ARM_SMMU_ID1_PAGESIZE BIT(31) 61 #define ARM_SMMU_ID1_NUMPAGENDXB GENMASK(30, 28) 62 #define ARM_SMMU_ID1_NUMS2CB GENMASK(23, 16) 63 #define ARM_SMMU_ID1_NUMCB GENMASK(7, 0) 64 65 #define ARM_SMMU_GR0_ID2 0x28 66 #define ARM_SMMU_ID2_VMID16 BIT(15) 67 #define ARM_SMMU_ID2_PTFS_64K BIT(14) 68 #define ARM_SMMU_ID2_PTFS_16K BIT(13) 69 #define ARM_SMMU_ID2_PTFS_4K BIT(12) 70 #define ARM_SMMU_ID2_UBS GENMASK(11, 8) 71 #define ARM_SMMU_ID2_OAS GENMASK(7, 4) 72 #define ARM_SMMU_ID2_IAS GENMASK(3, 0) 73 74 #define ARM_SMMU_GR0_ID3 0x2c 75 #define ARM_SMMU_GR0_ID4 0x30 76 #define ARM_SMMU_GR0_ID5 0x34 77 #define ARM_SMMU_GR0_ID6 0x38 78 79 #define ARM_SMMU_GR0_ID7 0x3c 80 #define ARM_SMMU_ID7_MAJOR GENMASK(7, 4) 81 #define ARM_SMMU_ID7_MINOR GENMASK(3, 0) 82 83 #define ARM_SMMU_GR0_sGFSR 0x48 84 #define ARM_SMMU_sGFSR_USF BIT(1) 85 86 #define ARM_SMMU_GR0_sGFSYNR0 0x50 87 #define ARM_SMMU_GR0_sGFSYNR1 0x54 88 #define ARM_SMMU_GR0_sGFSYNR2 0x58 89 90 /* Global TLB invalidation */ 91 #define ARM_SMMU_GR0_TLBIVMID 0x64 92 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 93 #define ARM_SMMU_GR0_TLBIALLH 0x6c 94 #define ARM_SMMU_GR0_sTLBGSYNC 0x70 95 96 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 97 #define ARM_SMMU_sTLBGSTATUS_GSACTIVE BIT(0) 98 99 /* Stream mapping registers */ 100 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) 101 #define ARM_SMMU_SMR_VALID BIT(31) 102 #define ARM_SMMU_SMR_MASK GENMASK(31, 16) 103 #define ARM_SMMU_SMR_ID GENMASK(15, 0) 104 105 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) 106 #define ARM_SMMU_S2CR_PRIVCFG GENMASK(25, 24) 107 enum arm_smmu_s2cr_privcfg { 108 S2CR_PRIVCFG_DEFAULT, 109 S2CR_PRIVCFG_DIPAN, 110 S2CR_PRIVCFG_UNPRIV, 111 S2CR_PRIVCFG_PRIV, 112 }; 113 #define ARM_SMMU_S2CR_TYPE GENMASK(17, 16) 114 enum arm_smmu_s2cr_type { 115 S2CR_TYPE_TRANS, 116 S2CR_TYPE_BYPASS, 117 S2CR_TYPE_FAULT, 118 }; 119 #define ARM_SMMU_S2CR_EXIDVALID BIT(10) 120 #define ARM_SMMU_S2CR_CBNDX GENMASK(7, 0) 121 122 /* Context bank attribute registers */ 123 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) 124 #define ARM_SMMU_CBAR_IRPTNDX GENMASK(31, 24) 125 #define ARM_SMMU_CBAR_TYPE GENMASK(17, 16) 126 enum arm_smmu_cbar_type { 127 CBAR_TYPE_S2_TRANS, 128 CBAR_TYPE_S1_TRANS_S2_BYPASS, 129 CBAR_TYPE_S1_TRANS_S2_FAULT, 130 CBAR_TYPE_S1_TRANS_S2_TRANS, 131 }; 132 #define ARM_SMMU_CBAR_S1_MEMATTR GENMASK(15, 12) 133 #define ARM_SMMU_CBAR_S1_MEMATTR_WB 0xf 134 #define ARM_SMMU_CBAR_S1_BPSHCFG GENMASK(9, 8) 135 #define ARM_SMMU_CBAR_S1_BPSHCFG_NSH 3 136 #define ARM_SMMU_CBAR_VMID GENMASK(7, 0) 137 138 #define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2)) 139 140 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) 141 #define ARM_SMMU_CBA2R_VMID16 GENMASK(31, 16) 142 #define ARM_SMMU_CBA2R_VA64 BIT(0) 143 144 #define ARM_SMMU_CB_SCTLR 0x0 145 #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) 146 #define ARM_SMMU_SCTLR_CFCFG BIT(7) 147 #define ARM_SMMU_SCTLR_CFIE BIT(6) 148 #define ARM_SMMU_SCTLR_CFRE BIT(5) 149 #define ARM_SMMU_SCTLR_E BIT(4) 150 #define ARM_SMMU_SCTLR_AFE BIT(2) 151 #define ARM_SMMU_SCTLR_TRE BIT(1) 152 #define ARM_SMMU_SCTLR_M BIT(0) 153 154 #define ARM_SMMU_CB_ACTLR 0x4 155 156 #define ARM_SMMU_CB_RESUME 0x8 157 #define ARM_SMMU_RESUME_TERMINATE BIT(0) 158 159 #define ARM_SMMU_CB_TCR2 0x10 160 #define ARM_SMMU_TCR2_SEP GENMASK(17, 15) 161 #define ARM_SMMU_TCR2_SEP_UPSTREAM 0x7 162 #define ARM_SMMU_TCR2_AS BIT(4) 163 #define ARM_SMMU_TCR2_PASIZE GENMASK(3, 0) 164 165 #define ARM_SMMU_CB_TTBR0 0x20 166 #define ARM_SMMU_CB_TTBR1 0x28 167 #define ARM_SMMU_TTBRn_ASID GENMASK_ULL(63, 48) 168 169 #define ARM_SMMU_CB_TCR 0x30 170 #define ARM_SMMU_TCR_EAE BIT(31) 171 #define ARM_SMMU_TCR_EPD1 BIT(23) 172 #define ARM_SMMU_TCR_TG0 GENMASK(15, 14) 173 #define ARM_SMMU_TCR_SH0 GENMASK(13, 12) 174 #define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10) 175 #define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8) 176 #define ARM_SMMU_TCR_T0SZ GENMASK(5, 0) 177 178 #define ARM_SMMU_VTCR_RES1 BIT(31) 179 #define ARM_SMMU_VTCR_PS GENMASK(18, 16) 180 #define ARM_SMMU_VTCR_TG0 ARM_SMMU_TCR_TG0 181 #define ARM_SMMU_VTCR_SH0 ARM_SMMU_TCR_SH0 182 #define ARM_SMMU_VTCR_ORGN0 ARM_SMMU_TCR_ORGN0 183 #define ARM_SMMU_VTCR_IRGN0 ARM_SMMU_TCR_IRGN0 184 #define ARM_SMMU_VTCR_SL0 GENMASK(7, 6) 185 #define ARM_SMMU_VTCR_T0SZ ARM_SMMU_TCR_T0SZ 186 187 #define ARM_SMMU_CB_CONTEXTIDR 0x34 188 #define ARM_SMMU_CB_S1_MAIR0 0x38 189 #define ARM_SMMU_CB_S1_MAIR1 0x3c 190 191 #define ARM_SMMU_CB_PAR 0x50 192 #define ARM_SMMU_CB_PAR_F BIT(0) 193 194 #define ARM_SMMU_CB_FSR 0x58 195 #define ARM_SMMU_FSR_MULTI BIT(31) 196 #define ARM_SMMU_FSR_SS BIT(30) 197 #define ARM_SMMU_FSR_UUT BIT(8) 198 #define ARM_SMMU_FSR_ASF BIT(7) 199 #define ARM_SMMU_FSR_TLBLKF BIT(6) 200 #define ARM_SMMU_FSR_TLBMCF BIT(5) 201 #define ARM_SMMU_FSR_EF BIT(4) 202 #define ARM_SMMU_FSR_PF BIT(3) 203 #define ARM_SMMU_FSR_AFF BIT(2) 204 #define ARM_SMMU_FSR_TF BIT(1) 205 206 #define ARM_SMMU_FSR_IGN (ARM_SMMU_FSR_AFF | \ 207 ARM_SMMU_FSR_ASF | \ 208 ARM_SMMU_FSR_TLBMCF | \ 209 ARM_SMMU_FSR_TLBLKF) 210 211 #define ARM_SMMU_FSR_FAULT (ARM_SMMU_FSR_MULTI | \ 212 ARM_SMMU_FSR_SS | \ 213 ARM_SMMU_FSR_UUT | \ 214 ARM_SMMU_FSR_EF | \ 215 ARM_SMMU_FSR_PF | \ 216 ARM_SMMU_FSR_TF | \ 217 ARM_SMMU_FSR_IGN) 218 219 #define ARM_SMMU_CB_FAR 0x60 220 221 #define ARM_SMMU_CB_FSYNR0 0x68 222 #define ARM_SMMU_FSYNR0_WNR BIT(4) 223 224 #define ARM_SMMU_CB_S1_TLBIVA 0x600 225 #define ARM_SMMU_CB_S1_TLBIASID 0x610 226 #define ARM_SMMU_CB_S1_TLBIVAL 0x620 227 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 228 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 229 #define ARM_SMMU_CB_TLBSYNC 0x7f0 230 #define ARM_SMMU_CB_TLBSTATUS 0x7f4 231 #define ARM_SMMU_CB_ATS1PR 0x800 232 233 #define ARM_SMMU_CB_ATSR 0x8f0 234 #define ARM_SMMU_ATSR_ACTIVE BIT(0) 235 236 237 /* Maximum number of context banks per SMMU */ 238 #define ARM_SMMU_MAX_CBS 128 239 240 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ 241 #define TLB_SPIN_COUNT 10 242 243 /* Shared driver definitions */ 244 enum arm_smmu_arch_version { 245 ARM_SMMU_V1, 246 ARM_SMMU_V1_64K, 247 ARM_SMMU_V2, 248 }; 249 250 enum arm_smmu_implementation { 251 GENERIC_SMMU, 252 ARM_MMU500, 253 CAVIUM_SMMUV2, 254 QCOM_SMMUV2, 255 }; 256 257 struct arm_smmu_device { 258 struct device *dev; 259 260 void __iomem *base; 261 unsigned int numpage; 262 unsigned int pgshift; 263 264 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) 265 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) 266 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) 267 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) 268 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) 269 #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5) 270 #define ARM_SMMU_FEAT_VMID16 (1 << 6) 271 #define ARM_SMMU_FEAT_FMT_AARCH64_4K (1 << 7) 272 #define ARM_SMMU_FEAT_FMT_AARCH64_16K (1 << 8) 273 #define ARM_SMMU_FEAT_FMT_AARCH64_64K (1 << 9) 274 #define ARM_SMMU_FEAT_FMT_AARCH32_L (1 << 10) 275 #define ARM_SMMU_FEAT_FMT_AARCH32_S (1 << 11) 276 #define ARM_SMMU_FEAT_EXIDS (1 << 12) 277 u32 features; 278 279 enum arm_smmu_arch_version version; 280 enum arm_smmu_implementation model; 281 const struct arm_smmu_impl *impl; 282 283 u32 num_context_banks; 284 u32 num_s2_context_banks; 285 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); 286 struct arm_smmu_cb *cbs; 287 atomic_t irptndx; 288 289 u32 num_mapping_groups; 290 u16 streamid_mask; 291 u16 smr_mask_mask; 292 struct arm_smmu_smr *smrs; 293 struct arm_smmu_s2cr *s2crs; 294 struct mutex stream_map_mutex; 295 296 unsigned long va_size; 297 unsigned long ipa_size; 298 unsigned long pa_size; 299 unsigned long pgsize_bitmap; 300 301 u32 num_global_irqs; 302 u32 num_context_irqs; 303 unsigned int *irqs; 304 struct clk_bulk_data *clks; 305 int num_clks; 306 307 spinlock_t global_sync_lock; 308 309 /* IOMMU core code handle */ 310 struct iommu_device iommu; 311 }; 312 313 enum arm_smmu_context_fmt { 314 ARM_SMMU_CTX_FMT_NONE, 315 ARM_SMMU_CTX_FMT_AARCH64, 316 ARM_SMMU_CTX_FMT_AARCH32_L, 317 ARM_SMMU_CTX_FMT_AARCH32_S, 318 }; 319 320 struct arm_smmu_cfg { 321 u8 cbndx; 322 u8 irptndx; 323 union { 324 u16 asid; 325 u16 vmid; 326 }; 327 enum arm_smmu_cbar_type cbar; 328 enum arm_smmu_context_fmt fmt; 329 }; 330 #define ARM_SMMU_INVALID_IRPTNDX 0xff 331 332 enum arm_smmu_domain_stage { 333 ARM_SMMU_DOMAIN_S1 = 0, 334 ARM_SMMU_DOMAIN_S2, 335 ARM_SMMU_DOMAIN_NESTED, 336 ARM_SMMU_DOMAIN_BYPASS, 337 }; 338 339 struct arm_smmu_domain { 340 struct arm_smmu_device *smmu; 341 struct io_pgtable_ops *pgtbl_ops; 342 const struct iommu_flush_ops *flush_ops; 343 struct arm_smmu_cfg cfg; 344 enum arm_smmu_domain_stage stage; 345 bool non_strict; 346 struct mutex init_mutex; /* Protects smmu pointer */ 347 spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */ 348 struct iommu_domain domain; 349 }; 350 351 static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) 352 { 353 return ARM_SMMU_TCR_EPD1 | 354 FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | 355 FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | 356 FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | 357 FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | 358 FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); 359 } 360 361 static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg) 362 { 363 return FIELD_PREP(ARM_SMMU_TCR2_PASIZE, cfg->arm_lpae_s1_cfg.tcr.ips) | 364 FIELD_PREP(ARM_SMMU_TCR2_SEP, ARM_SMMU_TCR2_SEP_UPSTREAM); 365 } 366 367 static inline u32 arm_smmu_lpae_vtcr(struct io_pgtable_cfg *cfg) 368 { 369 return ARM_SMMU_VTCR_RES1 | 370 FIELD_PREP(ARM_SMMU_VTCR_PS, cfg->arm_lpae_s2_cfg.vtcr.ps) | 371 FIELD_PREP(ARM_SMMU_VTCR_TG0, cfg->arm_lpae_s2_cfg.vtcr.tg) | 372 FIELD_PREP(ARM_SMMU_VTCR_SH0, cfg->arm_lpae_s2_cfg.vtcr.sh) | 373 FIELD_PREP(ARM_SMMU_VTCR_ORGN0, cfg->arm_lpae_s2_cfg.vtcr.orgn) | 374 FIELD_PREP(ARM_SMMU_VTCR_IRGN0, cfg->arm_lpae_s2_cfg.vtcr.irgn) | 375 FIELD_PREP(ARM_SMMU_VTCR_SL0, cfg->arm_lpae_s2_cfg.vtcr.sl) | 376 FIELD_PREP(ARM_SMMU_VTCR_T0SZ, cfg->arm_lpae_s2_cfg.vtcr.tsz); 377 } 378 379 /* Implementation details, yay! */ 380 struct arm_smmu_impl { 381 u32 (*read_reg)(struct arm_smmu_device *smmu, int page, int offset); 382 void (*write_reg)(struct arm_smmu_device *smmu, int page, int offset, 383 u32 val); 384 u64 (*read_reg64)(struct arm_smmu_device *smmu, int page, int offset); 385 void (*write_reg64)(struct arm_smmu_device *smmu, int page, int offset, 386 u64 val); 387 int (*cfg_probe)(struct arm_smmu_device *smmu); 388 int (*reset)(struct arm_smmu_device *smmu); 389 int (*init_context)(struct arm_smmu_domain *smmu_domain); 390 void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync, 391 int status); 392 int (*def_domain_type)(struct device *dev); 393 irqreturn_t (*global_fault)(int irq, void *dev); 394 irqreturn_t (*context_fault)(int irq, void *dev); 395 }; 396 397 static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n) 398 { 399 return smmu->base + (n << smmu->pgshift); 400 } 401 402 static inline u32 arm_smmu_readl(struct arm_smmu_device *smmu, int page, int offset) 403 { 404 if (smmu->impl && unlikely(smmu->impl->read_reg)) 405 return smmu->impl->read_reg(smmu, page, offset); 406 return readl_relaxed(arm_smmu_page(smmu, page) + offset); 407 } 408 409 static inline void arm_smmu_writel(struct arm_smmu_device *smmu, int page, 410 int offset, u32 val) 411 { 412 if (smmu->impl && unlikely(smmu->impl->write_reg)) 413 smmu->impl->write_reg(smmu, page, offset, val); 414 else 415 writel_relaxed(val, arm_smmu_page(smmu, page) + offset); 416 } 417 418 static inline u64 arm_smmu_readq(struct arm_smmu_device *smmu, int page, int offset) 419 { 420 if (smmu->impl && unlikely(smmu->impl->read_reg64)) 421 return smmu->impl->read_reg64(smmu, page, offset); 422 return readq_relaxed(arm_smmu_page(smmu, page) + offset); 423 } 424 425 static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, 426 int offset, u64 val) 427 { 428 if (smmu->impl && unlikely(smmu->impl->write_reg64)) 429 smmu->impl->write_reg64(smmu, page, offset, val); 430 else 431 writeq_relaxed(val, arm_smmu_page(smmu, page) + offset); 432 } 433 434 #define ARM_SMMU_GR0 0 435 #define ARM_SMMU_GR1 1 436 #define ARM_SMMU_CB(s, n) ((s)->numpage + (n)) 437 438 #define arm_smmu_gr0_read(s, o) \ 439 arm_smmu_readl((s), ARM_SMMU_GR0, (o)) 440 #define arm_smmu_gr0_write(s, o, v) \ 441 arm_smmu_writel((s), ARM_SMMU_GR0, (o), (v)) 442 443 #define arm_smmu_gr1_read(s, o) \ 444 arm_smmu_readl((s), ARM_SMMU_GR1, (o)) 445 #define arm_smmu_gr1_write(s, o, v) \ 446 arm_smmu_writel((s), ARM_SMMU_GR1, (o), (v)) 447 448 #define arm_smmu_cb_read(s, n, o) \ 449 arm_smmu_readl((s), ARM_SMMU_CB((s), (n)), (o)) 450 #define arm_smmu_cb_write(s, n, o, v) \ 451 arm_smmu_writel((s), ARM_SMMU_CB((s), (n)), (o), (v)) 452 #define arm_smmu_cb_readq(s, n, o) \ 453 arm_smmu_readq((s), ARM_SMMU_CB((s), (n)), (o)) 454 #define arm_smmu_cb_writeq(s, n, o, v) \ 455 arm_smmu_writeq((s), ARM_SMMU_CB((s), (n)), (o), (v)) 456 457 struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); 458 struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); 459 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); 460 461 int arm_mmu500_reset(struct arm_smmu_device *smmu); 462 463 #endif /* _ARM_SMMU_H */ 464