1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * IOMMU API for ARM architected SMMU implementations.
4  *
5  * Copyright (C) 2013 ARM Limited
6  *
7  * Author: Will Deacon <will.deacon@arm.com>
8  */
9 
10 #ifndef _ARM_SMMU_H
11 #define _ARM_SMMU_H
12 
13 #include <linux/atomic.h>
14 #include <linux/bitfield.h>
15 #include <linux/bits.h>
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/io-64-nonatomic-hi-lo.h>
19 #include <linux/io-pgtable.h>
20 #include <linux/iommu.h>
21 #include <linux/irqreturn.h>
22 #include <linux/mutex.h>
23 #include <linux/spinlock.h>
24 #include <linux/types.h>
25 
26 /* Configuration registers */
27 #define ARM_SMMU_GR0_sCR0		0x0
28 #define ARM_SMMU_sCR0_VMID16EN		BIT(31)
29 #define ARM_SMMU_sCR0_BSU		GENMASK(15, 14)
30 #define ARM_SMMU_sCR0_FB		BIT(13)
31 #define ARM_SMMU_sCR0_PTM		BIT(12)
32 #define ARM_SMMU_sCR0_VMIDPNE		BIT(11)
33 #define ARM_SMMU_sCR0_USFCFG		BIT(10)
34 #define ARM_SMMU_sCR0_GCFGFIE		BIT(5)
35 #define ARM_SMMU_sCR0_GCFGFRE		BIT(4)
36 #define ARM_SMMU_sCR0_EXIDENABLE	BIT(3)
37 #define ARM_SMMU_sCR0_GFIE		BIT(2)
38 #define ARM_SMMU_sCR0_GFRE		BIT(1)
39 #define ARM_SMMU_sCR0_CLIENTPD		BIT(0)
40 
41 /* Auxiliary Configuration register */
42 #define ARM_SMMU_GR0_sACR		0x10
43 
44 /* Identification registers */
45 #define ARM_SMMU_GR0_ID0		0x20
46 #define ARM_SMMU_ID0_S1TS		BIT(30)
47 #define ARM_SMMU_ID0_S2TS		BIT(29)
48 #define ARM_SMMU_ID0_NTS		BIT(28)
49 #define ARM_SMMU_ID0_SMS		BIT(27)
50 #define ARM_SMMU_ID0_ATOSNS		BIT(26)
51 #define ARM_SMMU_ID0_PTFS_NO_AARCH32	BIT(25)
52 #define ARM_SMMU_ID0_PTFS_NO_AARCH32S	BIT(24)
53 #define ARM_SMMU_ID0_NUMIRPT		GENMASK(23, 16)
54 #define ARM_SMMU_ID0_CTTW		BIT(14)
55 #define ARM_SMMU_ID0_NUMSIDB		GENMASK(12, 9)
56 #define ARM_SMMU_ID0_EXIDS		BIT(8)
57 #define ARM_SMMU_ID0_NUMSMRG		GENMASK(7, 0)
58 
59 #define ARM_SMMU_GR0_ID1		0x24
60 #define ARM_SMMU_ID1_PAGESIZE		BIT(31)
61 #define ARM_SMMU_ID1_NUMPAGENDXB	GENMASK(30, 28)
62 #define ARM_SMMU_ID1_NUMS2CB		GENMASK(23, 16)
63 #define ARM_SMMU_ID1_NUMCB		GENMASK(7, 0)
64 
65 #define ARM_SMMU_GR0_ID2		0x28
66 #define ARM_SMMU_ID2_VMID16		BIT(15)
67 #define ARM_SMMU_ID2_PTFS_64K		BIT(14)
68 #define ARM_SMMU_ID2_PTFS_16K		BIT(13)
69 #define ARM_SMMU_ID2_PTFS_4K		BIT(12)
70 #define ARM_SMMU_ID2_UBS		GENMASK(11, 8)
71 #define ARM_SMMU_ID2_OAS		GENMASK(7, 4)
72 #define ARM_SMMU_ID2_IAS		GENMASK(3, 0)
73 
74 #define ARM_SMMU_GR0_ID3		0x2c
75 #define ARM_SMMU_GR0_ID4		0x30
76 #define ARM_SMMU_GR0_ID5		0x34
77 #define ARM_SMMU_GR0_ID6		0x38
78 
79 #define ARM_SMMU_GR0_ID7		0x3c
80 #define ARM_SMMU_ID7_MAJOR		GENMASK(7, 4)
81 #define ARM_SMMU_ID7_MINOR		GENMASK(3, 0)
82 
83 #define ARM_SMMU_GR0_sGFSR		0x48
84 #define ARM_SMMU_sGFSR_USF		BIT(1)
85 
86 #define ARM_SMMU_GR0_sGFSYNR0		0x50
87 #define ARM_SMMU_GR0_sGFSYNR1		0x54
88 #define ARM_SMMU_GR0_sGFSYNR2		0x58
89 
90 /* Global TLB invalidation */
91 #define ARM_SMMU_GR0_TLBIVMID		0x64
92 #define ARM_SMMU_GR0_TLBIALLNSNH	0x68
93 #define ARM_SMMU_GR0_TLBIALLH		0x6c
94 #define ARM_SMMU_GR0_sTLBGSYNC		0x70
95 
96 #define ARM_SMMU_GR0_sTLBGSTATUS	0x74
97 #define ARM_SMMU_sTLBGSTATUS_GSACTIVE	BIT(0)
98 
99 /* Stream mapping registers */
100 #define ARM_SMMU_GR0_SMR(n)		(0x800 + ((n) << 2))
101 #define ARM_SMMU_SMR_VALID		BIT(31)
102 #define ARM_SMMU_SMR_MASK		GENMASK(31, 16)
103 #define ARM_SMMU_SMR_ID			GENMASK(15, 0)
104 
105 #define ARM_SMMU_GR0_S2CR(n)		(0xc00 + ((n) << 2))
106 #define ARM_SMMU_S2CR_PRIVCFG		GENMASK(25, 24)
107 enum arm_smmu_s2cr_privcfg {
108 	S2CR_PRIVCFG_DEFAULT,
109 	S2CR_PRIVCFG_DIPAN,
110 	S2CR_PRIVCFG_UNPRIV,
111 	S2CR_PRIVCFG_PRIV,
112 };
113 #define ARM_SMMU_S2CR_TYPE		GENMASK(17, 16)
114 enum arm_smmu_s2cr_type {
115 	S2CR_TYPE_TRANS,
116 	S2CR_TYPE_BYPASS,
117 	S2CR_TYPE_FAULT,
118 };
119 #define ARM_SMMU_S2CR_EXIDVALID		BIT(10)
120 #define ARM_SMMU_S2CR_CBNDX		GENMASK(7, 0)
121 
122 /* Context bank attribute registers */
123 #define ARM_SMMU_GR1_CBAR(n)		(0x0 + ((n) << 2))
124 #define ARM_SMMU_CBAR_IRPTNDX		GENMASK(31, 24)
125 #define ARM_SMMU_CBAR_TYPE		GENMASK(17, 16)
126 enum arm_smmu_cbar_type {
127 	CBAR_TYPE_S2_TRANS,
128 	CBAR_TYPE_S1_TRANS_S2_BYPASS,
129 	CBAR_TYPE_S1_TRANS_S2_FAULT,
130 	CBAR_TYPE_S1_TRANS_S2_TRANS,
131 };
132 #define ARM_SMMU_CBAR_S1_MEMATTR	GENMASK(15, 12)
133 #define ARM_SMMU_CBAR_S1_MEMATTR_WB	0xf
134 #define ARM_SMMU_CBAR_S1_BPSHCFG	GENMASK(9, 8)
135 #define ARM_SMMU_CBAR_S1_BPSHCFG_NSH	3
136 #define ARM_SMMU_CBAR_VMID		GENMASK(7, 0)
137 
138 #define ARM_SMMU_GR1_CBFRSYNRA(n)	(0x400 + ((n) << 2))
139 
140 #define ARM_SMMU_GR1_CBA2R(n)		(0x800 + ((n) << 2))
141 #define ARM_SMMU_CBA2R_VMID16		GENMASK(31, 16)
142 #define ARM_SMMU_CBA2R_VA64		BIT(0)
143 
144 #define ARM_SMMU_CB_SCTLR		0x0
145 #define ARM_SMMU_SCTLR_S1_ASIDPNE	BIT(12)
146 #define ARM_SMMU_SCTLR_CFCFG		BIT(7)
147 #define ARM_SMMU_SCTLR_HUPCF		BIT(8)
148 #define ARM_SMMU_SCTLR_CFIE		BIT(6)
149 #define ARM_SMMU_SCTLR_CFRE		BIT(5)
150 #define ARM_SMMU_SCTLR_E		BIT(4)
151 #define ARM_SMMU_SCTLR_AFE		BIT(2)
152 #define ARM_SMMU_SCTLR_TRE		BIT(1)
153 #define ARM_SMMU_SCTLR_M		BIT(0)
154 
155 #define ARM_SMMU_CB_ACTLR		0x4
156 
157 #define ARM_SMMU_CB_RESUME		0x8
158 #define ARM_SMMU_RESUME_TERMINATE	BIT(0)
159 
160 #define ARM_SMMU_CB_TCR2		0x10
161 #define ARM_SMMU_TCR2_SEP		GENMASK(17, 15)
162 #define ARM_SMMU_TCR2_SEP_UPSTREAM	0x7
163 #define ARM_SMMU_TCR2_AS		BIT(4)
164 #define ARM_SMMU_TCR2_PASIZE		GENMASK(3, 0)
165 
166 #define ARM_SMMU_CB_TTBR0		0x20
167 #define ARM_SMMU_CB_TTBR1		0x28
168 #define ARM_SMMU_TTBRn_ASID		GENMASK_ULL(63, 48)
169 
170 #define ARM_SMMU_CB_TCR			0x30
171 #define ARM_SMMU_TCR_EAE		BIT(31)
172 #define ARM_SMMU_TCR_EPD1		BIT(23)
173 #define ARM_SMMU_TCR_A1			BIT(22)
174 #define ARM_SMMU_TCR_TG0		GENMASK(15, 14)
175 #define ARM_SMMU_TCR_SH0		GENMASK(13, 12)
176 #define ARM_SMMU_TCR_ORGN0		GENMASK(11, 10)
177 #define ARM_SMMU_TCR_IRGN0		GENMASK(9, 8)
178 #define ARM_SMMU_TCR_EPD0		BIT(7)
179 #define ARM_SMMU_TCR_T0SZ		GENMASK(5, 0)
180 
181 #define ARM_SMMU_VTCR_RES1		BIT(31)
182 #define ARM_SMMU_VTCR_PS		GENMASK(18, 16)
183 #define ARM_SMMU_VTCR_TG0		ARM_SMMU_TCR_TG0
184 #define ARM_SMMU_VTCR_SH0		ARM_SMMU_TCR_SH0
185 #define ARM_SMMU_VTCR_ORGN0		ARM_SMMU_TCR_ORGN0
186 #define ARM_SMMU_VTCR_IRGN0		ARM_SMMU_TCR_IRGN0
187 #define ARM_SMMU_VTCR_SL0		GENMASK(7, 6)
188 #define ARM_SMMU_VTCR_T0SZ		ARM_SMMU_TCR_T0SZ
189 
190 #define ARM_SMMU_CB_CONTEXTIDR		0x34
191 #define ARM_SMMU_CB_S1_MAIR0		0x38
192 #define ARM_SMMU_CB_S1_MAIR1		0x3c
193 
194 #define ARM_SMMU_CB_PAR			0x50
195 #define ARM_SMMU_CB_PAR_F		BIT(0)
196 
197 #define ARM_SMMU_CB_FSR			0x58
198 #define ARM_SMMU_FSR_MULTI		BIT(31)
199 #define ARM_SMMU_FSR_SS			BIT(30)
200 #define ARM_SMMU_FSR_UUT		BIT(8)
201 #define ARM_SMMU_FSR_ASF		BIT(7)
202 #define ARM_SMMU_FSR_TLBLKF		BIT(6)
203 #define ARM_SMMU_FSR_TLBMCF		BIT(5)
204 #define ARM_SMMU_FSR_EF			BIT(4)
205 #define ARM_SMMU_FSR_PF			BIT(3)
206 #define ARM_SMMU_FSR_AFF		BIT(2)
207 #define ARM_SMMU_FSR_TF			BIT(1)
208 
209 #define ARM_SMMU_FSR_IGN		(ARM_SMMU_FSR_AFF |		\
210 					 ARM_SMMU_FSR_ASF |		\
211 					 ARM_SMMU_FSR_TLBMCF |		\
212 					 ARM_SMMU_FSR_TLBLKF)
213 
214 #define ARM_SMMU_FSR_FAULT		(ARM_SMMU_FSR_MULTI |		\
215 					 ARM_SMMU_FSR_SS |		\
216 					 ARM_SMMU_FSR_UUT |		\
217 					 ARM_SMMU_FSR_EF |		\
218 					 ARM_SMMU_FSR_PF |		\
219 					 ARM_SMMU_FSR_TF |		\
220 					 ARM_SMMU_FSR_IGN)
221 
222 #define ARM_SMMU_CB_FAR			0x60
223 
224 #define ARM_SMMU_CB_FSYNR0		0x68
225 #define ARM_SMMU_FSYNR0_WNR		BIT(4)
226 
227 #define ARM_SMMU_CB_FSYNR1		0x6c
228 
229 #define ARM_SMMU_CB_S1_TLBIVA		0x600
230 #define ARM_SMMU_CB_S1_TLBIASID		0x610
231 #define ARM_SMMU_CB_S1_TLBIVAL		0x620
232 #define ARM_SMMU_CB_S2_TLBIIPAS2	0x630
233 #define ARM_SMMU_CB_S2_TLBIIPAS2L	0x638
234 #define ARM_SMMU_CB_TLBSYNC		0x7f0
235 #define ARM_SMMU_CB_TLBSTATUS		0x7f4
236 #define ARM_SMMU_CB_ATS1PR		0x800
237 
238 #define ARM_SMMU_CB_ATSR		0x8f0
239 #define ARM_SMMU_ATSR_ACTIVE		BIT(0)
240 
241 
242 /* Maximum number of context banks per SMMU */
243 #define ARM_SMMU_MAX_CBS		128
244 
245 #define TLB_LOOP_TIMEOUT		1000000	/* 1s! */
246 #define TLB_SPIN_COUNT			10
247 
248 /* Shared driver definitions */
249 enum arm_smmu_arch_version {
250 	ARM_SMMU_V1,
251 	ARM_SMMU_V1_64K,
252 	ARM_SMMU_V2,
253 };
254 
255 enum arm_smmu_implementation {
256 	GENERIC_SMMU,
257 	ARM_MMU500,
258 	CAVIUM_SMMUV2,
259 	QCOM_SMMUV2,
260 };
261 
262 struct arm_smmu_s2cr {
263 	struct iommu_group		*group;
264 	int				count;
265 	enum arm_smmu_s2cr_type		type;
266 	enum arm_smmu_s2cr_privcfg	privcfg;
267 	u8				cbndx;
268 };
269 
270 struct arm_smmu_smr {
271 	u16				mask;
272 	u16				id;
273 	bool				valid;
274 	bool				pinned;
275 };
276 
277 struct arm_smmu_device {
278 	struct device			*dev;
279 
280 	void __iomem			*base;
281 	phys_addr_t			ioaddr;
282 	unsigned int			numpage;
283 	unsigned int			pgshift;
284 
285 #define ARM_SMMU_FEAT_COHERENT_WALK	(1 << 0)
286 #define ARM_SMMU_FEAT_STREAM_MATCH	(1 << 1)
287 #define ARM_SMMU_FEAT_TRANS_S1		(1 << 2)
288 #define ARM_SMMU_FEAT_TRANS_S2		(1 << 3)
289 #define ARM_SMMU_FEAT_TRANS_NESTED	(1 << 4)
290 #define ARM_SMMU_FEAT_TRANS_OPS		(1 << 5)
291 #define ARM_SMMU_FEAT_VMID16		(1 << 6)
292 #define ARM_SMMU_FEAT_FMT_AARCH64_4K	(1 << 7)
293 #define ARM_SMMU_FEAT_FMT_AARCH64_16K	(1 << 8)
294 #define ARM_SMMU_FEAT_FMT_AARCH64_64K	(1 << 9)
295 #define ARM_SMMU_FEAT_FMT_AARCH32_L	(1 << 10)
296 #define ARM_SMMU_FEAT_FMT_AARCH32_S	(1 << 11)
297 #define ARM_SMMU_FEAT_EXIDS		(1 << 12)
298 	u32				features;
299 
300 	enum arm_smmu_arch_version	version;
301 	enum arm_smmu_implementation	model;
302 	const struct arm_smmu_impl	*impl;
303 
304 	u32				num_context_banks;
305 	u32				num_s2_context_banks;
306 	DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
307 	struct arm_smmu_cb		*cbs;
308 	atomic_t			irptndx;
309 
310 	u32				num_mapping_groups;
311 	u16				streamid_mask;
312 	u16				smr_mask_mask;
313 	struct arm_smmu_smr		*smrs;
314 	struct arm_smmu_s2cr		*s2crs;
315 	struct mutex			stream_map_mutex;
316 
317 	unsigned long			va_size;
318 	unsigned long			ipa_size;
319 	unsigned long			pa_size;
320 	unsigned long			pgsize_bitmap;
321 
322 	int				num_context_irqs;
323 	int				num_clks;
324 	unsigned int			*irqs;
325 	struct clk_bulk_data		*clks;
326 
327 	spinlock_t			global_sync_lock;
328 
329 	/* IOMMU core code handle */
330 	struct iommu_device		iommu;
331 };
332 
333 enum arm_smmu_context_fmt {
334 	ARM_SMMU_CTX_FMT_NONE,
335 	ARM_SMMU_CTX_FMT_AARCH64,
336 	ARM_SMMU_CTX_FMT_AARCH32_L,
337 	ARM_SMMU_CTX_FMT_AARCH32_S,
338 };
339 
340 struct arm_smmu_cfg {
341 	u8				cbndx;
342 	u8				irptndx;
343 	union {
344 		u16			asid;
345 		u16			vmid;
346 	};
347 	enum arm_smmu_cbar_type		cbar;
348 	enum arm_smmu_context_fmt	fmt;
349 	bool				flush_walk_prefer_tlbiasid;
350 };
351 #define ARM_SMMU_INVALID_IRPTNDX	0xff
352 
353 struct arm_smmu_cb {
354 	u64				ttbr[2];
355 	u32				tcr[2];
356 	u32				mair[2];
357 	struct arm_smmu_cfg		*cfg;
358 };
359 
360 enum arm_smmu_domain_stage {
361 	ARM_SMMU_DOMAIN_S1 = 0,
362 	ARM_SMMU_DOMAIN_S2,
363 	ARM_SMMU_DOMAIN_NESTED,
364 	ARM_SMMU_DOMAIN_BYPASS,
365 };
366 
367 struct arm_smmu_domain {
368 	struct arm_smmu_device		*smmu;
369 	struct io_pgtable_ops		*pgtbl_ops;
370 	unsigned long			pgtbl_quirks;
371 	const struct iommu_flush_ops	*flush_ops;
372 	struct arm_smmu_cfg		cfg;
373 	enum arm_smmu_domain_stage	stage;
374 	struct mutex			init_mutex; /* Protects smmu pointer */
375 	spinlock_t			cb_lock; /* Serialises ATS1* ops and TLB syncs */
376 	struct iommu_domain		domain;
377 };
378 
379 struct arm_smmu_master_cfg {
380 	struct arm_smmu_device		*smmu;
381 	s16				smendx[];
382 };
383 
384 static inline u32 arm_smmu_lpae_tcr(const struct io_pgtable_cfg *cfg)
385 {
386 	u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
387 		FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
388 		FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
389 		FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
390 		FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
391 
392        /*
393 	* When TTBR1 is selected shift the TCR fields by 16 bits and disable
394 	* translation in TTBR0
395 	*/
396 	if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
397 		tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1;
398 		tcr |= ARM_SMMU_TCR_EPD0;
399 	} else
400 		tcr |= ARM_SMMU_TCR_EPD1;
401 
402 	return tcr;
403 }
404 
405 static inline u32 arm_smmu_lpae_tcr2(const struct io_pgtable_cfg *cfg)
406 {
407 	return FIELD_PREP(ARM_SMMU_TCR2_PASIZE, cfg->arm_lpae_s1_cfg.tcr.ips) |
408 	       FIELD_PREP(ARM_SMMU_TCR2_SEP, ARM_SMMU_TCR2_SEP_UPSTREAM);
409 }
410 
411 static inline u32 arm_smmu_lpae_vtcr(const struct io_pgtable_cfg *cfg)
412 {
413 	return ARM_SMMU_VTCR_RES1 |
414 	       FIELD_PREP(ARM_SMMU_VTCR_PS, cfg->arm_lpae_s2_cfg.vtcr.ps) |
415 	       FIELD_PREP(ARM_SMMU_VTCR_TG0, cfg->arm_lpae_s2_cfg.vtcr.tg) |
416 	       FIELD_PREP(ARM_SMMU_VTCR_SH0, cfg->arm_lpae_s2_cfg.vtcr.sh) |
417 	       FIELD_PREP(ARM_SMMU_VTCR_ORGN0, cfg->arm_lpae_s2_cfg.vtcr.orgn) |
418 	       FIELD_PREP(ARM_SMMU_VTCR_IRGN0, cfg->arm_lpae_s2_cfg.vtcr.irgn) |
419 	       FIELD_PREP(ARM_SMMU_VTCR_SL0, cfg->arm_lpae_s2_cfg.vtcr.sl) |
420 	       FIELD_PREP(ARM_SMMU_VTCR_T0SZ, cfg->arm_lpae_s2_cfg.vtcr.tsz);
421 }
422 
423 /* Implementation details, yay! */
424 struct arm_smmu_impl {
425 	u32 (*read_reg)(struct arm_smmu_device *smmu, int page, int offset);
426 	void (*write_reg)(struct arm_smmu_device *smmu, int page, int offset,
427 			  u32 val);
428 	u64 (*read_reg64)(struct arm_smmu_device *smmu, int page, int offset);
429 	void (*write_reg64)(struct arm_smmu_device *smmu, int page, int offset,
430 			    u64 val);
431 	int (*cfg_probe)(struct arm_smmu_device *smmu);
432 	int (*reset)(struct arm_smmu_device *smmu);
433 	int (*init_context)(struct arm_smmu_domain *smmu_domain,
434 			struct io_pgtable_cfg *cfg, struct device *dev);
435 	void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync,
436 			 int status);
437 	int (*def_domain_type)(struct device *dev);
438 	irqreturn_t (*global_fault)(int irq, void *dev);
439 	irqreturn_t (*context_fault)(int irq, void *dev);
440 	int (*alloc_context_bank)(struct arm_smmu_domain *smmu_domain,
441 				  struct arm_smmu_device *smmu,
442 				  struct device *dev, int start);
443 	void (*write_s2cr)(struct arm_smmu_device *smmu, int idx);
444 	void (*write_sctlr)(struct arm_smmu_device *smmu, int idx, u32 reg);
445 	void (*probe_finalize)(struct arm_smmu_device *smmu, struct device *dev);
446 };
447 
448 #define INVALID_SMENDX			-1
449 #define cfg_smendx(cfg, fw, i) \
450 	(i >= fw->num_ids ? INVALID_SMENDX : cfg->smendx[i])
451 #define for_each_cfg_sme(cfg, fw, i, idx) \
452 	for (i = 0; idx = cfg_smendx(cfg, fw, i), i < fw->num_ids; ++i)
453 
454 static inline int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
455 {
456 	int idx;
457 
458 	do {
459 		idx = find_next_zero_bit(map, end, start);
460 		if (idx == end)
461 			return -ENOSPC;
462 	} while (test_and_set_bit(idx, map));
463 
464 	return idx;
465 }
466 
467 static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)
468 {
469 	return smmu->base + (n << smmu->pgshift);
470 }
471 
472 static inline u32 arm_smmu_readl(struct arm_smmu_device *smmu, int page, int offset)
473 {
474 	if (smmu->impl && unlikely(smmu->impl->read_reg))
475 		return smmu->impl->read_reg(smmu, page, offset);
476 	return readl_relaxed(arm_smmu_page(smmu, page) + offset);
477 }
478 
479 static inline void arm_smmu_writel(struct arm_smmu_device *smmu, int page,
480 				   int offset, u32 val)
481 {
482 	if (smmu->impl && unlikely(smmu->impl->write_reg))
483 		smmu->impl->write_reg(smmu, page, offset, val);
484 	else
485 		writel_relaxed(val, arm_smmu_page(smmu, page) + offset);
486 }
487 
488 static inline u64 arm_smmu_readq(struct arm_smmu_device *smmu, int page, int offset)
489 {
490 	if (smmu->impl && unlikely(smmu->impl->read_reg64))
491 		return smmu->impl->read_reg64(smmu, page, offset);
492 	return readq_relaxed(arm_smmu_page(smmu, page) + offset);
493 }
494 
495 static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
496 				   int offset, u64 val)
497 {
498 	if (smmu->impl && unlikely(smmu->impl->write_reg64))
499 		smmu->impl->write_reg64(smmu, page, offset, val);
500 	else
501 		writeq_relaxed(val, arm_smmu_page(smmu, page) + offset);
502 }
503 
504 #define ARM_SMMU_GR0		0
505 #define ARM_SMMU_GR1		1
506 #define ARM_SMMU_CB(s, n)	((s)->numpage + (n))
507 
508 #define arm_smmu_gr0_read(s, o)		\
509 	arm_smmu_readl((s), ARM_SMMU_GR0, (o))
510 #define arm_smmu_gr0_write(s, o, v)	\
511 	arm_smmu_writel((s), ARM_SMMU_GR0, (o), (v))
512 
513 #define arm_smmu_gr1_read(s, o)		\
514 	arm_smmu_readl((s), ARM_SMMU_GR1, (o))
515 #define arm_smmu_gr1_write(s, o, v)	\
516 	arm_smmu_writel((s), ARM_SMMU_GR1, (o), (v))
517 
518 #define arm_smmu_cb_read(s, n, o)	\
519 	arm_smmu_readl((s), ARM_SMMU_CB((s), (n)), (o))
520 #define arm_smmu_cb_write(s, n, o, v)	\
521 	arm_smmu_writel((s), ARM_SMMU_CB((s), (n)), (o), (v))
522 #define arm_smmu_cb_readq(s, n, o)	\
523 	arm_smmu_readq((s), ARM_SMMU_CB((s), (n)), (o))
524 #define arm_smmu_cb_writeq(s, n, o, v)	\
525 	arm_smmu_writeq((s), ARM_SMMU_CB((s), (n)), (o), (v))
526 
527 struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu);
528 struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu);
529 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
530 
531 void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
532 int arm_mmu500_reset(struct arm_smmu_device *smmu);
533 
534 #endif /* _ARM_SMMU_H */
535