1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/adreno-smmu-priv.h> 7 #include <linux/of_device.h> 8 #include <linux/qcom_scm.h> 9 10 #include "arm-smmu.h" 11 12 struct qcom_smmu { 13 struct arm_smmu_device smmu; 14 bool bypass_quirk; 15 u8 bypass_cbndx; 16 }; 17 18 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) 19 { 20 return container_of(smmu, struct qcom_smmu, smmu); 21 } 22 23 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, 24 u32 reg) 25 { 26 /* 27 * On the GPU device we want to process subsequent transactions after a 28 * fault to keep the GPU from hanging 29 */ 30 reg |= ARM_SMMU_SCTLR_HUPCF; 31 32 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); 33 } 34 35 #define QCOM_ADRENO_SMMU_GPU_SID 0 36 37 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) 38 { 39 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 40 int i; 41 42 /* 43 * The GPU will always use SID 0 so that is a handy way to uniquely 44 * identify it and configure it for per-instance pagetables 45 */ 46 for (i = 0; i < fwspec->num_ids; i++) { 47 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); 48 49 if (sid == QCOM_ADRENO_SMMU_GPU_SID) 50 return true; 51 } 52 53 return false; 54 } 55 56 static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( 57 const void *cookie) 58 { 59 struct arm_smmu_domain *smmu_domain = (void *)cookie; 60 struct io_pgtable *pgtable = 61 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 62 return &pgtable->cfg; 63 } 64 65 /* 66 * Local implementation to configure TTBR0 with the specified pagetable config. 67 * The GPU driver will call this to enable TTBR0 when per-instance pagetables 68 * are active 69 */ 70 71 static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, 72 const struct io_pgtable_cfg *pgtbl_cfg) 73 { 74 struct arm_smmu_domain *smmu_domain = (void *)cookie; 75 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 76 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 77 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; 78 79 /* The domain must have split pagetables already enabled */ 80 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) 81 return -EINVAL; 82 83 /* If the pagetable config is NULL, disable TTBR0 */ 84 if (!pgtbl_cfg) { 85 /* Do nothing if it is already disabled */ 86 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 87 return -EINVAL; 88 89 /* Set TCR to the original configuration */ 90 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); 91 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 92 } else { 93 u32 tcr = cb->tcr[0]; 94 95 /* Don't call this again if TTBR0 is already enabled */ 96 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 97 return -EINVAL; 98 99 tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); 100 tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); 101 102 cb->tcr[0] = tcr; 103 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; 104 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 105 } 106 107 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); 108 109 return 0; 110 } 111 112 static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, 113 struct arm_smmu_device *smmu, 114 struct device *dev, int start) 115 { 116 int count; 117 118 /* 119 * Assign context bank 0 to the GPU device so the GPU hardware can 120 * switch pagetables 121 */ 122 if (qcom_adreno_smmu_is_gpu_device(dev)) { 123 start = 0; 124 count = 1; 125 } else { 126 start = 1; 127 count = smmu->num_context_banks; 128 } 129 130 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); 131 } 132 133 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, 134 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) 135 { 136 struct adreno_smmu_priv *priv; 137 138 /* Only enable split pagetables for the GPU device (SID 0) */ 139 if (!qcom_adreno_smmu_is_gpu_device(dev)) 140 return 0; 141 142 /* 143 * All targets that use the qcom,adreno-smmu compatible string *should* 144 * be AARCH64 stage 1 but double check because the arm-smmu code assumes 145 * that is the case when the TTBR1 quirk is enabled 146 */ 147 if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && 148 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) 149 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; 150 151 /* 152 * Initialize private interface with GPU: 153 */ 154 155 priv = dev_get_drvdata(dev); 156 priv->cookie = smmu_domain; 157 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; 158 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; 159 160 return 0; 161 } 162 163 static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { 164 { .compatible = "qcom,adreno" }, 165 { .compatible = "qcom,mdp4" }, 166 { .compatible = "qcom,mdss" }, 167 { .compatible = "qcom,sc7180-mdss" }, 168 { .compatible = "qcom,sc7180-mss-pil" }, 169 { .compatible = "qcom,sdm845-mdss" }, 170 { .compatible = "qcom,sdm845-mss-pil" }, 171 { } 172 }; 173 174 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) 175 { 176 unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); 177 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 178 u32 reg; 179 u32 smr; 180 int i; 181 182 /* 183 * With some firmware versions writes to S2CR of type FAULT are 184 * ignored, and writing BYPASS will end up written as FAULT in the 185 * register. Perform a write to S2CR to detect if this is the case and 186 * if so reserve a context bank to emulate bypass streams. 187 */ 188 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | 189 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | 190 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); 191 arm_smmu_gr0_write(smmu, last_s2cr, reg); 192 reg = arm_smmu_gr0_read(smmu, last_s2cr); 193 if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { 194 qsmmu->bypass_quirk = true; 195 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; 196 197 set_bit(qsmmu->bypass_cbndx, smmu->context_map); 198 199 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); 200 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); 201 } 202 203 for (i = 0; i < smmu->num_mapping_groups; i++) { 204 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); 205 206 if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { 207 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); 208 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); 209 smmu->smrs[i].valid = true; 210 211 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; 212 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; 213 smmu->s2crs[i].cbndx = 0xff; 214 } 215 } 216 217 return 0; 218 } 219 220 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) 221 { 222 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; 223 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 224 u32 cbndx = s2cr->cbndx; 225 u32 type = s2cr->type; 226 u32 reg; 227 228 if (qsmmu->bypass_quirk) { 229 if (type == S2CR_TYPE_BYPASS) { 230 /* 231 * Firmware with quirky S2CR handling will substitute 232 * BYPASS writes with FAULT, so point the stream to the 233 * reserved context bank and ask for translation on the 234 * stream 235 */ 236 type = S2CR_TYPE_TRANS; 237 cbndx = qsmmu->bypass_cbndx; 238 } else if (type == S2CR_TYPE_FAULT) { 239 /* 240 * Firmware with quirky S2CR handling will ignore FAULT 241 * writes, so trick it to write FAULT by asking for a 242 * BYPASS. 243 */ 244 type = S2CR_TYPE_BYPASS; 245 cbndx = 0xff; 246 } 247 } 248 249 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) | 250 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) | 251 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); 252 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); 253 } 254 255 static int qcom_smmu_def_domain_type(struct device *dev) 256 { 257 const struct of_device_id *match = 258 of_match_device(qcom_smmu_client_of_match, dev); 259 260 return match ? IOMMU_DOMAIN_IDENTITY : 0; 261 } 262 263 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) 264 { 265 int ret; 266 267 /* 268 * To address performance degradation in non-real time clients, 269 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, 270 * such as MTP and db845, whose firmwares implement secure monitor 271 * call handlers to turn on/off the wait-for-safe logic. 272 */ 273 ret = qcom_scm_qsmmu500_wait_safe_toggle(0); 274 if (ret) 275 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); 276 277 return ret; 278 } 279 280 static int qcom_smmu500_reset(struct arm_smmu_device *smmu) 281 { 282 const struct device_node *np = smmu->dev->of_node; 283 284 arm_mmu500_reset(smmu); 285 286 if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) 287 return qcom_sdm845_smmu500_reset(smmu); 288 289 return 0; 290 } 291 292 static const struct arm_smmu_impl qcom_smmu_impl = { 293 .cfg_probe = qcom_smmu_cfg_probe, 294 .def_domain_type = qcom_smmu_def_domain_type, 295 .reset = qcom_smmu500_reset, 296 .write_s2cr = qcom_smmu_write_s2cr, 297 }; 298 299 static const struct arm_smmu_impl qcom_adreno_smmu_impl = { 300 .init_context = qcom_adreno_smmu_init_context, 301 .def_domain_type = qcom_smmu_def_domain_type, 302 .reset = qcom_smmu500_reset, 303 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, 304 .write_sctlr = qcom_adreno_smmu_write_sctlr, 305 }; 306 307 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, 308 const struct arm_smmu_impl *impl) 309 { 310 struct qcom_smmu *qsmmu; 311 312 /* Check to make sure qcom_scm has finished probing */ 313 if (!qcom_scm_is_available()) 314 return ERR_PTR(-EPROBE_DEFER); 315 316 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); 317 if (!qsmmu) 318 return ERR_PTR(-ENOMEM); 319 320 qsmmu->smmu.impl = impl; 321 322 return &qsmmu->smmu; 323 } 324 325 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { 326 { .compatible = "qcom,sc7180-smmu-500" }, 327 { .compatible = "qcom,sdm845-smmu-500" }, 328 { .compatible = "qcom,sm8150-smmu-500" }, 329 { .compatible = "qcom,sm8250-smmu-500" }, 330 { } 331 }; 332 333 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) 334 { 335 const struct device_node *np = smmu->dev->of_node; 336 337 if (of_match_node(qcom_smmu_impl_of_match, np)) 338 return qcom_smmu_create(smmu, &qcom_smmu_impl); 339 340 if (of_device_is_compatible(np, "qcom,adreno-smmu")) 341 return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); 342 343 return smmu; 344 } 345