1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/adreno-smmu-priv.h> 8 #include <linux/delay.h> 9 #include <linux/of_device.h> 10 #include <linux/firmware/qcom/qcom_scm.h> 11 12 #include "arm-smmu.h" 13 #include "arm-smmu-qcom.h" 14 15 #define QCOM_DUMMY_VAL -1 16 17 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) 18 { 19 return container_of(smmu, struct qcom_smmu, smmu); 20 } 21 22 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, 23 int sync, int status) 24 { 25 unsigned int spin_cnt, delay; 26 u32 reg; 27 28 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); 29 for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) { 30 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { 31 reg = arm_smmu_readl(smmu, page, status); 32 if (!(reg & ARM_SMMU_sTLBGSTATUS_GSACTIVE)) 33 return; 34 cpu_relax(); 35 } 36 udelay(delay); 37 } 38 39 qcom_smmu_tlb_sync_debug(smmu); 40 } 41 42 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, 43 u32 reg) 44 { 45 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 46 47 /* 48 * On the GPU device we want to process subsequent transactions after a 49 * fault to keep the GPU from hanging 50 */ 51 reg |= ARM_SMMU_SCTLR_HUPCF; 52 53 if (qsmmu->stall_enabled & BIT(idx)) 54 reg |= ARM_SMMU_SCTLR_CFCFG; 55 56 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); 57 } 58 59 static void qcom_adreno_smmu_get_fault_info(const void *cookie, 60 struct adreno_smmu_fault_info *info) 61 { 62 struct arm_smmu_domain *smmu_domain = (void *)cookie; 63 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 64 struct arm_smmu_device *smmu = smmu_domain->smmu; 65 66 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); 67 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); 68 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); 69 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); 70 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); 71 info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); 72 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); 73 } 74 75 static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) 76 { 77 struct arm_smmu_domain *smmu_domain = (void *)cookie; 78 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 79 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); 80 81 if (enabled) 82 qsmmu->stall_enabled |= BIT(cfg->cbndx); 83 else 84 qsmmu->stall_enabled &= ~BIT(cfg->cbndx); 85 } 86 87 static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate) 88 { 89 struct arm_smmu_domain *smmu_domain = (void *)cookie; 90 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 91 struct arm_smmu_device *smmu = smmu_domain->smmu; 92 u32 reg = 0; 93 94 if (terminate) 95 reg |= ARM_SMMU_RESUME_TERMINATE; 96 97 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); 98 } 99 100 #define QCOM_ADRENO_SMMU_GPU_SID 0 101 102 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) 103 { 104 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 105 int i; 106 107 /* 108 * The GPU will always use SID 0 so that is a handy way to uniquely 109 * identify it and configure it for per-instance pagetables 110 */ 111 for (i = 0; i < fwspec->num_ids; i++) { 112 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); 113 114 if (sid == QCOM_ADRENO_SMMU_GPU_SID) 115 return true; 116 } 117 118 return false; 119 } 120 121 static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( 122 const void *cookie) 123 { 124 struct arm_smmu_domain *smmu_domain = (void *)cookie; 125 struct io_pgtable *pgtable = 126 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 127 return &pgtable->cfg; 128 } 129 130 /* 131 * Local implementation to configure TTBR0 with the specified pagetable config. 132 * The GPU driver will call this to enable TTBR0 when per-instance pagetables 133 * are active 134 */ 135 136 static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, 137 const struct io_pgtable_cfg *pgtbl_cfg) 138 { 139 struct arm_smmu_domain *smmu_domain = (void *)cookie; 140 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 141 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 142 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; 143 144 /* The domain must have split pagetables already enabled */ 145 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) 146 return -EINVAL; 147 148 /* If the pagetable config is NULL, disable TTBR0 */ 149 if (!pgtbl_cfg) { 150 /* Do nothing if it is already disabled */ 151 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 152 return -EINVAL; 153 154 /* Set TCR to the original configuration */ 155 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); 156 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 157 } else { 158 u32 tcr = cb->tcr[0]; 159 160 /* Don't call this again if TTBR0 is already enabled */ 161 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 162 return -EINVAL; 163 164 tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); 165 tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); 166 167 cb->tcr[0] = tcr; 168 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; 169 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 170 } 171 172 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); 173 174 return 0; 175 } 176 177 static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, 178 struct arm_smmu_device *smmu, 179 struct device *dev, int start) 180 { 181 int count; 182 183 /* 184 * Assign context bank 0 to the GPU device so the GPU hardware can 185 * switch pagetables 186 */ 187 if (qcom_adreno_smmu_is_gpu_device(dev)) { 188 start = 0; 189 count = 1; 190 } else { 191 start = 1; 192 count = smmu->num_context_banks; 193 } 194 195 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); 196 } 197 198 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) 199 { 200 const struct device_node *np = smmu->dev->of_node; 201 202 if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) 203 return false; 204 205 return true; 206 } 207 208 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, 209 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) 210 { 211 struct adreno_smmu_priv *priv; 212 213 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; 214 215 /* Only enable split pagetables for the GPU device (SID 0) */ 216 if (!qcom_adreno_smmu_is_gpu_device(dev)) 217 return 0; 218 219 /* 220 * All targets that use the qcom,adreno-smmu compatible string *should* 221 * be AARCH64 stage 1 but double check because the arm-smmu code assumes 222 * that is the case when the TTBR1 quirk is enabled 223 */ 224 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && 225 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && 226 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) 227 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; 228 229 /* 230 * Initialize private interface with GPU: 231 */ 232 233 priv = dev_get_drvdata(dev); 234 priv->cookie = smmu_domain; 235 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; 236 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; 237 priv->get_fault_info = qcom_adreno_smmu_get_fault_info; 238 priv->set_stall = qcom_adreno_smmu_set_stall; 239 priv->resume_translation = qcom_adreno_smmu_resume_translation; 240 241 return 0; 242 } 243 244 static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { 245 { .compatible = "qcom,adreno" }, 246 { .compatible = "qcom,mdp4" }, 247 { .compatible = "qcom,mdss" }, 248 { .compatible = "qcom,sc7180-mdss" }, 249 { .compatible = "qcom,sc7180-mss-pil" }, 250 { .compatible = "qcom,sc7280-mdss" }, 251 { .compatible = "qcom,sc7280-mss-pil" }, 252 { .compatible = "qcom,sc8180x-mdss" }, 253 { .compatible = "qcom,sc8280xp-mdss" }, 254 { .compatible = "qcom,sdm845-mdss" }, 255 { .compatible = "qcom,sdm845-mss-pil" }, 256 { .compatible = "qcom,sm6350-mdss" }, 257 { .compatible = "qcom,sm6375-mdss" }, 258 { .compatible = "qcom,sm8150-mdss" }, 259 { .compatible = "qcom,sm8250-mdss" }, 260 { } 261 }; 262 263 static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain, 264 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) 265 { 266 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; 267 268 return 0; 269 } 270 271 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) 272 { 273 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 274 unsigned int last_s2cr; 275 u32 reg; 276 u32 smr; 277 int i; 278 279 /* 280 * Some platforms support more than the Arm SMMU architected maximum of 281 * 128 stream matching groups. For unknown reasons, the additional 282 * groups don't exhibit the same behavior as the architected registers, 283 * so limit the groups to 128 until the behavior is fixed for the other 284 * groups. 285 */ 286 if (smmu->num_mapping_groups > 128) { 287 dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n"); 288 smmu->num_mapping_groups = 128; 289 } 290 291 last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); 292 293 /* 294 * With some firmware versions writes to S2CR of type FAULT are 295 * ignored, and writing BYPASS will end up written as FAULT in the 296 * register. Perform a write to S2CR to detect if this is the case and 297 * if so reserve a context bank to emulate bypass streams. 298 */ 299 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | 300 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | 301 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); 302 arm_smmu_gr0_write(smmu, last_s2cr, reg); 303 reg = arm_smmu_gr0_read(smmu, last_s2cr); 304 if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { 305 qsmmu->bypass_quirk = true; 306 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; 307 308 set_bit(qsmmu->bypass_cbndx, smmu->context_map); 309 310 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); 311 312 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); 313 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); 314 } 315 316 for (i = 0; i < smmu->num_mapping_groups; i++) { 317 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); 318 319 if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { 320 /* Ignore valid bit for SMR mask extraction. */ 321 smr &= ~ARM_SMMU_SMR_VALID; 322 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); 323 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); 324 smmu->smrs[i].valid = true; 325 326 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; 327 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; 328 smmu->s2crs[i].cbndx = 0xff; 329 } 330 } 331 332 return 0; 333 } 334 335 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) 336 { 337 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; 338 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 339 u32 cbndx = s2cr->cbndx; 340 u32 type = s2cr->type; 341 u32 reg; 342 343 if (qsmmu->bypass_quirk) { 344 if (type == S2CR_TYPE_BYPASS) { 345 /* 346 * Firmware with quirky S2CR handling will substitute 347 * BYPASS writes with FAULT, so point the stream to the 348 * reserved context bank and ask for translation on the 349 * stream 350 */ 351 type = S2CR_TYPE_TRANS; 352 cbndx = qsmmu->bypass_cbndx; 353 } else if (type == S2CR_TYPE_FAULT) { 354 /* 355 * Firmware with quirky S2CR handling will ignore FAULT 356 * writes, so trick it to write FAULT by asking for a 357 * BYPASS. 358 */ 359 type = S2CR_TYPE_BYPASS; 360 cbndx = 0xff; 361 } 362 } 363 364 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) | 365 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) | 366 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); 367 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); 368 } 369 370 static int qcom_smmu_def_domain_type(struct device *dev) 371 { 372 const struct of_device_id *match = 373 of_match_device(qcom_smmu_client_of_match, dev); 374 375 return match ? IOMMU_DOMAIN_IDENTITY : 0; 376 } 377 378 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) 379 { 380 int ret; 381 382 arm_mmu500_reset(smmu); 383 384 /* 385 * To address performance degradation in non-real time clients, 386 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, 387 * such as MTP and db845, whose firmwares implement secure monitor 388 * call handlers to turn on/off the wait-for-safe logic. 389 */ 390 ret = qcom_scm_qsmmu500_wait_safe_toggle(0); 391 if (ret) 392 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); 393 394 return ret; 395 } 396 397 static const struct arm_smmu_impl qcom_smmu_v2_impl = { 398 .init_context = qcom_smmu_init_context, 399 .cfg_probe = qcom_smmu_cfg_probe, 400 .def_domain_type = qcom_smmu_def_domain_type, 401 .write_s2cr = qcom_smmu_write_s2cr, 402 .tlb_sync = qcom_smmu_tlb_sync, 403 }; 404 405 static const struct arm_smmu_impl qcom_smmu_500_impl = { 406 .init_context = qcom_smmu_init_context, 407 .cfg_probe = qcom_smmu_cfg_probe, 408 .def_domain_type = qcom_smmu_def_domain_type, 409 .reset = arm_mmu500_reset, 410 .write_s2cr = qcom_smmu_write_s2cr, 411 .tlb_sync = qcom_smmu_tlb_sync, 412 }; 413 414 static const struct arm_smmu_impl sdm845_smmu_500_impl = { 415 .init_context = qcom_smmu_init_context, 416 .cfg_probe = qcom_smmu_cfg_probe, 417 .def_domain_type = qcom_smmu_def_domain_type, 418 .reset = qcom_sdm845_smmu500_reset, 419 .write_s2cr = qcom_smmu_write_s2cr, 420 .tlb_sync = qcom_smmu_tlb_sync, 421 }; 422 423 static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { 424 .init_context = qcom_adreno_smmu_init_context, 425 .def_domain_type = qcom_smmu_def_domain_type, 426 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, 427 .write_sctlr = qcom_adreno_smmu_write_sctlr, 428 .tlb_sync = qcom_smmu_tlb_sync, 429 }; 430 431 static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { 432 .init_context = qcom_adreno_smmu_init_context, 433 .def_domain_type = qcom_smmu_def_domain_type, 434 .reset = arm_mmu500_reset, 435 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, 436 .write_sctlr = qcom_adreno_smmu_write_sctlr, 437 .tlb_sync = qcom_smmu_tlb_sync, 438 }; 439 440 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, 441 const struct qcom_smmu_match_data *data) 442 { 443 const struct device_node *np = smmu->dev->of_node; 444 const struct arm_smmu_impl *impl; 445 struct qcom_smmu *qsmmu; 446 447 if (!data) 448 return ERR_PTR(-EINVAL); 449 450 if (np && of_device_is_compatible(np, "qcom,adreno-smmu")) 451 impl = data->adreno_impl; 452 else 453 impl = data->impl; 454 455 if (!impl) 456 return smmu; 457 458 /* Check to make sure qcom_scm has finished probing */ 459 if (!qcom_scm_is_available()) 460 return ERR_PTR(-EPROBE_DEFER); 461 462 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); 463 if (!qsmmu) 464 return ERR_PTR(-ENOMEM); 465 466 qsmmu->smmu.impl = impl; 467 qsmmu->cfg = data->cfg; 468 469 return &qsmmu->smmu; 470 } 471 472 /* Implementation Defined Register Space 0 register offsets */ 473 static const u32 qcom_smmu_impl0_reg_offset[] = { 474 [QCOM_SMMU_TBU_PWR_STATUS] = 0x2204, 475 [QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc, 476 [QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670, 477 }; 478 479 static const struct qcom_smmu_config qcom_smmu_impl0_cfg = { 480 .reg_offset = qcom_smmu_impl0_reg_offset, 481 }; 482 483 /* 484 * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996, 485 * there are not enough context banks. 486 */ 487 static const struct qcom_smmu_match_data msm8996_smmu_data = { 488 .impl = NULL, 489 .adreno_impl = &qcom_adreno_smmu_v2_impl, 490 }; 491 492 static const struct qcom_smmu_match_data qcom_smmu_v2_data = { 493 .impl = &qcom_smmu_v2_impl, 494 .adreno_impl = &qcom_adreno_smmu_v2_impl, 495 }; 496 497 static const struct qcom_smmu_match_data sdm845_smmu_500_data = { 498 .impl = &sdm845_smmu_500_impl, 499 /* 500 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled 501 * by the separate sdm845-smmu-v2 device. 502 */ 503 /* Also no debug configuration. */ 504 }; 505 506 static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = { 507 .impl = &qcom_smmu_500_impl, 508 .adreno_impl = &qcom_adreno_smmu_500_impl, 509 .cfg = &qcom_smmu_impl0_cfg, 510 }; 511 512 /* 513 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need 514 * special handling and can not be covered by the qcom,smmu-500 entry. 515 */ 516 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { 517 { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data }, 518 { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data }, 519 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data }, 520 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data }, 521 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data }, 522 { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data }, 523 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data }, 524 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data }, 525 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data }, 526 { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data }, 527 { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data }, 528 { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data }, 529 { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data}, 530 { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data }, 531 { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data }, 532 { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data }, 533 { .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data }, 534 { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data }, 535 { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data }, 536 { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data }, 537 { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data }, 538 { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data }, 539 { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data }, 540 { } 541 }; 542 543 #ifdef CONFIG_ACPI 544 static struct acpi_platform_list qcom_acpi_platlist[] = { 545 { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" }, 546 { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" }, 547 { } 548 }; 549 #endif 550 551 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) 552 { 553 const struct device_node *np = smmu->dev->of_node; 554 const struct of_device_id *match; 555 556 #ifdef CONFIG_ACPI 557 if (np == NULL) { 558 /* Match platform for ACPI boot */ 559 if (acpi_match_platform_list(qcom_acpi_platlist) >= 0) 560 return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data); 561 } 562 #endif 563 564 match = of_match_node(qcom_smmu_impl_of_match, np); 565 if (match) 566 return qcom_smmu_create(smmu, match->data); 567 568 /* 569 * If you hit this WARN_ON() you are missing an entry in the 570 * qcom_smmu_impl_of_match[] table, and GPU per-process page- 571 * tables will be broken. 572 */ 573 WARN(of_device_is_compatible(np, "qcom,adreno-smmu"), 574 "Missing qcom_smmu_impl_of_match entry for: %s", 575 dev_name(smmu->dev)); 576 577 return smmu; 578 } 579