1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/adreno-smmu-priv.h> 7 #include <linux/of_device.h> 8 #include <linux/qcom_scm.h> 9 10 #include "arm-smmu.h" 11 12 struct qcom_smmu { 13 struct arm_smmu_device smmu; 14 bool bypass_quirk; 15 u8 bypass_cbndx; 16 u32 stall_enabled; 17 }; 18 19 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) 20 { 21 return container_of(smmu, struct qcom_smmu, smmu); 22 } 23 24 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, 25 u32 reg) 26 { 27 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 28 29 /* 30 * On the GPU device we want to process subsequent transactions after a 31 * fault to keep the GPU from hanging 32 */ 33 reg |= ARM_SMMU_SCTLR_HUPCF; 34 35 if (qsmmu->stall_enabled & BIT(idx)) 36 reg |= ARM_SMMU_SCTLR_CFCFG; 37 38 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); 39 } 40 41 static void qcom_adreno_smmu_get_fault_info(const void *cookie, 42 struct adreno_smmu_fault_info *info) 43 { 44 struct arm_smmu_domain *smmu_domain = (void *)cookie; 45 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 46 struct arm_smmu_device *smmu = smmu_domain->smmu; 47 48 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); 49 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); 50 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); 51 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); 52 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); 53 info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); 54 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); 55 } 56 57 static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) 58 { 59 struct arm_smmu_domain *smmu_domain = (void *)cookie; 60 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 61 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); 62 63 if (enabled) 64 qsmmu->stall_enabled |= BIT(cfg->cbndx); 65 else 66 qsmmu->stall_enabled &= ~BIT(cfg->cbndx); 67 } 68 69 static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate) 70 { 71 struct arm_smmu_domain *smmu_domain = (void *)cookie; 72 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 73 struct arm_smmu_device *smmu = smmu_domain->smmu; 74 u32 reg = 0; 75 76 if (terminate) 77 reg |= ARM_SMMU_RESUME_TERMINATE; 78 79 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); 80 } 81 82 #define QCOM_ADRENO_SMMU_GPU_SID 0 83 84 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) 85 { 86 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 87 int i; 88 89 /* 90 * The GPU will always use SID 0 so that is a handy way to uniquely 91 * identify it and configure it for per-instance pagetables 92 */ 93 for (i = 0; i < fwspec->num_ids; i++) { 94 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); 95 96 if (sid == QCOM_ADRENO_SMMU_GPU_SID) 97 return true; 98 } 99 100 return false; 101 } 102 103 static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( 104 const void *cookie) 105 { 106 struct arm_smmu_domain *smmu_domain = (void *)cookie; 107 struct io_pgtable *pgtable = 108 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 109 return &pgtable->cfg; 110 } 111 112 /* 113 * Local implementation to configure TTBR0 with the specified pagetable config. 114 * The GPU driver will call this to enable TTBR0 when per-instance pagetables 115 * are active 116 */ 117 118 static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, 119 const struct io_pgtable_cfg *pgtbl_cfg) 120 { 121 struct arm_smmu_domain *smmu_domain = (void *)cookie; 122 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 123 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 124 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; 125 126 /* The domain must have split pagetables already enabled */ 127 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) 128 return -EINVAL; 129 130 /* If the pagetable config is NULL, disable TTBR0 */ 131 if (!pgtbl_cfg) { 132 /* Do nothing if it is already disabled */ 133 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 134 return -EINVAL; 135 136 /* Set TCR to the original configuration */ 137 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); 138 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 139 } else { 140 u32 tcr = cb->tcr[0]; 141 142 /* Don't call this again if TTBR0 is already enabled */ 143 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 144 return -EINVAL; 145 146 tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); 147 tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); 148 149 cb->tcr[0] = tcr; 150 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; 151 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 152 } 153 154 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); 155 156 return 0; 157 } 158 159 static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, 160 struct arm_smmu_device *smmu, 161 struct device *dev, int start) 162 { 163 int count; 164 165 /* 166 * Assign context bank 0 to the GPU device so the GPU hardware can 167 * switch pagetables 168 */ 169 if (qcom_adreno_smmu_is_gpu_device(dev)) { 170 start = 0; 171 count = 1; 172 } else { 173 start = 1; 174 count = smmu->num_context_banks; 175 } 176 177 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); 178 } 179 180 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, 181 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) 182 { 183 struct adreno_smmu_priv *priv; 184 185 /* Only enable split pagetables for the GPU device (SID 0) */ 186 if (!qcom_adreno_smmu_is_gpu_device(dev)) 187 return 0; 188 189 /* 190 * All targets that use the qcom,adreno-smmu compatible string *should* 191 * be AARCH64 stage 1 but double check because the arm-smmu code assumes 192 * that is the case when the TTBR1 quirk is enabled 193 */ 194 if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && 195 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) 196 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; 197 198 /* 199 * Initialize private interface with GPU: 200 */ 201 202 priv = dev_get_drvdata(dev); 203 priv->cookie = smmu_domain; 204 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; 205 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; 206 priv->get_fault_info = qcom_adreno_smmu_get_fault_info; 207 priv->set_stall = qcom_adreno_smmu_set_stall; 208 priv->resume_translation = qcom_adreno_smmu_resume_translation; 209 210 return 0; 211 } 212 213 static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { 214 { .compatible = "qcom,adreno" }, 215 { .compatible = "qcom,mdp4" }, 216 { .compatible = "qcom,mdss" }, 217 { .compatible = "qcom,sc7180-mdss" }, 218 { .compatible = "qcom,sc7180-mss-pil" }, 219 { .compatible = "qcom,sc8180x-mdss" }, 220 { .compatible = "qcom,sdm845-mdss" }, 221 { .compatible = "qcom,sdm845-mss-pil" }, 222 { } 223 }; 224 225 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) 226 { 227 unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); 228 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 229 u32 reg; 230 u32 smr; 231 int i; 232 233 /* 234 * With some firmware versions writes to S2CR of type FAULT are 235 * ignored, and writing BYPASS will end up written as FAULT in the 236 * register. Perform a write to S2CR to detect if this is the case and 237 * if so reserve a context bank to emulate bypass streams. 238 */ 239 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | 240 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | 241 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); 242 arm_smmu_gr0_write(smmu, last_s2cr, reg); 243 reg = arm_smmu_gr0_read(smmu, last_s2cr); 244 if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { 245 qsmmu->bypass_quirk = true; 246 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; 247 248 set_bit(qsmmu->bypass_cbndx, smmu->context_map); 249 250 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); 251 252 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); 253 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); 254 } 255 256 for (i = 0; i < smmu->num_mapping_groups; i++) { 257 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); 258 259 if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { 260 /* Ignore valid bit for SMR mask extraction. */ 261 smr &= ~ARM_SMMU_SMR_VALID; 262 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); 263 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); 264 smmu->smrs[i].valid = true; 265 266 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; 267 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; 268 smmu->s2crs[i].cbndx = 0xff; 269 } 270 } 271 272 return 0; 273 } 274 275 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) 276 { 277 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; 278 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 279 u32 cbndx = s2cr->cbndx; 280 u32 type = s2cr->type; 281 u32 reg; 282 283 if (qsmmu->bypass_quirk) { 284 if (type == S2CR_TYPE_BYPASS) { 285 /* 286 * Firmware with quirky S2CR handling will substitute 287 * BYPASS writes with FAULT, so point the stream to the 288 * reserved context bank and ask for translation on the 289 * stream 290 */ 291 type = S2CR_TYPE_TRANS; 292 cbndx = qsmmu->bypass_cbndx; 293 } else if (type == S2CR_TYPE_FAULT) { 294 /* 295 * Firmware with quirky S2CR handling will ignore FAULT 296 * writes, so trick it to write FAULT by asking for a 297 * BYPASS. 298 */ 299 type = S2CR_TYPE_BYPASS; 300 cbndx = 0xff; 301 } 302 } 303 304 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) | 305 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) | 306 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); 307 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); 308 } 309 310 static int qcom_smmu_def_domain_type(struct device *dev) 311 { 312 const struct of_device_id *match = 313 of_match_device(qcom_smmu_client_of_match, dev); 314 315 return match ? IOMMU_DOMAIN_IDENTITY : 0; 316 } 317 318 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) 319 { 320 int ret; 321 322 /* 323 * To address performance degradation in non-real time clients, 324 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, 325 * such as MTP and db845, whose firmwares implement secure monitor 326 * call handlers to turn on/off the wait-for-safe logic. 327 */ 328 ret = qcom_scm_qsmmu500_wait_safe_toggle(0); 329 if (ret) 330 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); 331 332 return ret; 333 } 334 335 static int qcom_smmu500_reset(struct arm_smmu_device *smmu) 336 { 337 const struct device_node *np = smmu->dev->of_node; 338 339 arm_mmu500_reset(smmu); 340 341 if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) 342 return qcom_sdm845_smmu500_reset(smmu); 343 344 return 0; 345 } 346 347 static const struct arm_smmu_impl qcom_smmu_impl = { 348 .cfg_probe = qcom_smmu_cfg_probe, 349 .def_domain_type = qcom_smmu_def_domain_type, 350 .reset = qcom_smmu500_reset, 351 .write_s2cr = qcom_smmu_write_s2cr, 352 }; 353 354 static const struct arm_smmu_impl qcom_adreno_smmu_impl = { 355 .init_context = qcom_adreno_smmu_init_context, 356 .def_domain_type = qcom_smmu_def_domain_type, 357 .reset = qcom_smmu500_reset, 358 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, 359 .write_sctlr = qcom_adreno_smmu_write_sctlr, 360 }; 361 362 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, 363 const struct arm_smmu_impl *impl) 364 { 365 struct qcom_smmu *qsmmu; 366 367 /* Check to make sure qcom_scm has finished probing */ 368 if (!qcom_scm_is_available()) 369 return ERR_PTR(-EPROBE_DEFER); 370 371 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); 372 if (!qsmmu) 373 return ERR_PTR(-ENOMEM); 374 375 qsmmu->smmu.impl = impl; 376 377 return &qsmmu->smmu; 378 } 379 380 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { 381 { .compatible = "qcom,msm8998-smmu-v2" }, 382 { .compatible = "qcom,sc7180-smmu-500" }, 383 { .compatible = "qcom,sc8180x-smmu-500" }, 384 { .compatible = "qcom,sdm630-smmu-v2" }, 385 { .compatible = "qcom,sdm845-smmu-500" }, 386 { .compatible = "qcom,sm8150-smmu-500" }, 387 { .compatible = "qcom,sm8250-smmu-500" }, 388 { .compatible = "qcom,sm8350-smmu-500" }, 389 { } 390 }; 391 392 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) 393 { 394 const struct device_node *np = smmu->dev->of_node; 395 396 if (of_match_node(qcom_smmu_impl_of_match, np)) 397 return qcom_smmu_create(smmu, &qcom_smmu_impl); 398 399 if (of_device_is_compatible(np, "qcom,adreno-smmu")) 400 return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); 401 402 return smmu; 403 } 404