1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/ratelimit.h> 12 #include <linux/pci.h> 13 #include <linux/acpi.h> 14 #include <linux/pci-ats.h> 15 #include <linux/bitmap.h> 16 #include <linux/slab.h> 17 #include <linux/debugfs.h> 18 #include <linux/scatterlist.h> 19 #include <linux/dma-map-ops.h> 20 #include <linux/dma-direct.h> 21 #include <linux/iommu-helper.h> 22 #include <linux/delay.h> 23 #include <linux/amd-iommu.h> 24 #include <linux/notifier.h> 25 #include <linux/export.h> 26 #include <linux/irq.h> 27 #include <linux/msi.h> 28 #include <linux/irqdomain.h> 29 #include <linux/percpu.h> 30 #include <linux/io-pgtable.h> 31 #include <linux/cc_platform.h> 32 #include <asm/irq_remapping.h> 33 #include <asm/io_apic.h> 34 #include <asm/apic.h> 35 #include <asm/hw_irq.h> 36 #include <asm/proto.h> 37 #include <asm/iommu.h> 38 #include <asm/gart.h> 39 #include <asm/dma.h> 40 41 #include "amd_iommu.h" 42 #include "../dma-iommu.h" 43 #include "../irq_remapping.h" 44 45 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) 46 47 #define LOOP_TIMEOUT 100000 48 49 /* IO virtual address start page frame number */ 50 #define IOVA_START_PFN (1) 51 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) 52 53 /* Reserved IOVA ranges */ 54 #define MSI_RANGE_START (0xfee00000) 55 #define MSI_RANGE_END (0xfeefffff) 56 #define HT_RANGE_START (0xfd00000000ULL) 57 #define HT_RANGE_END (0xffffffffffULL) 58 59 #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL 60 61 static DEFINE_SPINLOCK(pd_bitmap_lock); 62 63 LIST_HEAD(ioapic_map); 64 LIST_HEAD(hpet_map); 65 LIST_HEAD(acpihid_map); 66 67 const struct iommu_ops amd_iommu_ops; 68 69 static ATOMIC_NOTIFIER_HEAD(ppr_notifier); 70 int amd_iommu_max_glx_val = -1; 71 72 /* 73 * general struct to manage commands send to an IOMMU 74 */ 75 struct iommu_cmd { 76 u32 data[4]; 77 }; 78 79 struct kmem_cache *amd_iommu_irq_cache; 80 81 static void detach_device(struct device *dev); 82 static int domain_enable_v2(struct protection_domain *domain, int pasids); 83 84 /**************************************************************************** 85 * 86 * Helper functions 87 * 88 ****************************************************************************/ 89 90 static inline int get_acpihid_device_id(struct device *dev, 91 struct acpihid_map_entry **entry) 92 { 93 struct acpi_device *adev = ACPI_COMPANION(dev); 94 struct acpihid_map_entry *p; 95 96 if (!adev) 97 return -ENODEV; 98 99 list_for_each_entry(p, &acpihid_map, list) { 100 if (acpi_dev_hid_uid_match(adev, p->hid, 101 p->uid[0] ? p->uid : NULL)) { 102 if (entry) 103 *entry = p; 104 return p->devid; 105 } 106 } 107 return -EINVAL; 108 } 109 110 static inline int get_device_sbdf_id(struct device *dev) 111 { 112 int sbdf; 113 114 if (dev_is_pci(dev)) 115 sbdf = get_pci_sbdf_id(to_pci_dev(dev)); 116 else 117 sbdf = get_acpihid_device_id(dev, NULL); 118 119 return sbdf; 120 } 121 122 struct dev_table_entry *get_dev_table(struct amd_iommu *iommu) 123 { 124 struct dev_table_entry *dev_table; 125 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 126 127 BUG_ON(pci_seg == NULL); 128 dev_table = pci_seg->dev_table; 129 BUG_ON(dev_table == NULL); 130 131 return dev_table; 132 } 133 134 static inline u16 get_device_segment(struct device *dev) 135 { 136 u16 seg; 137 138 if (dev_is_pci(dev)) { 139 struct pci_dev *pdev = to_pci_dev(dev); 140 141 seg = pci_domain_nr(pdev->bus); 142 } else { 143 u32 devid = get_acpihid_device_id(dev, NULL); 144 145 seg = PCI_SBDF_TO_SEGID(devid); 146 } 147 148 return seg; 149 } 150 151 /* Writes the specific IOMMU for a device into the PCI segment rlookup table */ 152 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid) 153 { 154 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 155 156 pci_seg->rlookup_table[devid] = iommu; 157 } 158 159 static struct amd_iommu *__rlookup_amd_iommu(u16 seg, u16 devid) 160 { 161 struct amd_iommu_pci_seg *pci_seg; 162 163 for_each_pci_segment(pci_seg) { 164 if (pci_seg->id == seg) 165 return pci_seg->rlookup_table[devid]; 166 } 167 return NULL; 168 } 169 170 static struct amd_iommu *rlookup_amd_iommu(struct device *dev) 171 { 172 u16 seg = get_device_segment(dev); 173 int devid = get_device_sbdf_id(dev); 174 175 if (devid < 0) 176 return NULL; 177 return __rlookup_amd_iommu(seg, PCI_SBDF_TO_DEVID(devid)); 178 } 179 180 static struct protection_domain *to_pdomain(struct iommu_domain *dom) 181 { 182 return container_of(dom, struct protection_domain, domain); 183 } 184 185 static struct iommu_dev_data *alloc_dev_data(struct amd_iommu *iommu, u16 devid) 186 { 187 struct iommu_dev_data *dev_data; 188 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 189 190 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); 191 if (!dev_data) 192 return NULL; 193 194 spin_lock_init(&dev_data->lock); 195 dev_data->devid = devid; 196 ratelimit_default_init(&dev_data->rs); 197 198 llist_add(&dev_data->dev_data_list, &pci_seg->dev_data_list); 199 return dev_data; 200 } 201 202 static struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid) 203 { 204 struct iommu_dev_data *dev_data; 205 struct llist_node *node; 206 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 207 208 if (llist_empty(&pci_seg->dev_data_list)) 209 return NULL; 210 211 node = pci_seg->dev_data_list.first; 212 llist_for_each_entry(dev_data, node, dev_data_list) { 213 if (dev_data->devid == devid) 214 return dev_data; 215 } 216 217 return NULL; 218 } 219 220 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data) 221 { 222 struct amd_iommu *iommu; 223 struct dev_table_entry *dev_table; 224 u16 devid = pci_dev_id(pdev); 225 226 if (devid == alias) 227 return 0; 228 229 iommu = rlookup_amd_iommu(&pdev->dev); 230 if (!iommu) 231 return 0; 232 233 amd_iommu_set_rlookup_table(iommu, alias); 234 dev_table = get_dev_table(iommu); 235 memcpy(dev_table[alias].data, 236 dev_table[devid].data, 237 sizeof(dev_table[alias].data)); 238 239 return 0; 240 } 241 242 static void clone_aliases(struct amd_iommu *iommu, struct device *dev) 243 { 244 struct pci_dev *pdev; 245 246 if (!dev_is_pci(dev)) 247 return; 248 pdev = to_pci_dev(dev); 249 250 /* 251 * The IVRS alias stored in the alias table may not be 252 * part of the PCI DMA aliases if it's bus differs 253 * from the original device. 254 */ 255 clone_alias(pdev, iommu->pci_seg->alias_table[pci_dev_id(pdev)], NULL); 256 257 pci_for_each_dma_alias(pdev, clone_alias, NULL); 258 } 259 260 static void setup_aliases(struct amd_iommu *iommu, struct device *dev) 261 { 262 struct pci_dev *pdev = to_pci_dev(dev); 263 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 264 u16 ivrs_alias; 265 266 /* For ACPI HID devices, there are no aliases */ 267 if (!dev_is_pci(dev)) 268 return; 269 270 /* 271 * Add the IVRS alias to the pci aliases if it is on the same 272 * bus. The IVRS table may know about a quirk that we don't. 273 */ 274 ivrs_alias = pci_seg->alias_table[pci_dev_id(pdev)]; 275 if (ivrs_alias != pci_dev_id(pdev) && 276 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) 277 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1); 278 279 clone_aliases(iommu, dev); 280 } 281 282 static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid) 283 { 284 struct iommu_dev_data *dev_data; 285 286 dev_data = search_dev_data(iommu, devid); 287 288 if (dev_data == NULL) { 289 dev_data = alloc_dev_data(iommu, devid); 290 if (!dev_data) 291 return NULL; 292 293 if (translation_pre_enabled(iommu)) 294 dev_data->defer_attach = true; 295 } 296 297 return dev_data; 298 } 299 300 /* 301 * Find or create an IOMMU group for a acpihid device. 302 */ 303 static struct iommu_group *acpihid_device_group(struct device *dev) 304 { 305 struct acpihid_map_entry *p, *entry = NULL; 306 int devid; 307 308 devid = get_acpihid_device_id(dev, &entry); 309 if (devid < 0) 310 return ERR_PTR(devid); 311 312 list_for_each_entry(p, &acpihid_map, list) { 313 if ((devid == p->devid) && p->group) 314 entry->group = p->group; 315 } 316 317 if (!entry->group) 318 entry->group = generic_device_group(dev); 319 else 320 iommu_group_ref_get(entry->group); 321 322 return entry->group; 323 } 324 325 static bool pci_iommuv2_capable(struct pci_dev *pdev) 326 { 327 static const int caps[] = { 328 PCI_EXT_CAP_ID_PRI, 329 PCI_EXT_CAP_ID_PASID, 330 }; 331 int i, pos; 332 333 if (!pci_ats_supported(pdev)) 334 return false; 335 336 for (i = 0; i < 2; ++i) { 337 pos = pci_find_ext_capability(pdev, caps[i]); 338 if (pos == 0) 339 return false; 340 } 341 342 return true; 343 } 344 345 /* 346 * This function checks if the driver got a valid device from the caller to 347 * avoid dereferencing invalid pointers. 348 */ 349 static bool check_device(struct device *dev) 350 { 351 struct amd_iommu_pci_seg *pci_seg; 352 struct amd_iommu *iommu; 353 int devid, sbdf; 354 355 if (!dev) 356 return false; 357 358 sbdf = get_device_sbdf_id(dev); 359 if (sbdf < 0) 360 return false; 361 devid = PCI_SBDF_TO_DEVID(sbdf); 362 363 iommu = rlookup_amd_iommu(dev); 364 if (!iommu) 365 return false; 366 367 /* Out of our scope? */ 368 pci_seg = iommu->pci_seg; 369 if (devid > pci_seg->last_bdf) 370 return false; 371 372 return true; 373 } 374 375 static int iommu_init_device(struct amd_iommu *iommu, struct device *dev) 376 { 377 struct iommu_dev_data *dev_data; 378 int devid, sbdf; 379 380 if (dev_iommu_priv_get(dev)) 381 return 0; 382 383 sbdf = get_device_sbdf_id(dev); 384 if (sbdf < 0) 385 return sbdf; 386 387 devid = PCI_SBDF_TO_DEVID(sbdf); 388 dev_data = find_dev_data(iommu, devid); 389 if (!dev_data) 390 return -ENOMEM; 391 392 dev_data->dev = dev; 393 setup_aliases(iommu, dev); 394 395 /* 396 * By default we use passthrough mode for IOMMUv2 capable device. 397 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to 398 * invalid address), we ignore the capability for the device so 399 * it'll be forced to go into translation mode. 400 */ 401 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) && 402 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { 403 dev_data->iommu_v2 = iommu->is_iommu_v2; 404 } 405 406 dev_iommu_priv_set(dev, dev_data); 407 408 return 0; 409 } 410 411 static void iommu_ignore_device(struct amd_iommu *iommu, struct device *dev) 412 { 413 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 414 struct dev_table_entry *dev_table = get_dev_table(iommu); 415 int devid, sbdf; 416 417 sbdf = get_device_sbdf_id(dev); 418 if (sbdf < 0) 419 return; 420 421 devid = PCI_SBDF_TO_DEVID(sbdf); 422 pci_seg->rlookup_table[devid] = NULL; 423 memset(&dev_table[devid], 0, sizeof(struct dev_table_entry)); 424 425 setup_aliases(iommu, dev); 426 } 427 428 static void amd_iommu_uninit_device(struct device *dev) 429 { 430 struct iommu_dev_data *dev_data; 431 432 dev_data = dev_iommu_priv_get(dev); 433 if (!dev_data) 434 return; 435 436 if (dev_data->domain) 437 detach_device(dev); 438 439 dev_iommu_priv_set(dev, NULL); 440 441 /* 442 * We keep dev_data around for unplugged devices and reuse it when the 443 * device is re-plugged - not doing so would introduce a ton of races. 444 */ 445 } 446 447 /**************************************************************************** 448 * 449 * Interrupt handling functions 450 * 451 ****************************************************************************/ 452 453 static void dump_dte_entry(struct amd_iommu *iommu, u16 devid) 454 { 455 int i; 456 struct dev_table_entry *dev_table = get_dev_table(iommu); 457 458 for (i = 0; i < 4; ++i) 459 pr_err("DTE[%d]: %016llx\n", i, dev_table[devid].data[i]); 460 } 461 462 static void dump_command(unsigned long phys_addr) 463 { 464 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr); 465 int i; 466 467 for (i = 0; i < 4; ++i) 468 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]); 469 } 470 471 static void amd_iommu_report_rmp_hw_error(struct amd_iommu *iommu, volatile u32 *event) 472 { 473 struct iommu_dev_data *dev_data = NULL; 474 int devid, vmg_tag, flags; 475 struct pci_dev *pdev; 476 u64 spa; 477 478 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; 479 vmg_tag = (event[1]) & 0xFFFF; 480 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; 481 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8); 482 483 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), 484 devid & 0xff); 485 if (pdev) 486 dev_data = dev_iommu_priv_get(&pdev->dev); 487 488 if (dev_data) { 489 if (__ratelimit(&dev_data->rs)) { 490 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n", 491 vmg_tag, spa, flags); 492 } 493 } else { 494 pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n", 495 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 496 vmg_tag, spa, flags); 497 } 498 499 if (pdev) 500 pci_dev_put(pdev); 501 } 502 503 static void amd_iommu_report_rmp_fault(struct amd_iommu *iommu, volatile u32 *event) 504 { 505 struct iommu_dev_data *dev_data = NULL; 506 int devid, flags_rmp, vmg_tag, flags; 507 struct pci_dev *pdev; 508 u64 gpa; 509 510 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; 511 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF; 512 vmg_tag = (event[1]) & 0xFFFF; 513 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; 514 gpa = ((u64)event[3] << 32) | event[2]; 515 516 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), 517 devid & 0xff); 518 if (pdev) 519 dev_data = dev_iommu_priv_get(&pdev->dev); 520 521 if (dev_data) { 522 if (__ratelimit(&dev_data->rs)) { 523 pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n", 524 vmg_tag, gpa, flags_rmp, flags); 525 } 526 } else { 527 pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n", 528 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 529 vmg_tag, gpa, flags_rmp, flags); 530 } 531 532 if (pdev) 533 pci_dev_put(pdev); 534 } 535 536 #define IS_IOMMU_MEM_TRANSACTION(flags) \ 537 (((flags) & EVENT_FLAG_I) == 0) 538 539 #define IS_WRITE_REQUEST(flags) \ 540 ((flags) & EVENT_FLAG_RW) 541 542 static void amd_iommu_report_page_fault(struct amd_iommu *iommu, 543 u16 devid, u16 domain_id, 544 u64 address, int flags) 545 { 546 struct iommu_dev_data *dev_data = NULL; 547 struct pci_dev *pdev; 548 549 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), 550 devid & 0xff); 551 if (pdev) 552 dev_data = dev_iommu_priv_get(&pdev->dev); 553 554 if (dev_data) { 555 /* 556 * If this is a DMA fault (for which the I(nterrupt) 557 * bit will be unset), allow report_iommu_fault() to 558 * prevent logging it. 559 */ 560 if (IS_IOMMU_MEM_TRANSACTION(flags)) { 561 /* Device not attached to domain properly */ 562 if (dev_data->domain == NULL) { 563 pr_err_ratelimited("Event logged [Device not attached to domain properly]\n"); 564 pr_err_ratelimited(" device=%04x:%02x:%02x.%x domain=0x%04x\n", 565 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), 566 PCI_FUNC(devid), domain_id); 567 goto out; 568 } 569 570 if (!report_iommu_fault(&dev_data->domain->domain, 571 &pdev->dev, address, 572 IS_WRITE_REQUEST(flags) ? 573 IOMMU_FAULT_WRITE : 574 IOMMU_FAULT_READ)) 575 goto out; 576 } 577 578 if (__ratelimit(&dev_data->rs)) { 579 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n", 580 domain_id, address, flags); 581 } 582 } else { 583 pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=%04x:%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n", 584 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 585 domain_id, address, flags); 586 } 587 588 out: 589 if (pdev) 590 pci_dev_put(pdev); 591 } 592 593 static void iommu_print_event(struct amd_iommu *iommu, void *__evt) 594 { 595 struct device *dev = iommu->iommu.dev; 596 int type, devid, flags, tag; 597 volatile u32 *event = __evt; 598 int count = 0; 599 u64 address; 600 u32 pasid; 601 602 retry: 603 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; 604 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; 605 pasid = (event[0] & EVENT_DOMID_MASK_HI) | 606 (event[1] & EVENT_DOMID_MASK_LO); 607 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; 608 address = (u64)(((u64)event[3]) << 32) | event[2]; 609 610 if (type == 0) { 611 /* Did we hit the erratum? */ 612 if (++count == LOOP_TIMEOUT) { 613 pr_err("No event written to event log\n"); 614 return; 615 } 616 udelay(1); 617 goto retry; 618 } 619 620 if (type == EVENT_TYPE_IO_FAULT) { 621 amd_iommu_report_page_fault(iommu, devid, pasid, address, flags); 622 return; 623 } 624 625 switch (type) { 626 case EVENT_TYPE_ILL_DEV: 627 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", 628 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 629 pasid, address, flags); 630 dump_dte_entry(iommu, devid); 631 break; 632 case EVENT_TYPE_DEV_TAB_ERR: 633 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x " 634 "address=0x%llx flags=0x%04x]\n", 635 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 636 address, flags); 637 break; 638 case EVENT_TYPE_PAGE_TAB_ERR: 639 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n", 640 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 641 pasid, address, flags); 642 break; 643 case EVENT_TYPE_ILL_CMD: 644 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address); 645 dump_command(address); 646 break; 647 case EVENT_TYPE_CMD_HARD_ERR: 648 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n", 649 address, flags); 650 break; 651 case EVENT_TYPE_IOTLB_INV_TO: 652 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%04x:%02x:%02x.%x address=0x%llx]\n", 653 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 654 address); 655 break; 656 case EVENT_TYPE_INV_DEV_REQ: 657 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", 658 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 659 pasid, address, flags); 660 break; 661 case EVENT_TYPE_RMP_FAULT: 662 amd_iommu_report_rmp_fault(iommu, event); 663 break; 664 case EVENT_TYPE_RMP_HW_ERR: 665 amd_iommu_report_rmp_hw_error(iommu, event); 666 break; 667 case EVENT_TYPE_INV_PPR_REQ: 668 pasid = PPR_PASID(*((u64 *)__evt)); 669 tag = event[1] & 0x03FF; 670 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n", 671 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), 672 pasid, address, flags, tag); 673 break; 674 default: 675 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n", 676 event[0], event[1], event[2], event[3]); 677 } 678 679 /* 680 * To detect the hardware errata 732 we need to clear the 681 * entry back to zero. This issue does not exist on SNP 682 * enabled system. Also this buffer is not writeable on 683 * SNP enabled system. 684 */ 685 if (!amd_iommu_snp_en) 686 memset(__evt, 0, 4 * sizeof(u32)); 687 } 688 689 static void iommu_poll_events(struct amd_iommu *iommu) 690 { 691 u32 head, tail; 692 693 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 694 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 695 696 while (head != tail) { 697 iommu_print_event(iommu, iommu->evt_buf + head); 698 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; 699 } 700 701 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 702 } 703 704 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) 705 { 706 struct amd_iommu_fault fault; 707 708 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { 709 pr_err_ratelimited("Unknown PPR request received\n"); 710 return; 711 } 712 713 fault.address = raw[1]; 714 fault.pasid = PPR_PASID(raw[0]); 715 fault.sbdf = PCI_SEG_DEVID_TO_SBDF(iommu->pci_seg->id, PPR_DEVID(raw[0])); 716 fault.tag = PPR_TAG(raw[0]); 717 fault.flags = PPR_FLAGS(raw[0]); 718 719 atomic_notifier_call_chain(&ppr_notifier, 0, &fault); 720 } 721 722 static void iommu_poll_ppr_log(struct amd_iommu *iommu) 723 { 724 u32 head, tail; 725 726 if (iommu->ppr_log == NULL) 727 return; 728 729 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 730 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 731 732 while (head != tail) { 733 volatile u64 *raw; 734 u64 entry[2]; 735 int i; 736 737 raw = (u64 *)(iommu->ppr_log + head); 738 739 /* 740 * Hardware bug: Interrupt may arrive before the entry is 741 * written to memory. If this happens we need to wait for the 742 * entry to arrive. 743 */ 744 for (i = 0; i < LOOP_TIMEOUT; ++i) { 745 if (PPR_REQ_TYPE(raw[0]) != 0) 746 break; 747 udelay(1); 748 } 749 750 /* Avoid memcpy function-call overhead */ 751 entry[0] = raw[0]; 752 entry[1] = raw[1]; 753 754 /* 755 * To detect the hardware errata 733 we need to clear the 756 * entry back to zero. This issue does not exist on SNP 757 * enabled system. Also this buffer is not writeable on 758 * SNP enabled system. 759 */ 760 if (!amd_iommu_snp_en) 761 raw[0] = raw[1] = 0UL; 762 763 /* Update head pointer of hardware ring-buffer */ 764 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; 765 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 766 767 /* Handle PPR entry */ 768 iommu_handle_ppr_entry(iommu, entry); 769 770 /* Refresh ring-buffer information */ 771 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 772 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 773 } 774 } 775 776 #ifdef CONFIG_IRQ_REMAP 777 static int (*iommu_ga_log_notifier)(u32); 778 779 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) 780 { 781 iommu_ga_log_notifier = notifier; 782 783 return 0; 784 } 785 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); 786 787 static void iommu_poll_ga_log(struct amd_iommu *iommu) 788 { 789 u32 head, tail; 790 791 if (iommu->ga_log == NULL) 792 return; 793 794 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 795 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 796 797 while (head != tail) { 798 volatile u64 *raw; 799 u64 log_entry; 800 801 raw = (u64 *)(iommu->ga_log + head); 802 803 /* Avoid memcpy function-call overhead */ 804 log_entry = *raw; 805 806 /* Update head pointer of hardware ring-buffer */ 807 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; 808 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 809 810 /* Handle GA entry */ 811 switch (GA_REQ_TYPE(log_entry)) { 812 case GA_GUEST_NR: 813 if (!iommu_ga_log_notifier) 814 break; 815 816 pr_debug("%s: devid=%#x, ga_tag=%#x\n", 817 __func__, GA_DEVID(log_entry), 818 GA_TAG(log_entry)); 819 820 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) 821 pr_err("GA log notifier failed.\n"); 822 break; 823 default: 824 break; 825 } 826 } 827 } 828 829 static void 830 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) 831 { 832 if (!irq_remapping_enabled || !dev_is_pci(dev) || 833 !pci_dev_has_default_msi_parent_domain(to_pci_dev(dev))) 834 return; 835 836 dev_set_msi_domain(dev, iommu->ir_domain); 837 } 838 839 #else /* CONFIG_IRQ_REMAP */ 840 static inline void 841 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { } 842 #endif /* !CONFIG_IRQ_REMAP */ 843 844 #define AMD_IOMMU_INT_MASK \ 845 (MMIO_STATUS_EVT_OVERFLOW_INT_MASK | \ 846 MMIO_STATUS_EVT_INT_MASK | \ 847 MMIO_STATUS_PPR_INT_MASK | \ 848 MMIO_STATUS_GALOG_INT_MASK) 849 850 irqreturn_t amd_iommu_int_thread(int irq, void *data) 851 { 852 struct amd_iommu *iommu = (struct amd_iommu *) data; 853 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 854 855 while (status & AMD_IOMMU_INT_MASK) { 856 /* Enable interrupt sources again */ 857 writel(AMD_IOMMU_INT_MASK, 858 iommu->mmio_base + MMIO_STATUS_OFFSET); 859 860 if (status & MMIO_STATUS_EVT_INT_MASK) { 861 pr_devel("Processing IOMMU Event Log\n"); 862 iommu_poll_events(iommu); 863 } 864 865 if (status & MMIO_STATUS_PPR_INT_MASK) { 866 pr_devel("Processing IOMMU PPR Log\n"); 867 iommu_poll_ppr_log(iommu); 868 } 869 870 #ifdef CONFIG_IRQ_REMAP 871 if (status & MMIO_STATUS_GALOG_INT_MASK) { 872 pr_devel("Processing IOMMU GA Log\n"); 873 iommu_poll_ga_log(iommu); 874 } 875 #endif 876 877 if (status & MMIO_STATUS_EVT_OVERFLOW_INT_MASK) { 878 pr_info_ratelimited("IOMMU event log overflow\n"); 879 amd_iommu_restart_event_logging(iommu); 880 } 881 882 /* 883 * Hardware bug: ERBT1312 884 * When re-enabling interrupt (by writing 1 885 * to clear the bit), the hardware might also try to set 886 * the interrupt bit in the event status register. 887 * In this scenario, the bit will be set, and disable 888 * subsequent interrupts. 889 * 890 * Workaround: The IOMMU driver should read back the 891 * status register and check if the interrupt bits are cleared. 892 * If not, driver will need to go through the interrupt handler 893 * again and re-clear the bits 894 */ 895 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 896 } 897 return IRQ_HANDLED; 898 } 899 900 irqreturn_t amd_iommu_int_handler(int irq, void *data) 901 { 902 return IRQ_WAKE_THREAD; 903 } 904 905 /**************************************************************************** 906 * 907 * IOMMU command queuing functions 908 * 909 ****************************************************************************/ 910 911 static int wait_on_sem(struct amd_iommu *iommu, u64 data) 912 { 913 int i = 0; 914 915 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) { 916 udelay(1); 917 i += 1; 918 } 919 920 if (i == LOOP_TIMEOUT) { 921 pr_alert("Completion-Wait loop timed out\n"); 922 return -EIO; 923 } 924 925 return 0; 926 } 927 928 static void copy_cmd_to_buffer(struct amd_iommu *iommu, 929 struct iommu_cmd *cmd) 930 { 931 u8 *target; 932 u32 tail; 933 934 /* Copy command to buffer */ 935 tail = iommu->cmd_buf_tail; 936 target = iommu->cmd_buf + tail; 937 memcpy(target, cmd, sizeof(*cmd)); 938 939 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; 940 iommu->cmd_buf_tail = tail; 941 942 /* Tell the IOMMU about it */ 943 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 944 } 945 946 static void build_completion_wait(struct iommu_cmd *cmd, 947 struct amd_iommu *iommu, 948 u64 data) 949 { 950 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem); 951 952 memset(cmd, 0, sizeof(*cmd)); 953 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; 954 cmd->data[1] = upper_32_bits(paddr); 955 cmd->data[2] = lower_32_bits(data); 956 cmd->data[3] = upper_32_bits(data); 957 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); 958 } 959 960 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) 961 { 962 memset(cmd, 0, sizeof(*cmd)); 963 cmd->data[0] = devid; 964 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); 965 } 966 967 /* 968 * Builds an invalidation address which is suitable for one page or multiple 969 * pages. Sets the size bit (S) as needed is more than one page is flushed. 970 */ 971 static inline u64 build_inv_address(u64 address, size_t size) 972 { 973 u64 pages, end, msb_diff; 974 975 pages = iommu_num_pages(address, size, PAGE_SIZE); 976 977 if (pages == 1) 978 return address & PAGE_MASK; 979 980 end = address + size - 1; 981 982 /* 983 * msb_diff would hold the index of the most significant bit that 984 * flipped between the start and end. 985 */ 986 msb_diff = fls64(end ^ address) - 1; 987 988 /* 989 * Bits 63:52 are sign extended. If for some reason bit 51 is different 990 * between the start and the end, invalidate everything. 991 */ 992 if (unlikely(msb_diff > 51)) { 993 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; 994 } else { 995 /* 996 * The msb-bit must be clear on the address. Just set all the 997 * lower bits. 998 */ 999 address |= (1ull << msb_diff) - 1; 1000 } 1001 1002 /* Clear bits 11:0 */ 1003 address &= PAGE_MASK; 1004 1005 /* Set the size bit - we flush more than one 4kb page */ 1006 return address | CMD_INV_IOMMU_PAGES_SIZE_MASK; 1007 } 1008 1009 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, 1010 size_t size, u16 domid, int pde) 1011 { 1012 u64 inv_address = build_inv_address(address, size); 1013 1014 memset(cmd, 0, sizeof(*cmd)); 1015 cmd->data[1] |= domid; 1016 cmd->data[2] = lower_32_bits(inv_address); 1017 cmd->data[3] = upper_32_bits(inv_address); 1018 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); 1019 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ 1020 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; 1021 } 1022 1023 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, 1024 u64 address, size_t size) 1025 { 1026 u64 inv_address = build_inv_address(address, size); 1027 1028 memset(cmd, 0, sizeof(*cmd)); 1029 cmd->data[0] = devid; 1030 cmd->data[0] |= (qdep & 0xff) << 24; 1031 cmd->data[1] = devid; 1032 cmd->data[2] = lower_32_bits(inv_address); 1033 cmd->data[3] = upper_32_bits(inv_address); 1034 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); 1035 } 1036 1037 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid, 1038 u64 address, bool size) 1039 { 1040 memset(cmd, 0, sizeof(*cmd)); 1041 1042 address &= ~(0xfffULL); 1043 1044 cmd->data[0] = pasid; 1045 cmd->data[1] = domid; 1046 cmd->data[2] = lower_32_bits(address); 1047 cmd->data[3] = upper_32_bits(address); 1048 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; 1049 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; 1050 if (size) 1051 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; 1052 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); 1053 } 1054 1055 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid, 1056 int qdep, u64 address, bool size) 1057 { 1058 memset(cmd, 0, sizeof(*cmd)); 1059 1060 address &= ~(0xfffULL); 1061 1062 cmd->data[0] = devid; 1063 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; 1064 cmd->data[0] |= (qdep & 0xff) << 24; 1065 cmd->data[1] = devid; 1066 cmd->data[1] |= (pasid & 0xff) << 16; 1067 cmd->data[2] = lower_32_bits(address); 1068 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; 1069 cmd->data[3] = upper_32_bits(address); 1070 if (size) 1071 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; 1072 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); 1073 } 1074 1075 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid, 1076 int status, int tag, bool gn) 1077 { 1078 memset(cmd, 0, sizeof(*cmd)); 1079 1080 cmd->data[0] = devid; 1081 if (gn) { 1082 cmd->data[1] = pasid; 1083 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; 1084 } 1085 cmd->data[3] = tag & 0x1ff; 1086 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; 1087 1088 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); 1089 } 1090 1091 static void build_inv_all(struct iommu_cmd *cmd) 1092 { 1093 memset(cmd, 0, sizeof(*cmd)); 1094 CMD_SET_TYPE(cmd, CMD_INV_ALL); 1095 } 1096 1097 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) 1098 { 1099 memset(cmd, 0, sizeof(*cmd)); 1100 cmd->data[0] = devid; 1101 CMD_SET_TYPE(cmd, CMD_INV_IRT); 1102 } 1103 1104 /* 1105 * Writes the command to the IOMMUs command buffer and informs the 1106 * hardware about the new command. 1107 */ 1108 static int __iommu_queue_command_sync(struct amd_iommu *iommu, 1109 struct iommu_cmd *cmd, 1110 bool sync) 1111 { 1112 unsigned int count = 0; 1113 u32 left, next_tail; 1114 1115 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; 1116 again: 1117 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; 1118 1119 if (left <= 0x20) { 1120 /* Skip udelay() the first time around */ 1121 if (count++) { 1122 if (count == LOOP_TIMEOUT) { 1123 pr_err("Command buffer timeout\n"); 1124 return -EIO; 1125 } 1126 1127 udelay(1); 1128 } 1129 1130 /* Update head and recheck remaining space */ 1131 iommu->cmd_buf_head = readl(iommu->mmio_base + 1132 MMIO_CMD_HEAD_OFFSET); 1133 1134 goto again; 1135 } 1136 1137 copy_cmd_to_buffer(iommu, cmd); 1138 1139 /* Do we need to make sure all commands are processed? */ 1140 iommu->need_sync = sync; 1141 1142 return 0; 1143 } 1144 1145 static int iommu_queue_command_sync(struct amd_iommu *iommu, 1146 struct iommu_cmd *cmd, 1147 bool sync) 1148 { 1149 unsigned long flags; 1150 int ret; 1151 1152 raw_spin_lock_irqsave(&iommu->lock, flags); 1153 ret = __iommu_queue_command_sync(iommu, cmd, sync); 1154 raw_spin_unlock_irqrestore(&iommu->lock, flags); 1155 1156 return ret; 1157 } 1158 1159 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) 1160 { 1161 return iommu_queue_command_sync(iommu, cmd, true); 1162 } 1163 1164 /* 1165 * This function queues a completion wait command into the command 1166 * buffer of an IOMMU 1167 */ 1168 static int iommu_completion_wait(struct amd_iommu *iommu) 1169 { 1170 struct iommu_cmd cmd; 1171 unsigned long flags; 1172 int ret; 1173 u64 data; 1174 1175 if (!iommu->need_sync) 1176 return 0; 1177 1178 raw_spin_lock_irqsave(&iommu->lock, flags); 1179 1180 data = ++iommu->cmd_sem_val; 1181 build_completion_wait(&cmd, iommu, data); 1182 1183 ret = __iommu_queue_command_sync(iommu, &cmd, false); 1184 if (ret) 1185 goto out_unlock; 1186 1187 ret = wait_on_sem(iommu, data); 1188 1189 out_unlock: 1190 raw_spin_unlock_irqrestore(&iommu->lock, flags); 1191 1192 return ret; 1193 } 1194 1195 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) 1196 { 1197 struct iommu_cmd cmd; 1198 1199 build_inv_dte(&cmd, devid); 1200 1201 return iommu_queue_command(iommu, &cmd); 1202 } 1203 1204 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) 1205 { 1206 u32 devid; 1207 u16 last_bdf = iommu->pci_seg->last_bdf; 1208 1209 for (devid = 0; devid <= last_bdf; ++devid) 1210 iommu_flush_dte(iommu, devid); 1211 1212 iommu_completion_wait(iommu); 1213 } 1214 1215 /* 1216 * This function uses heavy locking and may disable irqs for some time. But 1217 * this is no issue because it is only called during resume. 1218 */ 1219 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu) 1220 { 1221 u32 dom_id; 1222 u16 last_bdf = iommu->pci_seg->last_bdf; 1223 1224 for (dom_id = 0; dom_id <= last_bdf; ++dom_id) { 1225 struct iommu_cmd cmd; 1226 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1227 dom_id, 1); 1228 iommu_queue_command(iommu, &cmd); 1229 } 1230 1231 iommu_completion_wait(iommu); 1232 } 1233 1234 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id) 1235 { 1236 struct iommu_cmd cmd; 1237 1238 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1239 dom_id, 1); 1240 iommu_queue_command(iommu, &cmd); 1241 1242 iommu_completion_wait(iommu); 1243 } 1244 1245 static void amd_iommu_flush_all(struct amd_iommu *iommu) 1246 { 1247 struct iommu_cmd cmd; 1248 1249 build_inv_all(&cmd); 1250 1251 iommu_queue_command(iommu, &cmd); 1252 iommu_completion_wait(iommu); 1253 } 1254 1255 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) 1256 { 1257 struct iommu_cmd cmd; 1258 1259 build_inv_irt(&cmd, devid); 1260 1261 iommu_queue_command(iommu, &cmd); 1262 } 1263 1264 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) 1265 { 1266 u32 devid; 1267 u16 last_bdf = iommu->pci_seg->last_bdf; 1268 1269 for (devid = 0; devid <= last_bdf; devid++) 1270 iommu_flush_irt(iommu, devid); 1271 1272 iommu_completion_wait(iommu); 1273 } 1274 1275 void iommu_flush_all_caches(struct amd_iommu *iommu) 1276 { 1277 if (iommu_feature(iommu, FEATURE_IA)) { 1278 amd_iommu_flush_all(iommu); 1279 } else { 1280 amd_iommu_flush_dte_all(iommu); 1281 amd_iommu_flush_irt_all(iommu); 1282 amd_iommu_flush_tlb_all(iommu); 1283 } 1284 } 1285 1286 /* 1287 * Command send function for flushing on-device TLB 1288 */ 1289 static int device_flush_iotlb(struct iommu_dev_data *dev_data, 1290 u64 address, size_t size) 1291 { 1292 struct amd_iommu *iommu; 1293 struct iommu_cmd cmd; 1294 int qdep; 1295 1296 qdep = dev_data->ats.qdep; 1297 iommu = rlookup_amd_iommu(dev_data->dev); 1298 if (!iommu) 1299 return -EINVAL; 1300 1301 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); 1302 1303 return iommu_queue_command(iommu, &cmd); 1304 } 1305 1306 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data) 1307 { 1308 struct amd_iommu *iommu = data; 1309 1310 return iommu_flush_dte(iommu, alias); 1311 } 1312 1313 /* 1314 * Command send function for invalidating a device table entry 1315 */ 1316 static int device_flush_dte(struct iommu_dev_data *dev_data) 1317 { 1318 struct amd_iommu *iommu; 1319 struct pci_dev *pdev = NULL; 1320 struct amd_iommu_pci_seg *pci_seg; 1321 u16 alias; 1322 int ret; 1323 1324 iommu = rlookup_amd_iommu(dev_data->dev); 1325 if (!iommu) 1326 return -EINVAL; 1327 1328 if (dev_is_pci(dev_data->dev)) 1329 pdev = to_pci_dev(dev_data->dev); 1330 1331 if (pdev) 1332 ret = pci_for_each_dma_alias(pdev, 1333 device_flush_dte_alias, iommu); 1334 else 1335 ret = iommu_flush_dte(iommu, dev_data->devid); 1336 if (ret) 1337 return ret; 1338 1339 pci_seg = iommu->pci_seg; 1340 alias = pci_seg->alias_table[dev_data->devid]; 1341 if (alias != dev_data->devid) { 1342 ret = iommu_flush_dte(iommu, alias); 1343 if (ret) 1344 return ret; 1345 } 1346 1347 if (dev_data->ats.enabled) 1348 ret = device_flush_iotlb(dev_data, 0, ~0UL); 1349 1350 return ret; 1351 } 1352 1353 /* 1354 * TLB invalidation function which is called from the mapping functions. 1355 * It invalidates a single PTE if the range to flush is within a single 1356 * page. Otherwise it flushes the whole TLB of the IOMMU. 1357 */ 1358 static void __domain_flush_pages(struct protection_domain *domain, 1359 u64 address, size_t size, int pde) 1360 { 1361 struct iommu_dev_data *dev_data; 1362 struct iommu_cmd cmd; 1363 int ret = 0, i; 1364 1365 build_inv_iommu_pages(&cmd, address, size, domain->id, pde); 1366 1367 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { 1368 if (!domain->dev_iommu[i]) 1369 continue; 1370 1371 /* 1372 * Devices of this domain are behind this IOMMU 1373 * We need a TLB flush 1374 */ 1375 ret |= iommu_queue_command(amd_iommus[i], &cmd); 1376 } 1377 1378 list_for_each_entry(dev_data, &domain->dev_list, list) { 1379 1380 if (!dev_data->ats.enabled) 1381 continue; 1382 1383 ret |= device_flush_iotlb(dev_data, address, size); 1384 } 1385 1386 WARN_ON(ret); 1387 } 1388 1389 static void domain_flush_pages(struct protection_domain *domain, 1390 u64 address, size_t size, int pde) 1391 { 1392 if (likely(!amd_iommu_np_cache)) { 1393 __domain_flush_pages(domain, address, size, pde); 1394 return; 1395 } 1396 1397 /* 1398 * When NpCache is on, we infer that we run in a VM and use a vIOMMU. 1399 * In such setups it is best to avoid flushes of ranges which are not 1400 * naturally aligned, since it would lead to flushes of unmodified 1401 * PTEs. Such flushes would require the hypervisor to do more work than 1402 * necessary. Therefore, perform repeated flushes of aligned ranges 1403 * until you cover the range. Each iteration flushes the smaller 1404 * between the natural alignment of the address that we flush and the 1405 * greatest naturally aligned region that fits in the range. 1406 */ 1407 while (size != 0) { 1408 int addr_alignment = __ffs(address); 1409 int size_alignment = __fls(size); 1410 int min_alignment; 1411 size_t flush_size; 1412 1413 /* 1414 * size is always non-zero, but address might be zero, causing 1415 * addr_alignment to be negative. As the casting of the 1416 * argument in __ffs(address) to long might trim the high bits 1417 * of the address on x86-32, cast to long when doing the check. 1418 */ 1419 if (likely((unsigned long)address != 0)) 1420 min_alignment = min(addr_alignment, size_alignment); 1421 else 1422 min_alignment = size_alignment; 1423 1424 flush_size = 1ul << min_alignment; 1425 1426 __domain_flush_pages(domain, address, flush_size, pde); 1427 address += flush_size; 1428 size -= flush_size; 1429 } 1430 } 1431 1432 /* Flush the whole IO/TLB for a given protection domain - including PDE */ 1433 void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain) 1434 { 1435 domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); 1436 } 1437 1438 void amd_iommu_domain_flush_complete(struct protection_domain *domain) 1439 { 1440 int i; 1441 1442 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { 1443 if (domain && !domain->dev_iommu[i]) 1444 continue; 1445 1446 /* 1447 * Devices of this domain are behind this IOMMU 1448 * We need to wait for completion of all commands. 1449 */ 1450 iommu_completion_wait(amd_iommus[i]); 1451 } 1452 } 1453 1454 /* Flush the not present cache if it exists */ 1455 static void domain_flush_np_cache(struct protection_domain *domain, 1456 dma_addr_t iova, size_t size) 1457 { 1458 if (unlikely(amd_iommu_np_cache)) { 1459 unsigned long flags; 1460 1461 spin_lock_irqsave(&domain->lock, flags); 1462 domain_flush_pages(domain, iova, size, 1); 1463 amd_iommu_domain_flush_complete(domain); 1464 spin_unlock_irqrestore(&domain->lock, flags); 1465 } 1466 } 1467 1468 1469 /* 1470 * This function flushes the DTEs for all devices in domain 1471 */ 1472 static void domain_flush_devices(struct protection_domain *domain) 1473 { 1474 struct iommu_dev_data *dev_data; 1475 1476 list_for_each_entry(dev_data, &domain->dev_list, list) 1477 device_flush_dte(dev_data); 1478 } 1479 1480 /**************************************************************************** 1481 * 1482 * The next functions belong to the domain allocation. A domain is 1483 * allocated for every IOMMU as the default domain. If device isolation 1484 * is enabled, every device get its own domain. The most important thing 1485 * about domains is the page table mapping the DMA address space they 1486 * contain. 1487 * 1488 ****************************************************************************/ 1489 1490 static u16 domain_id_alloc(void) 1491 { 1492 int id; 1493 1494 spin_lock(&pd_bitmap_lock); 1495 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); 1496 BUG_ON(id == 0); 1497 if (id > 0 && id < MAX_DOMAIN_ID) 1498 __set_bit(id, amd_iommu_pd_alloc_bitmap); 1499 else 1500 id = 0; 1501 spin_unlock(&pd_bitmap_lock); 1502 1503 return id; 1504 } 1505 1506 static void domain_id_free(int id) 1507 { 1508 spin_lock(&pd_bitmap_lock); 1509 if (id > 0 && id < MAX_DOMAIN_ID) 1510 __clear_bit(id, amd_iommu_pd_alloc_bitmap); 1511 spin_unlock(&pd_bitmap_lock); 1512 } 1513 1514 static void free_gcr3_tbl_level1(u64 *tbl) 1515 { 1516 u64 *ptr; 1517 int i; 1518 1519 for (i = 0; i < 512; ++i) { 1520 if (!(tbl[i] & GCR3_VALID)) 1521 continue; 1522 1523 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); 1524 1525 free_page((unsigned long)ptr); 1526 } 1527 } 1528 1529 static void free_gcr3_tbl_level2(u64 *tbl) 1530 { 1531 u64 *ptr; 1532 int i; 1533 1534 for (i = 0; i < 512; ++i) { 1535 if (!(tbl[i] & GCR3_VALID)) 1536 continue; 1537 1538 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); 1539 1540 free_gcr3_tbl_level1(ptr); 1541 } 1542 } 1543 1544 static void free_gcr3_table(struct protection_domain *domain) 1545 { 1546 if (domain->glx == 2) 1547 free_gcr3_tbl_level2(domain->gcr3_tbl); 1548 else if (domain->glx == 1) 1549 free_gcr3_tbl_level1(domain->gcr3_tbl); 1550 else 1551 BUG_ON(domain->glx != 0); 1552 1553 free_page((unsigned long)domain->gcr3_tbl); 1554 } 1555 1556 static void set_dte_entry(struct amd_iommu *iommu, u16 devid, 1557 struct protection_domain *domain, bool ats, bool ppr) 1558 { 1559 u64 pte_root = 0; 1560 u64 flags = 0; 1561 u32 old_domid; 1562 struct dev_table_entry *dev_table = get_dev_table(iommu); 1563 1564 if (domain->iop.mode != PAGE_MODE_NONE) 1565 pte_root = iommu_virt_to_phys(domain->iop.root); 1566 1567 pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK) 1568 << DEV_ENTRY_MODE_SHIFT; 1569 1570 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V; 1571 1572 /* 1573 * When SNP is enabled, Only set TV bit when IOMMU 1574 * page translation is in use. 1575 */ 1576 if (!amd_iommu_snp_en || (domain->id != 0)) 1577 pte_root |= DTE_FLAG_TV; 1578 1579 flags = dev_table[devid].data[1]; 1580 1581 if (ats) 1582 flags |= DTE_FLAG_IOTLB; 1583 1584 if (ppr) { 1585 if (iommu_feature(iommu, FEATURE_EPHSUP)) 1586 pte_root |= 1ULL << DEV_ENTRY_PPR; 1587 } 1588 1589 if (domain->flags & PD_IOMMUV2_MASK) { 1590 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); 1591 u64 glx = domain->glx; 1592 u64 tmp; 1593 1594 pte_root |= DTE_FLAG_GV; 1595 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; 1596 1597 /* First mask out possible old values for GCR3 table */ 1598 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 1599 flags &= ~tmp; 1600 1601 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 1602 flags &= ~tmp; 1603 1604 /* Encode GCR3 table into DTE */ 1605 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; 1606 pte_root |= tmp; 1607 1608 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; 1609 flags |= tmp; 1610 1611 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; 1612 flags |= tmp; 1613 1614 if (amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) { 1615 dev_table[devid].data[2] |= 1616 ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); 1617 } 1618 1619 if (domain->flags & PD_GIOV_MASK) 1620 pte_root |= DTE_FLAG_GIOV; 1621 } 1622 1623 flags &= ~DEV_DOMID_MASK; 1624 flags |= domain->id; 1625 1626 old_domid = dev_table[devid].data[1] & DEV_DOMID_MASK; 1627 dev_table[devid].data[1] = flags; 1628 dev_table[devid].data[0] = pte_root; 1629 1630 /* 1631 * A kdump kernel might be replacing a domain ID that was copied from 1632 * the previous kernel--if so, it needs to flush the translation cache 1633 * entries for the old domain ID that is being overwritten 1634 */ 1635 if (old_domid) { 1636 amd_iommu_flush_tlb_domid(iommu, old_domid); 1637 } 1638 } 1639 1640 static void clear_dte_entry(struct amd_iommu *iommu, u16 devid) 1641 { 1642 struct dev_table_entry *dev_table = get_dev_table(iommu); 1643 1644 /* remove entry from the device table seen by the hardware */ 1645 dev_table[devid].data[0] = DTE_FLAG_V; 1646 1647 if (!amd_iommu_snp_en) 1648 dev_table[devid].data[0] |= DTE_FLAG_TV; 1649 1650 dev_table[devid].data[1] &= DTE_FLAG_MASK; 1651 1652 amd_iommu_apply_erratum_63(iommu, devid); 1653 } 1654 1655 static void do_attach(struct iommu_dev_data *dev_data, 1656 struct protection_domain *domain) 1657 { 1658 struct amd_iommu *iommu; 1659 bool ats; 1660 1661 iommu = rlookup_amd_iommu(dev_data->dev); 1662 if (!iommu) 1663 return; 1664 ats = dev_data->ats.enabled; 1665 1666 /* Update data structures */ 1667 dev_data->domain = domain; 1668 list_add(&dev_data->list, &domain->dev_list); 1669 1670 /* Update NUMA Node ID */ 1671 if (domain->nid == NUMA_NO_NODE) 1672 domain->nid = dev_to_node(dev_data->dev); 1673 1674 /* Do reference counting */ 1675 domain->dev_iommu[iommu->index] += 1; 1676 domain->dev_cnt += 1; 1677 1678 /* Update device table */ 1679 set_dte_entry(iommu, dev_data->devid, domain, 1680 ats, dev_data->iommu_v2); 1681 clone_aliases(iommu, dev_data->dev); 1682 1683 device_flush_dte(dev_data); 1684 } 1685 1686 static void do_detach(struct iommu_dev_data *dev_data) 1687 { 1688 struct protection_domain *domain = dev_data->domain; 1689 struct amd_iommu *iommu; 1690 1691 iommu = rlookup_amd_iommu(dev_data->dev); 1692 if (!iommu) 1693 return; 1694 1695 /* Update data structures */ 1696 dev_data->domain = NULL; 1697 list_del(&dev_data->list); 1698 clear_dte_entry(iommu, dev_data->devid); 1699 clone_aliases(iommu, dev_data->dev); 1700 1701 /* Flush the DTE entry */ 1702 device_flush_dte(dev_data); 1703 1704 /* Flush IOTLB */ 1705 amd_iommu_domain_flush_tlb_pde(domain); 1706 1707 /* Wait for the flushes to finish */ 1708 amd_iommu_domain_flush_complete(domain); 1709 1710 /* decrease reference counters - needs to happen after the flushes */ 1711 domain->dev_iommu[iommu->index] -= 1; 1712 domain->dev_cnt -= 1; 1713 } 1714 1715 static void pdev_iommuv2_disable(struct pci_dev *pdev) 1716 { 1717 pci_disable_ats(pdev); 1718 pci_disable_pri(pdev); 1719 pci_disable_pasid(pdev); 1720 } 1721 1722 static int pdev_pri_ats_enable(struct pci_dev *pdev) 1723 { 1724 int ret; 1725 1726 /* Only allow access to user-accessible pages */ 1727 ret = pci_enable_pasid(pdev, 0); 1728 if (ret) 1729 return ret; 1730 1731 /* First reset the PRI state of the device */ 1732 ret = pci_reset_pri(pdev); 1733 if (ret) 1734 goto out_err_pasid; 1735 1736 /* Enable PRI */ 1737 /* FIXME: Hardcode number of outstanding requests for now */ 1738 ret = pci_enable_pri(pdev, 32); 1739 if (ret) 1740 goto out_err_pasid; 1741 1742 ret = pci_enable_ats(pdev, PAGE_SHIFT); 1743 if (ret) 1744 goto out_err_pri; 1745 1746 return 0; 1747 1748 out_err_pri: 1749 pci_disable_pri(pdev); 1750 1751 out_err_pasid: 1752 pci_disable_pasid(pdev); 1753 1754 return ret; 1755 } 1756 1757 /* 1758 * If a device is not yet associated with a domain, this function makes the 1759 * device visible in the domain 1760 */ 1761 static int attach_device(struct device *dev, 1762 struct protection_domain *domain) 1763 { 1764 struct iommu_dev_data *dev_data; 1765 struct pci_dev *pdev; 1766 unsigned long flags; 1767 int ret; 1768 1769 spin_lock_irqsave(&domain->lock, flags); 1770 1771 dev_data = dev_iommu_priv_get(dev); 1772 1773 spin_lock(&dev_data->lock); 1774 1775 ret = -EBUSY; 1776 if (dev_data->domain != NULL) 1777 goto out; 1778 1779 if (!dev_is_pci(dev)) 1780 goto skip_ats_check; 1781 1782 pdev = to_pci_dev(dev); 1783 if (domain->flags & PD_IOMMUV2_MASK) { 1784 struct iommu_domain *def_domain = iommu_get_dma_domain(dev); 1785 1786 ret = -EINVAL; 1787 1788 /* 1789 * In case of using AMD_IOMMU_V1 page table mode and the device 1790 * is enabling for PPR/ATS support (using v2 table), 1791 * we need to make sure that the domain type is identity map. 1792 */ 1793 if ((amd_iommu_pgtable == AMD_IOMMU_V1) && 1794 def_domain->type != IOMMU_DOMAIN_IDENTITY) { 1795 goto out; 1796 } 1797 1798 if (dev_data->iommu_v2) { 1799 if (pdev_pri_ats_enable(pdev) != 0) 1800 goto out; 1801 1802 dev_data->ats.enabled = true; 1803 dev_data->ats.qdep = pci_ats_queue_depth(pdev); 1804 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev); 1805 } 1806 } else if (amd_iommu_iotlb_sup && 1807 pci_enable_ats(pdev, PAGE_SHIFT) == 0) { 1808 dev_data->ats.enabled = true; 1809 dev_data->ats.qdep = pci_ats_queue_depth(pdev); 1810 } 1811 1812 skip_ats_check: 1813 ret = 0; 1814 1815 do_attach(dev_data, domain); 1816 1817 /* 1818 * We might boot into a crash-kernel here. The crashed kernel 1819 * left the caches in the IOMMU dirty. So we have to flush 1820 * here to evict all dirty stuff. 1821 */ 1822 amd_iommu_domain_flush_tlb_pde(domain); 1823 1824 amd_iommu_domain_flush_complete(domain); 1825 1826 out: 1827 spin_unlock(&dev_data->lock); 1828 1829 spin_unlock_irqrestore(&domain->lock, flags); 1830 1831 return ret; 1832 } 1833 1834 /* 1835 * Removes a device from a protection domain (with devtable_lock held) 1836 */ 1837 static void detach_device(struct device *dev) 1838 { 1839 struct protection_domain *domain; 1840 struct iommu_dev_data *dev_data; 1841 unsigned long flags; 1842 1843 dev_data = dev_iommu_priv_get(dev); 1844 domain = dev_data->domain; 1845 1846 spin_lock_irqsave(&domain->lock, flags); 1847 1848 spin_lock(&dev_data->lock); 1849 1850 /* 1851 * First check if the device is still attached. It might already 1852 * be detached from its domain because the generic 1853 * iommu_detach_group code detached it and we try again here in 1854 * our alias handling. 1855 */ 1856 if (WARN_ON(!dev_data->domain)) 1857 goto out; 1858 1859 do_detach(dev_data); 1860 1861 if (!dev_is_pci(dev)) 1862 goto out; 1863 1864 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) 1865 pdev_iommuv2_disable(to_pci_dev(dev)); 1866 else if (dev_data->ats.enabled) 1867 pci_disable_ats(to_pci_dev(dev)); 1868 1869 dev_data->ats.enabled = false; 1870 1871 out: 1872 spin_unlock(&dev_data->lock); 1873 1874 spin_unlock_irqrestore(&domain->lock, flags); 1875 } 1876 1877 static struct iommu_device *amd_iommu_probe_device(struct device *dev) 1878 { 1879 struct iommu_device *iommu_dev; 1880 struct amd_iommu *iommu; 1881 int ret; 1882 1883 if (!check_device(dev)) 1884 return ERR_PTR(-ENODEV); 1885 1886 iommu = rlookup_amd_iommu(dev); 1887 if (!iommu) 1888 return ERR_PTR(-ENODEV); 1889 1890 /* Not registered yet? */ 1891 if (!iommu->iommu.ops) 1892 return ERR_PTR(-ENODEV); 1893 1894 if (dev_iommu_priv_get(dev)) 1895 return &iommu->iommu; 1896 1897 ret = iommu_init_device(iommu, dev); 1898 if (ret) { 1899 if (ret != -ENOTSUPP) 1900 dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); 1901 iommu_dev = ERR_PTR(ret); 1902 iommu_ignore_device(iommu, dev); 1903 } else { 1904 amd_iommu_set_pci_msi_domain(dev, iommu); 1905 iommu_dev = &iommu->iommu; 1906 } 1907 1908 iommu_completion_wait(iommu); 1909 1910 return iommu_dev; 1911 } 1912 1913 static void amd_iommu_probe_finalize(struct device *dev) 1914 { 1915 /* Domains are initialized for this device - have a look what we ended up with */ 1916 set_dma_ops(dev, NULL); 1917 iommu_setup_dma_ops(dev, 0, U64_MAX); 1918 } 1919 1920 static void amd_iommu_release_device(struct device *dev) 1921 { 1922 struct amd_iommu *iommu; 1923 1924 if (!check_device(dev)) 1925 return; 1926 1927 iommu = rlookup_amd_iommu(dev); 1928 if (!iommu) 1929 return; 1930 1931 amd_iommu_uninit_device(dev); 1932 iommu_completion_wait(iommu); 1933 } 1934 1935 static struct iommu_group *amd_iommu_device_group(struct device *dev) 1936 { 1937 if (dev_is_pci(dev)) 1938 return pci_device_group(dev); 1939 1940 return acpihid_device_group(dev); 1941 } 1942 1943 /***************************************************************************** 1944 * 1945 * The next functions belong to the dma_ops mapping/unmapping code. 1946 * 1947 *****************************************************************************/ 1948 1949 static void update_device_table(struct protection_domain *domain) 1950 { 1951 struct iommu_dev_data *dev_data; 1952 1953 list_for_each_entry(dev_data, &domain->dev_list, list) { 1954 struct amd_iommu *iommu = rlookup_amd_iommu(dev_data->dev); 1955 1956 if (!iommu) 1957 continue; 1958 set_dte_entry(iommu, dev_data->devid, domain, 1959 dev_data->ats.enabled, dev_data->iommu_v2); 1960 clone_aliases(iommu, dev_data->dev); 1961 } 1962 } 1963 1964 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain) 1965 { 1966 update_device_table(domain); 1967 domain_flush_devices(domain); 1968 } 1969 1970 void amd_iommu_domain_update(struct protection_domain *domain) 1971 { 1972 /* Update device table */ 1973 amd_iommu_update_and_flush_device_table(domain); 1974 1975 /* Flush domain TLB(s) and wait for completion */ 1976 amd_iommu_domain_flush_tlb_pde(domain); 1977 amd_iommu_domain_flush_complete(domain); 1978 } 1979 1980 /***************************************************************************** 1981 * 1982 * The following functions belong to the exported interface of AMD IOMMU 1983 * 1984 * This interface allows access to lower level functions of the IOMMU 1985 * like protection domain handling and assignement of devices to domains 1986 * which is not possible with the dma_ops interface. 1987 * 1988 *****************************************************************************/ 1989 1990 static void cleanup_domain(struct protection_domain *domain) 1991 { 1992 struct iommu_dev_data *entry; 1993 unsigned long flags; 1994 1995 spin_lock_irqsave(&domain->lock, flags); 1996 1997 while (!list_empty(&domain->dev_list)) { 1998 entry = list_first_entry(&domain->dev_list, 1999 struct iommu_dev_data, list); 2000 BUG_ON(!entry->domain); 2001 do_detach(entry); 2002 } 2003 2004 spin_unlock_irqrestore(&domain->lock, flags); 2005 } 2006 2007 static void protection_domain_free(struct protection_domain *domain) 2008 { 2009 if (!domain) 2010 return; 2011 2012 if (domain->iop.pgtbl_cfg.tlb) 2013 free_io_pgtable_ops(&domain->iop.iop.ops); 2014 2015 if (domain->id) 2016 domain_id_free(domain->id); 2017 2018 kfree(domain); 2019 } 2020 2021 static int protection_domain_init_v1(struct protection_domain *domain, int mode) 2022 { 2023 u64 *pt_root = NULL; 2024 2025 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL); 2026 2027 spin_lock_init(&domain->lock); 2028 domain->id = domain_id_alloc(); 2029 if (!domain->id) 2030 return -ENOMEM; 2031 INIT_LIST_HEAD(&domain->dev_list); 2032 2033 if (mode != PAGE_MODE_NONE) { 2034 pt_root = (void *)get_zeroed_page(GFP_KERNEL); 2035 if (!pt_root) { 2036 domain_id_free(domain->id); 2037 return -ENOMEM; 2038 } 2039 } 2040 2041 amd_iommu_domain_set_pgtable(domain, pt_root, mode); 2042 2043 return 0; 2044 } 2045 2046 static int protection_domain_init_v2(struct protection_domain *domain) 2047 { 2048 spin_lock_init(&domain->lock); 2049 domain->id = domain_id_alloc(); 2050 if (!domain->id) 2051 return -ENOMEM; 2052 INIT_LIST_HEAD(&domain->dev_list); 2053 2054 domain->flags |= PD_GIOV_MASK; 2055 2056 domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2; 2057 2058 if (domain_enable_v2(domain, 1)) { 2059 domain_id_free(domain->id); 2060 return -ENOMEM; 2061 } 2062 2063 return 0; 2064 } 2065 2066 static struct protection_domain *protection_domain_alloc(unsigned int type) 2067 { 2068 struct io_pgtable_ops *pgtbl_ops; 2069 struct protection_domain *domain; 2070 int pgtable = amd_iommu_pgtable; 2071 int mode = DEFAULT_PGTABLE_LEVEL; 2072 int ret; 2073 2074 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 2075 if (!domain) 2076 return NULL; 2077 2078 /* 2079 * Force IOMMU v1 page table when iommu=pt and 2080 * when allocating domain for pass-through devices. 2081 */ 2082 if (type == IOMMU_DOMAIN_IDENTITY) { 2083 pgtable = AMD_IOMMU_V1; 2084 mode = PAGE_MODE_NONE; 2085 } else if (type == IOMMU_DOMAIN_UNMANAGED) { 2086 pgtable = AMD_IOMMU_V1; 2087 } 2088 2089 switch (pgtable) { 2090 case AMD_IOMMU_V1: 2091 ret = protection_domain_init_v1(domain, mode); 2092 break; 2093 case AMD_IOMMU_V2: 2094 ret = protection_domain_init_v2(domain); 2095 break; 2096 default: 2097 ret = -EINVAL; 2098 } 2099 2100 if (ret) 2101 goto out_err; 2102 2103 /* No need to allocate io pgtable ops in passthrough mode */ 2104 if (type == IOMMU_DOMAIN_IDENTITY) 2105 return domain; 2106 2107 domain->nid = NUMA_NO_NODE; 2108 2109 pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain); 2110 if (!pgtbl_ops) { 2111 domain_id_free(domain->id); 2112 goto out_err; 2113 } 2114 2115 return domain; 2116 out_err: 2117 kfree(domain); 2118 return NULL; 2119 } 2120 2121 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) 2122 { 2123 struct protection_domain *domain; 2124 2125 /* 2126 * Since DTE[Mode]=0 is prohibited on SNP-enabled system, 2127 * default to use IOMMU_DOMAIN_DMA[_FQ]. 2128 */ 2129 if (amd_iommu_snp_en && (type == IOMMU_DOMAIN_IDENTITY)) 2130 return NULL; 2131 2132 domain = protection_domain_alloc(type); 2133 if (!domain) 2134 return NULL; 2135 2136 domain->domain.geometry.aperture_start = 0; 2137 domain->domain.geometry.aperture_end = ~0ULL; 2138 domain->domain.geometry.force_aperture = true; 2139 2140 return &domain->domain; 2141 } 2142 2143 static void amd_iommu_domain_free(struct iommu_domain *dom) 2144 { 2145 struct protection_domain *domain; 2146 2147 domain = to_pdomain(dom); 2148 2149 if (domain->dev_cnt > 0) 2150 cleanup_domain(domain); 2151 2152 BUG_ON(domain->dev_cnt != 0); 2153 2154 if (!dom) 2155 return; 2156 2157 if (domain->flags & PD_IOMMUV2_MASK) 2158 free_gcr3_table(domain); 2159 2160 protection_domain_free(domain); 2161 } 2162 2163 static int amd_iommu_attach_device(struct iommu_domain *dom, 2164 struct device *dev) 2165 { 2166 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); 2167 struct protection_domain *domain = to_pdomain(dom); 2168 struct amd_iommu *iommu = rlookup_amd_iommu(dev); 2169 int ret; 2170 2171 /* 2172 * Skip attach device to domain if new domain is same as 2173 * devices current domain 2174 */ 2175 if (dev_data->domain == domain) 2176 return 0; 2177 2178 dev_data->defer_attach = false; 2179 2180 if (dev_data->domain) 2181 detach_device(dev); 2182 2183 ret = attach_device(dev, domain); 2184 2185 #ifdef CONFIG_IRQ_REMAP 2186 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { 2187 if (dom->type == IOMMU_DOMAIN_UNMANAGED) 2188 dev_data->use_vapic = 1; 2189 else 2190 dev_data->use_vapic = 0; 2191 } 2192 #endif 2193 2194 iommu_completion_wait(iommu); 2195 2196 return ret; 2197 } 2198 2199 static void amd_iommu_iotlb_sync_map(struct iommu_domain *dom, 2200 unsigned long iova, size_t size) 2201 { 2202 struct protection_domain *domain = to_pdomain(dom); 2203 struct io_pgtable_ops *ops = &domain->iop.iop.ops; 2204 2205 if (ops->map_pages) 2206 domain_flush_np_cache(domain, iova, size); 2207 } 2208 2209 static int amd_iommu_map_pages(struct iommu_domain *dom, unsigned long iova, 2210 phys_addr_t paddr, size_t pgsize, size_t pgcount, 2211 int iommu_prot, gfp_t gfp, size_t *mapped) 2212 { 2213 struct protection_domain *domain = to_pdomain(dom); 2214 struct io_pgtable_ops *ops = &domain->iop.iop.ops; 2215 int prot = 0; 2216 int ret = -EINVAL; 2217 2218 if ((amd_iommu_pgtable == AMD_IOMMU_V1) && 2219 (domain->iop.mode == PAGE_MODE_NONE)) 2220 return -EINVAL; 2221 2222 if (iommu_prot & IOMMU_READ) 2223 prot |= IOMMU_PROT_IR; 2224 if (iommu_prot & IOMMU_WRITE) 2225 prot |= IOMMU_PROT_IW; 2226 2227 if (ops->map_pages) { 2228 ret = ops->map_pages(ops, iova, paddr, pgsize, 2229 pgcount, prot, gfp, mapped); 2230 } 2231 2232 return ret; 2233 } 2234 2235 static void amd_iommu_iotlb_gather_add_page(struct iommu_domain *domain, 2236 struct iommu_iotlb_gather *gather, 2237 unsigned long iova, size_t size) 2238 { 2239 /* 2240 * AMD's IOMMU can flush as many pages as necessary in a single flush. 2241 * Unless we run in a virtual machine, which can be inferred according 2242 * to whether "non-present cache" is on, it is probably best to prefer 2243 * (potentially) too extensive TLB flushing (i.e., more misses) over 2244 * mutliple TLB flushes (i.e., more flushes). For virtual machines the 2245 * hypervisor needs to synchronize the host IOMMU PTEs with those of 2246 * the guest, and the trade-off is different: unnecessary TLB flushes 2247 * should be avoided. 2248 */ 2249 if (amd_iommu_np_cache && 2250 iommu_iotlb_gather_is_disjoint(gather, iova, size)) 2251 iommu_iotlb_sync(domain, gather); 2252 2253 iommu_iotlb_gather_add_range(gather, iova, size); 2254 } 2255 2256 static size_t amd_iommu_unmap_pages(struct iommu_domain *dom, unsigned long iova, 2257 size_t pgsize, size_t pgcount, 2258 struct iommu_iotlb_gather *gather) 2259 { 2260 struct protection_domain *domain = to_pdomain(dom); 2261 struct io_pgtable_ops *ops = &domain->iop.iop.ops; 2262 size_t r; 2263 2264 if ((amd_iommu_pgtable == AMD_IOMMU_V1) && 2265 (domain->iop.mode == PAGE_MODE_NONE)) 2266 return 0; 2267 2268 r = (ops->unmap_pages) ? ops->unmap_pages(ops, iova, pgsize, pgcount, NULL) : 0; 2269 2270 if (r) 2271 amd_iommu_iotlb_gather_add_page(dom, gather, iova, r); 2272 2273 return r; 2274 } 2275 2276 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, 2277 dma_addr_t iova) 2278 { 2279 struct protection_domain *domain = to_pdomain(dom); 2280 struct io_pgtable_ops *ops = &domain->iop.iop.ops; 2281 2282 return ops->iova_to_phys(ops, iova); 2283 } 2284 2285 static bool amd_iommu_capable(struct device *dev, enum iommu_cap cap) 2286 { 2287 switch (cap) { 2288 case IOMMU_CAP_CACHE_COHERENCY: 2289 return true; 2290 case IOMMU_CAP_NOEXEC: 2291 return false; 2292 case IOMMU_CAP_PRE_BOOT_PROTECTION: 2293 return amdr_ivrs_remap_support; 2294 case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: 2295 return true; 2296 default: 2297 break; 2298 } 2299 2300 return false; 2301 } 2302 2303 static void amd_iommu_get_resv_regions(struct device *dev, 2304 struct list_head *head) 2305 { 2306 struct iommu_resv_region *region; 2307 struct unity_map_entry *entry; 2308 struct amd_iommu *iommu; 2309 struct amd_iommu_pci_seg *pci_seg; 2310 int devid, sbdf; 2311 2312 sbdf = get_device_sbdf_id(dev); 2313 if (sbdf < 0) 2314 return; 2315 2316 devid = PCI_SBDF_TO_DEVID(sbdf); 2317 iommu = rlookup_amd_iommu(dev); 2318 if (!iommu) 2319 return; 2320 pci_seg = iommu->pci_seg; 2321 2322 list_for_each_entry(entry, &pci_seg->unity_map, list) { 2323 int type, prot = 0; 2324 size_t length; 2325 2326 if (devid < entry->devid_start || devid > entry->devid_end) 2327 continue; 2328 2329 type = IOMMU_RESV_DIRECT; 2330 length = entry->address_end - entry->address_start; 2331 if (entry->prot & IOMMU_PROT_IR) 2332 prot |= IOMMU_READ; 2333 if (entry->prot & IOMMU_PROT_IW) 2334 prot |= IOMMU_WRITE; 2335 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE) 2336 /* Exclusion range */ 2337 type = IOMMU_RESV_RESERVED; 2338 2339 region = iommu_alloc_resv_region(entry->address_start, 2340 length, prot, type, 2341 GFP_KERNEL); 2342 if (!region) { 2343 dev_err(dev, "Out of memory allocating dm-regions\n"); 2344 return; 2345 } 2346 list_add_tail(®ion->list, head); 2347 } 2348 2349 region = iommu_alloc_resv_region(MSI_RANGE_START, 2350 MSI_RANGE_END - MSI_RANGE_START + 1, 2351 0, IOMMU_RESV_MSI, GFP_KERNEL); 2352 if (!region) 2353 return; 2354 list_add_tail(®ion->list, head); 2355 2356 region = iommu_alloc_resv_region(HT_RANGE_START, 2357 HT_RANGE_END - HT_RANGE_START + 1, 2358 0, IOMMU_RESV_RESERVED, GFP_KERNEL); 2359 if (!region) 2360 return; 2361 list_add_tail(®ion->list, head); 2362 } 2363 2364 bool amd_iommu_is_attach_deferred(struct device *dev) 2365 { 2366 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); 2367 2368 return dev_data->defer_attach; 2369 } 2370 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred); 2371 2372 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain) 2373 { 2374 struct protection_domain *dom = to_pdomain(domain); 2375 unsigned long flags; 2376 2377 spin_lock_irqsave(&dom->lock, flags); 2378 amd_iommu_domain_flush_tlb_pde(dom); 2379 amd_iommu_domain_flush_complete(dom); 2380 spin_unlock_irqrestore(&dom->lock, flags); 2381 } 2382 2383 static void amd_iommu_iotlb_sync(struct iommu_domain *domain, 2384 struct iommu_iotlb_gather *gather) 2385 { 2386 struct protection_domain *dom = to_pdomain(domain); 2387 unsigned long flags; 2388 2389 spin_lock_irqsave(&dom->lock, flags); 2390 domain_flush_pages(dom, gather->start, gather->end - gather->start, 1); 2391 amd_iommu_domain_flush_complete(dom); 2392 spin_unlock_irqrestore(&dom->lock, flags); 2393 } 2394 2395 static int amd_iommu_def_domain_type(struct device *dev) 2396 { 2397 struct iommu_dev_data *dev_data; 2398 2399 dev_data = dev_iommu_priv_get(dev); 2400 if (!dev_data) 2401 return 0; 2402 2403 /* 2404 * Do not identity map IOMMUv2 capable devices when: 2405 * - memory encryption is active, because some of those devices 2406 * (AMD GPUs) don't have the encryption bit in their DMA-mask 2407 * and require remapping. 2408 * - SNP is enabled, because it prohibits DTE[Mode]=0. 2409 */ 2410 if (dev_data->iommu_v2 && 2411 !cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2412 !amd_iommu_snp_en) { 2413 return IOMMU_DOMAIN_IDENTITY; 2414 } 2415 2416 return 0; 2417 } 2418 2419 static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain) 2420 { 2421 /* IOMMU_PTE_FC is always set */ 2422 return true; 2423 } 2424 2425 const struct iommu_ops amd_iommu_ops = { 2426 .capable = amd_iommu_capable, 2427 .domain_alloc = amd_iommu_domain_alloc, 2428 .probe_device = amd_iommu_probe_device, 2429 .release_device = amd_iommu_release_device, 2430 .probe_finalize = amd_iommu_probe_finalize, 2431 .device_group = amd_iommu_device_group, 2432 .get_resv_regions = amd_iommu_get_resv_regions, 2433 .is_attach_deferred = amd_iommu_is_attach_deferred, 2434 .pgsize_bitmap = AMD_IOMMU_PGSIZES, 2435 .def_domain_type = amd_iommu_def_domain_type, 2436 .default_domain_ops = &(const struct iommu_domain_ops) { 2437 .attach_dev = amd_iommu_attach_device, 2438 .map_pages = amd_iommu_map_pages, 2439 .unmap_pages = amd_iommu_unmap_pages, 2440 .iotlb_sync_map = amd_iommu_iotlb_sync_map, 2441 .iova_to_phys = amd_iommu_iova_to_phys, 2442 .flush_iotlb_all = amd_iommu_flush_iotlb_all, 2443 .iotlb_sync = amd_iommu_iotlb_sync, 2444 .free = amd_iommu_domain_free, 2445 .enforce_cache_coherency = amd_iommu_enforce_cache_coherency, 2446 } 2447 }; 2448 2449 /***************************************************************************** 2450 * 2451 * The next functions do a basic initialization of IOMMU for pass through 2452 * mode 2453 * 2454 * In passthrough mode the IOMMU is initialized and enabled but not used for 2455 * DMA-API translation. 2456 * 2457 *****************************************************************************/ 2458 2459 /* IOMMUv2 specific functions */ 2460 int amd_iommu_register_ppr_notifier(struct notifier_block *nb) 2461 { 2462 return atomic_notifier_chain_register(&ppr_notifier, nb); 2463 } 2464 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); 2465 2466 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) 2467 { 2468 return atomic_notifier_chain_unregister(&ppr_notifier, nb); 2469 } 2470 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); 2471 2472 void amd_iommu_domain_direct_map(struct iommu_domain *dom) 2473 { 2474 struct protection_domain *domain = to_pdomain(dom); 2475 unsigned long flags; 2476 2477 spin_lock_irqsave(&domain->lock, flags); 2478 2479 if (domain->iop.pgtbl_cfg.tlb) 2480 free_io_pgtable_ops(&domain->iop.iop.ops); 2481 2482 spin_unlock_irqrestore(&domain->lock, flags); 2483 } 2484 EXPORT_SYMBOL(amd_iommu_domain_direct_map); 2485 2486 /* Note: This function expects iommu_domain->lock to be held prior calling the function. */ 2487 static int domain_enable_v2(struct protection_domain *domain, int pasids) 2488 { 2489 int levels; 2490 2491 /* Number of GCR3 table levels required */ 2492 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) 2493 levels += 1; 2494 2495 if (levels > amd_iommu_max_glx_val) 2496 return -EINVAL; 2497 2498 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); 2499 if (domain->gcr3_tbl == NULL) 2500 return -ENOMEM; 2501 2502 domain->glx = levels; 2503 domain->flags |= PD_IOMMUV2_MASK; 2504 2505 amd_iommu_domain_update(domain); 2506 2507 return 0; 2508 } 2509 2510 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) 2511 { 2512 struct protection_domain *pdom = to_pdomain(dom); 2513 unsigned long flags; 2514 int ret; 2515 2516 spin_lock_irqsave(&pdom->lock, flags); 2517 2518 /* 2519 * Save us all sanity checks whether devices already in the 2520 * domain support IOMMUv2. Just force that the domain has no 2521 * devices attached when it is switched into IOMMUv2 mode. 2522 */ 2523 ret = -EBUSY; 2524 if (pdom->dev_cnt > 0 || pdom->flags & PD_IOMMUV2_MASK) 2525 goto out; 2526 2527 if (!pdom->gcr3_tbl) 2528 ret = domain_enable_v2(pdom, pasids); 2529 2530 out: 2531 spin_unlock_irqrestore(&pdom->lock, flags); 2532 return ret; 2533 } 2534 EXPORT_SYMBOL(amd_iommu_domain_enable_v2); 2535 2536 static int __flush_pasid(struct protection_domain *domain, u32 pasid, 2537 u64 address, bool size) 2538 { 2539 struct iommu_dev_data *dev_data; 2540 struct iommu_cmd cmd; 2541 int i, ret; 2542 2543 if (!(domain->flags & PD_IOMMUV2_MASK)) 2544 return -EINVAL; 2545 2546 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); 2547 2548 /* 2549 * IOMMU TLB needs to be flushed before Device TLB to 2550 * prevent device TLB refill from IOMMU TLB 2551 */ 2552 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { 2553 if (domain->dev_iommu[i] == 0) 2554 continue; 2555 2556 ret = iommu_queue_command(amd_iommus[i], &cmd); 2557 if (ret != 0) 2558 goto out; 2559 } 2560 2561 /* Wait until IOMMU TLB flushes are complete */ 2562 amd_iommu_domain_flush_complete(domain); 2563 2564 /* Now flush device TLBs */ 2565 list_for_each_entry(dev_data, &domain->dev_list, list) { 2566 struct amd_iommu *iommu; 2567 int qdep; 2568 2569 /* 2570 There might be non-IOMMUv2 capable devices in an IOMMUv2 2571 * domain. 2572 */ 2573 if (!dev_data->ats.enabled) 2574 continue; 2575 2576 qdep = dev_data->ats.qdep; 2577 iommu = rlookup_amd_iommu(dev_data->dev); 2578 if (!iommu) 2579 continue; 2580 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, 2581 qdep, address, size); 2582 2583 ret = iommu_queue_command(iommu, &cmd); 2584 if (ret != 0) 2585 goto out; 2586 } 2587 2588 /* Wait until all device TLBs are flushed */ 2589 amd_iommu_domain_flush_complete(domain); 2590 2591 ret = 0; 2592 2593 out: 2594 2595 return ret; 2596 } 2597 2598 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid, 2599 u64 address) 2600 { 2601 return __flush_pasid(domain, pasid, address, false); 2602 } 2603 2604 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, 2605 u64 address) 2606 { 2607 struct protection_domain *domain = to_pdomain(dom); 2608 unsigned long flags; 2609 int ret; 2610 2611 spin_lock_irqsave(&domain->lock, flags); 2612 ret = __amd_iommu_flush_page(domain, pasid, address); 2613 spin_unlock_irqrestore(&domain->lock, flags); 2614 2615 return ret; 2616 } 2617 EXPORT_SYMBOL(amd_iommu_flush_page); 2618 2619 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid) 2620 { 2621 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 2622 true); 2623 } 2624 2625 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid) 2626 { 2627 struct protection_domain *domain = to_pdomain(dom); 2628 unsigned long flags; 2629 int ret; 2630 2631 spin_lock_irqsave(&domain->lock, flags); 2632 ret = __amd_iommu_flush_tlb(domain, pasid); 2633 spin_unlock_irqrestore(&domain->lock, flags); 2634 2635 return ret; 2636 } 2637 EXPORT_SYMBOL(amd_iommu_flush_tlb); 2638 2639 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc) 2640 { 2641 int index; 2642 u64 *pte; 2643 2644 while (true) { 2645 2646 index = (pasid >> (9 * level)) & 0x1ff; 2647 pte = &root[index]; 2648 2649 if (level == 0) 2650 break; 2651 2652 if (!(*pte & GCR3_VALID)) { 2653 if (!alloc) 2654 return NULL; 2655 2656 root = (void *)get_zeroed_page(GFP_ATOMIC); 2657 if (root == NULL) 2658 return NULL; 2659 2660 *pte = iommu_virt_to_phys(root) | GCR3_VALID; 2661 } 2662 2663 root = iommu_phys_to_virt(*pte & PAGE_MASK); 2664 2665 level -= 1; 2666 } 2667 2668 return pte; 2669 } 2670 2671 static int __set_gcr3(struct protection_domain *domain, u32 pasid, 2672 unsigned long cr3) 2673 { 2674 u64 *pte; 2675 2676 if (domain->iop.mode != PAGE_MODE_NONE) 2677 return -EINVAL; 2678 2679 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); 2680 if (pte == NULL) 2681 return -ENOMEM; 2682 2683 *pte = (cr3 & PAGE_MASK) | GCR3_VALID; 2684 2685 return __amd_iommu_flush_tlb(domain, pasid); 2686 } 2687 2688 static int __clear_gcr3(struct protection_domain *domain, u32 pasid) 2689 { 2690 u64 *pte; 2691 2692 if (domain->iop.mode != PAGE_MODE_NONE) 2693 return -EINVAL; 2694 2695 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); 2696 if (pte == NULL) 2697 return 0; 2698 2699 *pte = 0; 2700 2701 return __amd_iommu_flush_tlb(domain, pasid); 2702 } 2703 2704 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, 2705 unsigned long cr3) 2706 { 2707 struct protection_domain *domain = to_pdomain(dom); 2708 unsigned long flags; 2709 int ret; 2710 2711 spin_lock_irqsave(&domain->lock, flags); 2712 ret = __set_gcr3(domain, pasid, cr3); 2713 spin_unlock_irqrestore(&domain->lock, flags); 2714 2715 return ret; 2716 } 2717 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); 2718 2719 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid) 2720 { 2721 struct protection_domain *domain = to_pdomain(dom); 2722 unsigned long flags; 2723 int ret; 2724 2725 spin_lock_irqsave(&domain->lock, flags); 2726 ret = __clear_gcr3(domain, pasid); 2727 spin_unlock_irqrestore(&domain->lock, flags); 2728 2729 return ret; 2730 } 2731 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); 2732 2733 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid, 2734 int status, int tag) 2735 { 2736 struct iommu_dev_data *dev_data; 2737 struct amd_iommu *iommu; 2738 struct iommu_cmd cmd; 2739 2740 dev_data = dev_iommu_priv_get(&pdev->dev); 2741 iommu = rlookup_amd_iommu(&pdev->dev); 2742 if (!iommu) 2743 return -ENODEV; 2744 2745 build_complete_ppr(&cmd, dev_data->devid, pasid, status, 2746 tag, dev_data->pri_tlp); 2747 2748 return iommu_queue_command(iommu, &cmd); 2749 } 2750 EXPORT_SYMBOL(amd_iommu_complete_ppr); 2751 2752 int amd_iommu_device_info(struct pci_dev *pdev, 2753 struct amd_iommu_device_info *info) 2754 { 2755 int max_pasids; 2756 int pos; 2757 2758 if (pdev == NULL || info == NULL) 2759 return -EINVAL; 2760 2761 if (!amd_iommu_v2_supported()) 2762 return -EINVAL; 2763 2764 memset(info, 0, sizeof(*info)); 2765 2766 if (pci_ats_supported(pdev)) 2767 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; 2768 2769 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); 2770 if (pos) 2771 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; 2772 2773 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); 2774 if (pos) { 2775 int features; 2776 2777 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); 2778 max_pasids = min(max_pasids, (1 << 20)); 2779 2780 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; 2781 info->max_pasids = min(pci_max_pasids(pdev), max_pasids); 2782 2783 features = pci_pasid_features(pdev); 2784 if (features & PCI_PASID_CAP_EXEC) 2785 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; 2786 if (features & PCI_PASID_CAP_PRIV) 2787 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; 2788 } 2789 2790 return 0; 2791 } 2792 EXPORT_SYMBOL(amd_iommu_device_info); 2793 2794 #ifdef CONFIG_IRQ_REMAP 2795 2796 /***************************************************************************** 2797 * 2798 * Interrupt Remapping Implementation 2799 * 2800 *****************************************************************************/ 2801 2802 static struct irq_chip amd_ir_chip; 2803 static DEFINE_SPINLOCK(iommu_table_lock); 2804 2805 static void set_dte_irq_entry(struct amd_iommu *iommu, u16 devid, 2806 struct irq_remap_table *table) 2807 { 2808 u64 dte; 2809 struct dev_table_entry *dev_table = get_dev_table(iommu); 2810 2811 dte = dev_table[devid].data[2]; 2812 dte &= ~DTE_IRQ_PHYS_ADDR_MASK; 2813 dte |= iommu_virt_to_phys(table->table); 2814 dte |= DTE_IRQ_REMAP_INTCTL; 2815 dte |= DTE_INTTABLEN; 2816 dte |= DTE_IRQ_REMAP_ENABLE; 2817 2818 dev_table[devid].data[2] = dte; 2819 } 2820 2821 static struct irq_remap_table *get_irq_table(struct amd_iommu *iommu, u16 devid) 2822 { 2823 struct irq_remap_table *table; 2824 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 2825 2826 if (WARN_ONCE(!pci_seg->rlookup_table[devid], 2827 "%s: no iommu for devid %x:%x\n", 2828 __func__, pci_seg->id, devid)) 2829 return NULL; 2830 2831 table = pci_seg->irq_lookup_table[devid]; 2832 if (WARN_ONCE(!table, "%s: no table for devid %x:%x\n", 2833 __func__, pci_seg->id, devid)) 2834 return NULL; 2835 2836 return table; 2837 } 2838 2839 static struct irq_remap_table *__alloc_irq_table(void) 2840 { 2841 struct irq_remap_table *table; 2842 2843 table = kzalloc(sizeof(*table), GFP_KERNEL); 2844 if (!table) 2845 return NULL; 2846 2847 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL); 2848 if (!table->table) { 2849 kfree(table); 2850 return NULL; 2851 } 2852 raw_spin_lock_init(&table->lock); 2853 2854 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 2855 memset(table->table, 0, 2856 MAX_IRQS_PER_TABLE * sizeof(u32)); 2857 else 2858 memset(table->table, 0, 2859 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); 2860 return table; 2861 } 2862 2863 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid, 2864 struct irq_remap_table *table) 2865 { 2866 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 2867 2868 pci_seg->irq_lookup_table[devid] = table; 2869 set_dte_irq_entry(iommu, devid, table); 2870 iommu_flush_dte(iommu, devid); 2871 } 2872 2873 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias, 2874 void *data) 2875 { 2876 struct irq_remap_table *table = data; 2877 struct amd_iommu_pci_seg *pci_seg; 2878 struct amd_iommu *iommu = rlookup_amd_iommu(&pdev->dev); 2879 2880 if (!iommu) 2881 return -EINVAL; 2882 2883 pci_seg = iommu->pci_seg; 2884 pci_seg->irq_lookup_table[alias] = table; 2885 set_dte_irq_entry(iommu, alias, table); 2886 iommu_flush_dte(pci_seg->rlookup_table[alias], alias); 2887 2888 return 0; 2889 } 2890 2891 static struct irq_remap_table *alloc_irq_table(struct amd_iommu *iommu, 2892 u16 devid, struct pci_dev *pdev) 2893 { 2894 struct irq_remap_table *table = NULL; 2895 struct irq_remap_table *new_table = NULL; 2896 struct amd_iommu_pci_seg *pci_seg; 2897 unsigned long flags; 2898 u16 alias; 2899 2900 spin_lock_irqsave(&iommu_table_lock, flags); 2901 2902 pci_seg = iommu->pci_seg; 2903 table = pci_seg->irq_lookup_table[devid]; 2904 if (table) 2905 goto out_unlock; 2906 2907 alias = pci_seg->alias_table[devid]; 2908 table = pci_seg->irq_lookup_table[alias]; 2909 if (table) { 2910 set_remap_table_entry(iommu, devid, table); 2911 goto out_wait; 2912 } 2913 spin_unlock_irqrestore(&iommu_table_lock, flags); 2914 2915 /* Nothing there yet, allocate new irq remapping table */ 2916 new_table = __alloc_irq_table(); 2917 if (!new_table) 2918 return NULL; 2919 2920 spin_lock_irqsave(&iommu_table_lock, flags); 2921 2922 table = pci_seg->irq_lookup_table[devid]; 2923 if (table) 2924 goto out_unlock; 2925 2926 table = pci_seg->irq_lookup_table[alias]; 2927 if (table) { 2928 set_remap_table_entry(iommu, devid, table); 2929 goto out_wait; 2930 } 2931 2932 table = new_table; 2933 new_table = NULL; 2934 2935 if (pdev) 2936 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias, 2937 table); 2938 else 2939 set_remap_table_entry(iommu, devid, table); 2940 2941 if (devid != alias) 2942 set_remap_table_entry(iommu, alias, table); 2943 2944 out_wait: 2945 iommu_completion_wait(iommu); 2946 2947 out_unlock: 2948 spin_unlock_irqrestore(&iommu_table_lock, flags); 2949 2950 if (new_table) { 2951 kmem_cache_free(amd_iommu_irq_cache, new_table->table); 2952 kfree(new_table); 2953 } 2954 return table; 2955 } 2956 2957 static int alloc_irq_index(struct amd_iommu *iommu, u16 devid, int count, 2958 bool align, struct pci_dev *pdev) 2959 { 2960 struct irq_remap_table *table; 2961 int index, c, alignment = 1; 2962 unsigned long flags; 2963 2964 table = alloc_irq_table(iommu, devid, pdev); 2965 if (!table) 2966 return -ENODEV; 2967 2968 if (align) 2969 alignment = roundup_pow_of_two(count); 2970 2971 raw_spin_lock_irqsave(&table->lock, flags); 2972 2973 /* Scan table for free entries */ 2974 for (index = ALIGN(table->min_index, alignment), c = 0; 2975 index < MAX_IRQS_PER_TABLE;) { 2976 if (!iommu->irte_ops->is_allocated(table, index)) { 2977 c += 1; 2978 } else { 2979 c = 0; 2980 index = ALIGN(index + 1, alignment); 2981 continue; 2982 } 2983 2984 if (c == count) { 2985 for (; c != 0; --c) 2986 iommu->irte_ops->set_allocated(table, index - c + 1); 2987 2988 index -= count - 1; 2989 goto out; 2990 } 2991 2992 index++; 2993 } 2994 2995 index = -ENOSPC; 2996 2997 out: 2998 raw_spin_unlock_irqrestore(&table->lock, flags); 2999 3000 return index; 3001 } 3002 3003 static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, 3004 struct irte_ga *irte, struct amd_ir_data *data) 3005 { 3006 bool ret; 3007 struct irq_remap_table *table; 3008 unsigned long flags; 3009 struct irte_ga *entry; 3010 3011 table = get_irq_table(iommu, devid); 3012 if (!table) 3013 return -ENOMEM; 3014 3015 raw_spin_lock_irqsave(&table->lock, flags); 3016 3017 entry = (struct irte_ga *)table->table; 3018 entry = &entry[index]; 3019 3020 ret = cmpxchg_double(&entry->lo.val, &entry->hi.val, 3021 entry->lo.val, entry->hi.val, 3022 irte->lo.val, irte->hi.val); 3023 /* 3024 * We use cmpxchg16 to atomically update the 128-bit IRTE, 3025 * and it cannot be updated by the hardware or other processors 3026 * behind us, so the return value of cmpxchg16 should be the 3027 * same as the old value. 3028 */ 3029 WARN_ON(!ret); 3030 3031 if (data) 3032 data->ref = entry; 3033 3034 raw_spin_unlock_irqrestore(&table->lock, flags); 3035 3036 iommu_flush_irt(iommu, devid); 3037 iommu_completion_wait(iommu); 3038 3039 return 0; 3040 } 3041 3042 static int modify_irte(struct amd_iommu *iommu, 3043 u16 devid, int index, union irte *irte) 3044 { 3045 struct irq_remap_table *table; 3046 unsigned long flags; 3047 3048 table = get_irq_table(iommu, devid); 3049 if (!table) 3050 return -ENOMEM; 3051 3052 raw_spin_lock_irqsave(&table->lock, flags); 3053 table->table[index] = irte->val; 3054 raw_spin_unlock_irqrestore(&table->lock, flags); 3055 3056 iommu_flush_irt(iommu, devid); 3057 iommu_completion_wait(iommu); 3058 3059 return 0; 3060 } 3061 3062 static void free_irte(struct amd_iommu *iommu, u16 devid, int index) 3063 { 3064 struct irq_remap_table *table; 3065 unsigned long flags; 3066 3067 table = get_irq_table(iommu, devid); 3068 if (!table) 3069 return; 3070 3071 raw_spin_lock_irqsave(&table->lock, flags); 3072 iommu->irte_ops->clear_allocated(table, index); 3073 raw_spin_unlock_irqrestore(&table->lock, flags); 3074 3075 iommu_flush_irt(iommu, devid); 3076 iommu_completion_wait(iommu); 3077 } 3078 3079 static void irte_prepare(void *entry, 3080 u32 delivery_mode, bool dest_mode, 3081 u8 vector, u32 dest_apicid, int devid) 3082 { 3083 union irte *irte = (union irte *) entry; 3084 3085 irte->val = 0; 3086 irte->fields.vector = vector; 3087 irte->fields.int_type = delivery_mode; 3088 irte->fields.destination = dest_apicid; 3089 irte->fields.dm = dest_mode; 3090 irte->fields.valid = 1; 3091 } 3092 3093 static void irte_ga_prepare(void *entry, 3094 u32 delivery_mode, bool dest_mode, 3095 u8 vector, u32 dest_apicid, int devid) 3096 { 3097 struct irte_ga *irte = (struct irte_ga *) entry; 3098 3099 irte->lo.val = 0; 3100 irte->hi.val = 0; 3101 irte->lo.fields_remap.int_type = delivery_mode; 3102 irte->lo.fields_remap.dm = dest_mode; 3103 irte->hi.fields.vector = vector; 3104 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid); 3105 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); 3106 irte->lo.fields_remap.valid = 1; 3107 } 3108 3109 static void irte_activate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) 3110 { 3111 union irte *irte = (union irte *) entry; 3112 3113 irte->fields.valid = 1; 3114 modify_irte(iommu, devid, index, irte); 3115 } 3116 3117 static void irte_ga_activate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) 3118 { 3119 struct irte_ga *irte = (struct irte_ga *) entry; 3120 3121 irte->lo.fields_remap.valid = 1; 3122 modify_irte_ga(iommu, devid, index, irte, NULL); 3123 } 3124 3125 static void irte_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) 3126 { 3127 union irte *irte = (union irte *) entry; 3128 3129 irte->fields.valid = 0; 3130 modify_irte(iommu, devid, index, irte); 3131 } 3132 3133 static void irte_ga_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) 3134 { 3135 struct irte_ga *irte = (struct irte_ga *) entry; 3136 3137 irte->lo.fields_remap.valid = 0; 3138 modify_irte_ga(iommu, devid, index, irte, NULL); 3139 } 3140 3141 static void irte_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index, 3142 u8 vector, u32 dest_apicid) 3143 { 3144 union irte *irte = (union irte *) entry; 3145 3146 irte->fields.vector = vector; 3147 irte->fields.destination = dest_apicid; 3148 modify_irte(iommu, devid, index, irte); 3149 } 3150 3151 static void irte_ga_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index, 3152 u8 vector, u32 dest_apicid) 3153 { 3154 struct irte_ga *irte = (struct irte_ga *) entry; 3155 3156 if (!irte->lo.fields_remap.guest_mode) { 3157 irte->hi.fields.vector = vector; 3158 irte->lo.fields_remap.destination = 3159 APICID_TO_IRTE_DEST_LO(dest_apicid); 3160 irte->hi.fields.destination = 3161 APICID_TO_IRTE_DEST_HI(dest_apicid); 3162 modify_irte_ga(iommu, devid, index, irte, NULL); 3163 } 3164 } 3165 3166 #define IRTE_ALLOCATED (~1U) 3167 static void irte_set_allocated(struct irq_remap_table *table, int index) 3168 { 3169 table->table[index] = IRTE_ALLOCATED; 3170 } 3171 3172 static void irte_ga_set_allocated(struct irq_remap_table *table, int index) 3173 { 3174 struct irte_ga *ptr = (struct irte_ga *)table->table; 3175 struct irte_ga *irte = &ptr[index]; 3176 3177 memset(&irte->lo.val, 0, sizeof(u64)); 3178 memset(&irte->hi.val, 0, sizeof(u64)); 3179 irte->hi.fields.vector = 0xff; 3180 } 3181 3182 static bool irte_is_allocated(struct irq_remap_table *table, int index) 3183 { 3184 union irte *ptr = (union irte *)table->table; 3185 union irte *irte = &ptr[index]; 3186 3187 return irte->val != 0; 3188 } 3189 3190 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) 3191 { 3192 struct irte_ga *ptr = (struct irte_ga *)table->table; 3193 struct irte_ga *irte = &ptr[index]; 3194 3195 return irte->hi.fields.vector != 0; 3196 } 3197 3198 static void irte_clear_allocated(struct irq_remap_table *table, int index) 3199 { 3200 table->table[index] = 0; 3201 } 3202 3203 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) 3204 { 3205 struct irte_ga *ptr = (struct irte_ga *)table->table; 3206 struct irte_ga *irte = &ptr[index]; 3207 3208 memset(&irte->lo.val, 0, sizeof(u64)); 3209 memset(&irte->hi.val, 0, sizeof(u64)); 3210 } 3211 3212 static int get_devid(struct irq_alloc_info *info) 3213 { 3214 switch (info->type) { 3215 case X86_IRQ_ALLOC_TYPE_IOAPIC: 3216 return get_ioapic_devid(info->devid); 3217 case X86_IRQ_ALLOC_TYPE_HPET: 3218 return get_hpet_devid(info->devid); 3219 case X86_IRQ_ALLOC_TYPE_PCI_MSI: 3220 case X86_IRQ_ALLOC_TYPE_PCI_MSIX: 3221 return get_device_sbdf_id(msi_desc_to_dev(info->desc)); 3222 default: 3223 WARN_ON_ONCE(1); 3224 return -1; 3225 } 3226 } 3227 3228 struct irq_remap_ops amd_iommu_irq_ops = { 3229 .prepare = amd_iommu_prepare, 3230 .enable = amd_iommu_enable, 3231 .disable = amd_iommu_disable, 3232 .reenable = amd_iommu_reenable, 3233 .enable_faulting = amd_iommu_enable_faulting, 3234 }; 3235 3236 static void fill_msi_msg(struct msi_msg *msg, u32 index) 3237 { 3238 msg->data = index; 3239 msg->address_lo = 0; 3240 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; 3241 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; 3242 } 3243 3244 static void irq_remapping_prepare_irte(struct amd_ir_data *data, 3245 struct irq_cfg *irq_cfg, 3246 struct irq_alloc_info *info, 3247 int devid, int index, int sub_handle) 3248 { 3249 struct irq_2_irte *irte_info = &data->irq_2_irte; 3250 struct amd_iommu *iommu = data->iommu; 3251 3252 if (!iommu) 3253 return; 3254 3255 data->irq_2_irte.devid = devid; 3256 data->irq_2_irte.index = index + sub_handle; 3257 iommu->irte_ops->prepare(data->entry, apic->delivery_mode, 3258 apic->dest_mode_logical, irq_cfg->vector, 3259 irq_cfg->dest_apicid, devid); 3260 3261 switch (info->type) { 3262 case X86_IRQ_ALLOC_TYPE_IOAPIC: 3263 case X86_IRQ_ALLOC_TYPE_HPET: 3264 case X86_IRQ_ALLOC_TYPE_PCI_MSI: 3265 case X86_IRQ_ALLOC_TYPE_PCI_MSIX: 3266 fill_msi_msg(&data->msi_entry, irte_info->index); 3267 break; 3268 3269 default: 3270 BUG_ON(1); 3271 break; 3272 } 3273 } 3274 3275 struct amd_irte_ops irte_32_ops = { 3276 .prepare = irte_prepare, 3277 .activate = irte_activate, 3278 .deactivate = irte_deactivate, 3279 .set_affinity = irte_set_affinity, 3280 .set_allocated = irte_set_allocated, 3281 .is_allocated = irte_is_allocated, 3282 .clear_allocated = irte_clear_allocated, 3283 }; 3284 3285 struct amd_irte_ops irte_128_ops = { 3286 .prepare = irte_ga_prepare, 3287 .activate = irte_ga_activate, 3288 .deactivate = irte_ga_deactivate, 3289 .set_affinity = irte_ga_set_affinity, 3290 .set_allocated = irte_ga_set_allocated, 3291 .is_allocated = irte_ga_is_allocated, 3292 .clear_allocated = irte_ga_clear_allocated, 3293 }; 3294 3295 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, 3296 unsigned int nr_irqs, void *arg) 3297 { 3298 struct irq_alloc_info *info = arg; 3299 struct irq_data *irq_data; 3300 struct amd_ir_data *data = NULL; 3301 struct amd_iommu *iommu; 3302 struct irq_cfg *cfg; 3303 int i, ret, devid, seg, sbdf; 3304 int index; 3305 3306 if (!info) 3307 return -EINVAL; 3308 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI) 3309 return -EINVAL; 3310 3311 sbdf = get_devid(info); 3312 if (sbdf < 0) 3313 return -EINVAL; 3314 3315 seg = PCI_SBDF_TO_SEGID(sbdf); 3316 devid = PCI_SBDF_TO_DEVID(sbdf); 3317 iommu = __rlookup_amd_iommu(seg, devid); 3318 if (!iommu) 3319 return -EINVAL; 3320 3321 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 3322 if (ret < 0) 3323 return ret; 3324 3325 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { 3326 struct irq_remap_table *table; 3327 3328 table = alloc_irq_table(iommu, devid, NULL); 3329 if (table) { 3330 if (!table->min_index) { 3331 /* 3332 * Keep the first 32 indexes free for IOAPIC 3333 * interrupts. 3334 */ 3335 table->min_index = 32; 3336 for (i = 0; i < 32; ++i) 3337 iommu->irte_ops->set_allocated(table, i); 3338 } 3339 WARN_ON(table->min_index != 32); 3340 index = info->ioapic.pin; 3341 } else { 3342 index = -ENOMEM; 3343 } 3344 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI || 3345 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) { 3346 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI); 3347 3348 index = alloc_irq_index(iommu, devid, nr_irqs, align, 3349 msi_desc_to_pci_dev(info->desc)); 3350 } else { 3351 index = alloc_irq_index(iommu, devid, nr_irqs, false, NULL); 3352 } 3353 3354 if (index < 0) { 3355 pr_warn("Failed to allocate IRTE\n"); 3356 ret = index; 3357 goto out_free_parent; 3358 } 3359 3360 for (i = 0; i < nr_irqs; i++) { 3361 irq_data = irq_domain_get_irq_data(domain, virq + i); 3362 cfg = irq_data ? irqd_cfg(irq_data) : NULL; 3363 if (!cfg) { 3364 ret = -EINVAL; 3365 goto out_free_data; 3366 } 3367 3368 ret = -ENOMEM; 3369 data = kzalloc(sizeof(*data), GFP_KERNEL); 3370 if (!data) 3371 goto out_free_data; 3372 3373 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 3374 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); 3375 else 3376 data->entry = kzalloc(sizeof(struct irte_ga), 3377 GFP_KERNEL); 3378 if (!data->entry) { 3379 kfree(data); 3380 goto out_free_data; 3381 } 3382 3383 data->iommu = iommu; 3384 irq_data->hwirq = (devid << 16) + i; 3385 irq_data->chip_data = data; 3386 irq_data->chip = &amd_ir_chip; 3387 irq_remapping_prepare_irte(data, cfg, info, devid, index, i); 3388 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); 3389 } 3390 3391 return 0; 3392 3393 out_free_data: 3394 for (i--; i >= 0; i--) { 3395 irq_data = irq_domain_get_irq_data(domain, virq + i); 3396 if (irq_data) 3397 kfree(irq_data->chip_data); 3398 } 3399 for (i = 0; i < nr_irqs; i++) 3400 free_irte(iommu, devid, index + i); 3401 out_free_parent: 3402 irq_domain_free_irqs_common(domain, virq, nr_irqs); 3403 return ret; 3404 } 3405 3406 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, 3407 unsigned int nr_irqs) 3408 { 3409 struct irq_2_irte *irte_info; 3410 struct irq_data *irq_data; 3411 struct amd_ir_data *data; 3412 int i; 3413 3414 for (i = 0; i < nr_irqs; i++) { 3415 irq_data = irq_domain_get_irq_data(domain, virq + i); 3416 if (irq_data && irq_data->chip_data) { 3417 data = irq_data->chip_data; 3418 irte_info = &data->irq_2_irte; 3419 free_irte(data->iommu, irte_info->devid, irte_info->index); 3420 kfree(data->entry); 3421 kfree(data); 3422 } 3423 } 3424 irq_domain_free_irqs_common(domain, virq, nr_irqs); 3425 } 3426 3427 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, 3428 struct amd_ir_data *ir_data, 3429 struct irq_2_irte *irte_info, 3430 struct irq_cfg *cfg); 3431 3432 static int irq_remapping_activate(struct irq_domain *domain, 3433 struct irq_data *irq_data, bool reserve) 3434 { 3435 struct amd_ir_data *data = irq_data->chip_data; 3436 struct irq_2_irte *irte_info = &data->irq_2_irte; 3437 struct amd_iommu *iommu = data->iommu; 3438 struct irq_cfg *cfg = irqd_cfg(irq_data); 3439 3440 if (!iommu) 3441 return 0; 3442 3443 iommu->irte_ops->activate(iommu, data->entry, irte_info->devid, 3444 irte_info->index); 3445 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg); 3446 return 0; 3447 } 3448 3449 static void irq_remapping_deactivate(struct irq_domain *domain, 3450 struct irq_data *irq_data) 3451 { 3452 struct amd_ir_data *data = irq_data->chip_data; 3453 struct irq_2_irte *irte_info = &data->irq_2_irte; 3454 struct amd_iommu *iommu = data->iommu; 3455 3456 if (iommu) 3457 iommu->irte_ops->deactivate(iommu, data->entry, irte_info->devid, 3458 irte_info->index); 3459 } 3460 3461 static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec, 3462 enum irq_domain_bus_token bus_token) 3463 { 3464 struct amd_iommu *iommu; 3465 int devid = -1; 3466 3467 if (!amd_iommu_irq_remap) 3468 return 0; 3469 3470 if (x86_fwspec_is_ioapic(fwspec)) 3471 devid = get_ioapic_devid(fwspec->param[0]); 3472 else if (x86_fwspec_is_hpet(fwspec)) 3473 devid = get_hpet_devid(fwspec->param[0]); 3474 3475 if (devid < 0) 3476 return 0; 3477 iommu = __rlookup_amd_iommu((devid >> 16), (devid & 0xffff)); 3478 3479 return iommu && iommu->ir_domain == d; 3480 } 3481 3482 static const struct irq_domain_ops amd_ir_domain_ops = { 3483 .select = irq_remapping_select, 3484 .alloc = irq_remapping_alloc, 3485 .free = irq_remapping_free, 3486 .activate = irq_remapping_activate, 3487 .deactivate = irq_remapping_deactivate, 3488 }; 3489 3490 int amd_iommu_activate_guest_mode(void *data) 3491 { 3492 struct amd_ir_data *ir_data = (struct amd_ir_data *)data; 3493 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; 3494 u64 valid; 3495 3496 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || 3497 !entry || entry->lo.fields_vapic.guest_mode) 3498 return 0; 3499 3500 valid = entry->lo.fields_vapic.valid; 3501 3502 entry->lo.val = 0; 3503 entry->hi.val = 0; 3504 3505 entry->lo.fields_vapic.valid = valid; 3506 entry->lo.fields_vapic.guest_mode = 1; 3507 entry->lo.fields_vapic.ga_log_intr = 1; 3508 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr; 3509 entry->hi.fields.vector = ir_data->ga_vector; 3510 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; 3511 3512 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, 3513 ir_data->irq_2_irte.index, entry, ir_data); 3514 } 3515 EXPORT_SYMBOL(amd_iommu_activate_guest_mode); 3516 3517 int amd_iommu_deactivate_guest_mode(void *data) 3518 { 3519 struct amd_ir_data *ir_data = (struct amd_ir_data *)data; 3520 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; 3521 struct irq_cfg *cfg = ir_data->cfg; 3522 u64 valid; 3523 3524 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || 3525 !entry || !entry->lo.fields_vapic.guest_mode) 3526 return 0; 3527 3528 valid = entry->lo.fields_remap.valid; 3529 3530 entry->lo.val = 0; 3531 entry->hi.val = 0; 3532 3533 entry->lo.fields_remap.valid = valid; 3534 entry->lo.fields_remap.dm = apic->dest_mode_logical; 3535 entry->lo.fields_remap.int_type = apic->delivery_mode; 3536 entry->hi.fields.vector = cfg->vector; 3537 entry->lo.fields_remap.destination = 3538 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid); 3539 entry->hi.fields.destination = 3540 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); 3541 3542 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, 3543 ir_data->irq_2_irte.index, entry, ir_data); 3544 } 3545 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode); 3546 3547 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) 3548 { 3549 int ret; 3550 struct amd_iommu_pi_data *pi_data = vcpu_info; 3551 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; 3552 struct amd_ir_data *ir_data = data->chip_data; 3553 struct irq_2_irte *irte_info = &ir_data->irq_2_irte; 3554 struct iommu_dev_data *dev_data; 3555 3556 if (ir_data->iommu == NULL) 3557 return -EINVAL; 3558 3559 dev_data = search_dev_data(ir_data->iommu, irte_info->devid); 3560 3561 /* Note: 3562 * This device has never been set up for guest mode. 3563 * we should not modify the IRTE 3564 */ 3565 if (!dev_data || !dev_data->use_vapic) 3566 return 0; 3567 3568 ir_data->cfg = irqd_cfg(data); 3569 pi_data->ir_data = ir_data; 3570 3571 /* Note: 3572 * SVM tries to set up for VAPIC mode, but we are in 3573 * legacy mode. So, we force legacy mode instead. 3574 */ 3575 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { 3576 pr_debug("%s: Fall back to using intr legacy remap\n", 3577 __func__); 3578 pi_data->is_guest_mode = false; 3579 } 3580 3581 pi_data->prev_ga_tag = ir_data->cached_ga_tag; 3582 if (pi_data->is_guest_mode) { 3583 ir_data->ga_root_ptr = (pi_data->base >> 12); 3584 ir_data->ga_vector = vcpu_pi_info->vector; 3585 ir_data->ga_tag = pi_data->ga_tag; 3586 ret = amd_iommu_activate_guest_mode(ir_data); 3587 if (!ret) 3588 ir_data->cached_ga_tag = pi_data->ga_tag; 3589 } else { 3590 ret = amd_iommu_deactivate_guest_mode(ir_data); 3591 3592 /* 3593 * This communicates the ga_tag back to the caller 3594 * so that it can do all the necessary clean up. 3595 */ 3596 if (!ret) 3597 ir_data->cached_ga_tag = 0; 3598 } 3599 3600 return ret; 3601 } 3602 3603 3604 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, 3605 struct amd_ir_data *ir_data, 3606 struct irq_2_irte *irte_info, 3607 struct irq_cfg *cfg) 3608 { 3609 3610 /* 3611 * Atomically updates the IRTE with the new destination, vector 3612 * and flushes the interrupt entry cache. 3613 */ 3614 iommu->irte_ops->set_affinity(iommu, ir_data->entry, irte_info->devid, 3615 irte_info->index, cfg->vector, 3616 cfg->dest_apicid); 3617 } 3618 3619 static int amd_ir_set_affinity(struct irq_data *data, 3620 const struct cpumask *mask, bool force) 3621 { 3622 struct amd_ir_data *ir_data = data->chip_data; 3623 struct irq_2_irte *irte_info = &ir_data->irq_2_irte; 3624 struct irq_cfg *cfg = irqd_cfg(data); 3625 struct irq_data *parent = data->parent_data; 3626 struct amd_iommu *iommu = ir_data->iommu; 3627 int ret; 3628 3629 if (!iommu) 3630 return -ENODEV; 3631 3632 ret = parent->chip->irq_set_affinity(parent, mask, force); 3633 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 3634 return ret; 3635 3636 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg); 3637 /* 3638 * After this point, all the interrupts will start arriving 3639 * at the new destination. So, time to cleanup the previous 3640 * vector allocation. 3641 */ 3642 send_cleanup_vector(cfg); 3643 3644 return IRQ_SET_MASK_OK_DONE; 3645 } 3646 3647 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) 3648 { 3649 struct amd_ir_data *ir_data = irq_data->chip_data; 3650 3651 *msg = ir_data->msi_entry; 3652 } 3653 3654 static struct irq_chip amd_ir_chip = { 3655 .name = "AMD-IR", 3656 .irq_ack = apic_ack_irq, 3657 .irq_set_affinity = amd_ir_set_affinity, 3658 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, 3659 .irq_compose_msi_msg = ir_compose_msi_msg, 3660 }; 3661 3662 static const struct msi_parent_ops amdvi_msi_parent_ops = { 3663 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | 3664 MSI_FLAG_MULTI_PCI_MSI | 3665 MSI_FLAG_PCI_IMS, 3666 .prefix = "IR-", 3667 .init_dev_msi_info = msi_parent_init_dev_msi_info, 3668 }; 3669 3670 static const struct msi_parent_ops virt_amdvi_msi_parent_ops = { 3671 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | 3672 MSI_FLAG_MULTI_PCI_MSI, 3673 .prefix = "vIR-", 3674 .init_dev_msi_info = msi_parent_init_dev_msi_info, 3675 }; 3676 3677 int amd_iommu_create_irq_domain(struct amd_iommu *iommu) 3678 { 3679 struct fwnode_handle *fn; 3680 3681 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); 3682 if (!fn) 3683 return -ENOMEM; 3684 iommu->ir_domain = irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 0, 0, 3685 fn, &amd_ir_domain_ops, iommu); 3686 if (!iommu->ir_domain) { 3687 irq_domain_free_fwnode(fn); 3688 return -ENOMEM; 3689 } 3690 3691 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_AMDVI); 3692 iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT | 3693 IRQ_DOMAIN_FLAG_ISOLATED_MSI; 3694 3695 if (amd_iommu_np_cache) 3696 iommu->ir_domain->msi_parent_ops = &virt_amdvi_msi_parent_ops; 3697 else 3698 iommu->ir_domain->msi_parent_ops = &amdvi_msi_parent_ops; 3699 3700 return 0; 3701 } 3702 3703 int amd_iommu_update_ga(int cpu, bool is_run, void *data) 3704 { 3705 unsigned long flags; 3706 struct amd_iommu *iommu; 3707 struct irq_remap_table *table; 3708 struct amd_ir_data *ir_data = (struct amd_ir_data *)data; 3709 int devid = ir_data->irq_2_irte.devid; 3710 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; 3711 struct irte_ga *ref = (struct irte_ga *) ir_data->ref; 3712 3713 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || 3714 !ref || !entry || !entry->lo.fields_vapic.guest_mode) 3715 return 0; 3716 3717 iommu = ir_data->iommu; 3718 if (!iommu) 3719 return -ENODEV; 3720 3721 table = get_irq_table(iommu, devid); 3722 if (!table) 3723 return -ENODEV; 3724 3725 raw_spin_lock_irqsave(&table->lock, flags); 3726 3727 if (ref->lo.fields_vapic.guest_mode) { 3728 if (cpu >= 0) { 3729 ref->lo.fields_vapic.destination = 3730 APICID_TO_IRTE_DEST_LO(cpu); 3731 ref->hi.fields.destination = 3732 APICID_TO_IRTE_DEST_HI(cpu); 3733 } 3734 ref->lo.fields_vapic.is_run = is_run; 3735 barrier(); 3736 } 3737 3738 raw_spin_unlock_irqrestore(&table->lock, flags); 3739 3740 iommu_flush_irt(iommu, devid); 3741 iommu_completion_wait(iommu); 3742 return 0; 3743 } 3744 EXPORT_SYMBOL(amd_iommu_update_ga); 3745 #endif 3746