1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/slab.h> 16 #include <linux/syscore_ops.h> 17 #include <linux/interrupt.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/amd-iommu.h> 21 #include <linux/export.h> 22 #include <linux/kmemleak.h> 23 #include <linux/mem_encrypt.h> 24 #include <asm/pci-direct.h> 25 #include <asm/iommu.h> 26 #include <asm/apic.h> 27 #include <asm/gart.h> 28 #include <asm/x86_init.h> 29 #include <asm/iommu_table.h> 30 #include <asm/io_apic.h> 31 #include <asm/irq_remapping.h> 32 #include <asm/set_memory.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 39 /* 40 * definitions for the ACPI scanning code 41 */ 42 #define IVRS_HEADER_LENGTH 48 43 44 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 45 #define ACPI_IVMD_TYPE_ALL 0x20 46 #define ACPI_IVMD_TYPE 0x21 47 #define ACPI_IVMD_TYPE_RANGE 0x22 48 49 #define IVHD_DEV_ALL 0x01 50 #define IVHD_DEV_SELECT 0x02 51 #define IVHD_DEV_SELECT_RANGE_START 0x03 52 #define IVHD_DEV_RANGE_END 0x04 53 #define IVHD_DEV_ALIAS 0x42 54 #define IVHD_DEV_ALIAS_RANGE 0x43 55 #define IVHD_DEV_EXT_SELECT 0x46 56 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 57 #define IVHD_DEV_SPECIAL 0x48 58 #define IVHD_DEV_ACPI_HID 0xf0 59 60 #define UID_NOT_PRESENT 0 61 #define UID_IS_INTEGER 1 62 #define UID_IS_CHARACTER 2 63 64 #define IVHD_SPECIAL_IOAPIC 1 65 #define IVHD_SPECIAL_HPET 2 66 67 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 68 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 69 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 70 #define IVHD_FLAG_ISOC_EN_MASK 0x08 71 72 #define IVMD_FLAG_EXCL_RANGE 0x08 73 #define IVMD_FLAG_IW 0x04 74 #define IVMD_FLAG_IR 0x02 75 #define IVMD_FLAG_UNITY_MAP 0x01 76 77 #define ACPI_DEVFLAG_INITPASS 0x01 78 #define ACPI_DEVFLAG_EXTINT 0x02 79 #define ACPI_DEVFLAG_NMI 0x04 80 #define ACPI_DEVFLAG_SYSMGT1 0x10 81 #define ACPI_DEVFLAG_SYSMGT2 0x20 82 #define ACPI_DEVFLAG_LINT0 0x40 83 #define ACPI_DEVFLAG_LINT1 0x80 84 #define ACPI_DEVFLAG_ATSDIS 0x10000000 85 86 #define LOOP_TIMEOUT 100000 87 /* 88 * ACPI table definitions 89 * 90 * These data structures are laid over the table to parse the important values 91 * out of it. 92 */ 93 94 extern const struct iommu_ops amd_iommu_ops; 95 96 /* 97 * structure describing one IOMMU in the ACPI table. Typically followed by one 98 * or more ivhd_entrys. 99 */ 100 struct ivhd_header { 101 u8 type; 102 u8 flags; 103 u16 length; 104 u16 devid; 105 u16 cap_ptr; 106 u64 mmio_phys; 107 u16 pci_seg; 108 u16 info; 109 u32 efr_attr; 110 111 /* Following only valid on IVHD type 11h and 40h */ 112 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 113 u64 res; 114 } __attribute__((packed)); 115 116 /* 117 * A device entry describing which devices a specific IOMMU translates and 118 * which requestor ids they use. 119 */ 120 struct ivhd_entry { 121 u8 type; 122 u16 devid; 123 u8 flags; 124 u32 ext; 125 u32 hidh; 126 u64 cid; 127 u8 uidf; 128 u8 uidl; 129 u8 uid; 130 } __attribute__((packed)); 131 132 /* 133 * An AMD IOMMU memory definition structure. It defines things like exclusion 134 * ranges for devices and regions that should be unity mapped. 135 */ 136 struct ivmd_header { 137 u8 type; 138 u8 flags; 139 u16 length; 140 u16 devid; 141 u16 aux; 142 u64 resv; 143 u64 range_start; 144 u64 range_length; 145 } __attribute__((packed)); 146 147 bool amd_iommu_dump; 148 bool amd_iommu_irq_remap __read_mostly; 149 150 enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1; 151 152 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 153 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 154 155 static bool amd_iommu_detected; 156 static bool amd_iommu_disabled __initdata; 157 static bool amd_iommu_force_enable __initdata; 158 static int amd_iommu_target_ivhd_type; 159 160 u16 amd_iommu_last_bdf; /* largest PCI device id we have 161 to handle */ 162 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings 163 we find in ACPI */ 164 165 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 166 system */ 167 168 /* Array to assign indices to IOMMUs*/ 169 struct amd_iommu *amd_iommus[MAX_IOMMUS]; 170 171 /* Number of IOMMUs present in the system */ 172 static int amd_iommus_present; 173 174 /* IOMMUs have a non-present cache? */ 175 bool amd_iommu_np_cache __read_mostly; 176 bool amd_iommu_iotlb_sup __read_mostly = true; 177 178 u32 amd_iommu_max_pasid __read_mostly = ~0; 179 180 bool amd_iommu_v2_present __read_mostly; 181 static bool amd_iommu_pc_present __read_mostly; 182 183 bool amd_iommu_force_isolation __read_mostly; 184 185 /* 186 * Pointer to the device table which is shared by all AMD IOMMUs 187 * it is indexed by the PCI device id or the HT unit id and contains 188 * information about the domain the device belongs to as well as the 189 * page table root pointer. 190 */ 191 struct dev_table_entry *amd_iommu_dev_table; 192 /* 193 * Pointer to a device table which the content of old device table 194 * will be copied to. It's only be used in kdump kernel. 195 */ 196 static struct dev_table_entry *old_dev_tbl_cpy; 197 198 /* 199 * The alias table is a driver specific data structure which contains the 200 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 201 * More than one device can share the same requestor id. 202 */ 203 u16 *amd_iommu_alias_table; 204 205 /* 206 * The rlookup table is used to find the IOMMU which is responsible 207 * for a specific device. It is also indexed by the PCI device id. 208 */ 209 struct amd_iommu **amd_iommu_rlookup_table; 210 211 /* 212 * This table is used to find the irq remapping table for a given device id 213 * quickly. 214 */ 215 struct irq_remap_table **irq_lookup_table; 216 217 /* 218 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap 219 * to know which ones are already in use. 220 */ 221 unsigned long *amd_iommu_pd_alloc_bitmap; 222 223 static u32 dev_table_size; /* size of the device table */ 224 static u32 alias_table_size; /* size of the alias table */ 225 static u32 rlookup_table_size; /* size if the rlookup table */ 226 227 enum iommu_init_state { 228 IOMMU_START_STATE, 229 IOMMU_IVRS_DETECTED, 230 IOMMU_ACPI_FINISHED, 231 IOMMU_ENABLED, 232 IOMMU_PCI_INIT, 233 IOMMU_INTERRUPTS_EN, 234 IOMMU_INITIALIZED, 235 IOMMU_NOT_FOUND, 236 IOMMU_INIT_ERROR, 237 IOMMU_CMDLINE_DISABLED, 238 }; 239 240 /* Early ioapic and hpet maps from kernel command line */ 241 #define EARLY_MAP_SIZE 4 242 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 243 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 244 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 245 246 static int __initdata early_ioapic_map_size; 247 static int __initdata early_hpet_map_size; 248 static int __initdata early_acpihid_map_size; 249 250 static bool __initdata cmdline_maps; 251 252 static enum iommu_init_state init_state = IOMMU_START_STATE; 253 254 static int amd_iommu_enable_interrupts(void); 255 static int __init iommu_go_to_state(enum iommu_init_state state); 256 static void init_device_table_dma(void); 257 258 static bool amd_iommu_pre_enabled = true; 259 260 static u32 amd_iommu_ivinfo __initdata; 261 262 bool translation_pre_enabled(struct amd_iommu *iommu) 263 { 264 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 265 } 266 267 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 268 { 269 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 270 } 271 272 static void init_translation_status(struct amd_iommu *iommu) 273 { 274 u64 ctrl; 275 276 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 277 if (ctrl & (1<<CONTROL_IOMMU_EN)) 278 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 279 } 280 281 static inline void update_last_devid(u16 devid) 282 { 283 if (devid > amd_iommu_last_bdf) 284 amd_iommu_last_bdf = devid; 285 } 286 287 static inline unsigned long tbl_size(int entry_size) 288 { 289 unsigned shift = PAGE_SHIFT + 290 get_order(((int)amd_iommu_last_bdf + 1) * entry_size); 291 292 return 1UL << shift; 293 } 294 295 int amd_iommu_get_num_iommus(void) 296 { 297 return amd_iommus_present; 298 } 299 300 #ifdef CONFIG_IRQ_REMAP 301 static bool check_feature_on_all_iommus(u64 mask) 302 { 303 bool ret = false; 304 struct amd_iommu *iommu; 305 306 for_each_iommu(iommu) { 307 ret = iommu_feature(iommu, mask); 308 if (!ret) 309 return false; 310 } 311 312 return true; 313 } 314 #endif 315 316 /* 317 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 318 * Default to IVHD EFR since it is available sooner 319 * (i.e. before PCI init). 320 */ 321 static void __init early_iommu_features_init(struct amd_iommu *iommu, 322 struct ivhd_header *h) 323 { 324 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) 325 iommu->features = h->efr_reg; 326 } 327 328 /* Access to l1 and l2 indexed register spaces */ 329 330 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 331 { 332 u32 val; 333 334 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 335 pci_read_config_dword(iommu->dev, 0xfc, &val); 336 return val; 337 } 338 339 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 340 { 341 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 342 pci_write_config_dword(iommu->dev, 0xfc, val); 343 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 344 } 345 346 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 347 { 348 u32 val; 349 350 pci_write_config_dword(iommu->dev, 0xf0, address); 351 pci_read_config_dword(iommu->dev, 0xf4, &val); 352 return val; 353 } 354 355 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 356 { 357 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 358 pci_write_config_dword(iommu->dev, 0xf4, val); 359 } 360 361 /**************************************************************************** 362 * 363 * AMD IOMMU MMIO register space handling functions 364 * 365 * These functions are used to program the IOMMU device registers in 366 * MMIO space required for that driver. 367 * 368 ****************************************************************************/ 369 370 /* 371 * This function set the exclusion range in the IOMMU. DMA accesses to the 372 * exclusion range are passed through untranslated 373 */ 374 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 375 { 376 u64 start = iommu->exclusion_start & PAGE_MASK; 377 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 378 u64 entry; 379 380 if (!iommu->exclusion_start) 381 return; 382 383 entry = start | MMIO_EXCL_ENABLE_MASK; 384 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 385 &entry, sizeof(entry)); 386 387 entry = limit; 388 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 389 &entry, sizeof(entry)); 390 } 391 392 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 393 { 394 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 395 u64 entry = start & PM_ADDR_MASK; 396 397 if (!iommu_feature(iommu, FEATURE_SNP)) 398 return; 399 400 /* Note: 401 * Re-purpose Exclusion base/limit registers for Completion wait 402 * write-back base/limit. 403 */ 404 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 405 &entry, sizeof(entry)); 406 407 /* Note: 408 * Default to 4 Kbytes, which can be specified by setting base 409 * address equal to the limit address. 410 */ 411 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 412 &entry, sizeof(entry)); 413 } 414 415 /* Programs the physical address of the device table into the IOMMU hardware */ 416 static void iommu_set_device_table(struct amd_iommu *iommu) 417 { 418 u64 entry; 419 420 BUG_ON(iommu->mmio_base == NULL); 421 422 entry = iommu_virt_to_phys(amd_iommu_dev_table); 423 entry |= (dev_table_size >> 12) - 1; 424 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 425 &entry, sizeof(entry)); 426 } 427 428 /* Generic functions to enable/disable certain features of the IOMMU. */ 429 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 430 { 431 u64 ctrl; 432 433 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 434 ctrl |= (1ULL << bit); 435 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 436 } 437 438 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 439 { 440 u64 ctrl; 441 442 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 443 ctrl &= ~(1ULL << bit); 444 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 445 } 446 447 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) 448 { 449 u64 ctrl; 450 451 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 452 ctrl &= ~CTRL_INV_TO_MASK; 453 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; 454 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 455 } 456 457 /* Function to enable the hardware */ 458 static void iommu_enable(struct amd_iommu *iommu) 459 { 460 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 461 } 462 463 static void iommu_disable(struct amd_iommu *iommu) 464 { 465 if (!iommu->mmio_base) 466 return; 467 468 /* Disable command buffer */ 469 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 470 471 /* Disable event logging and event interrupts */ 472 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 473 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 474 475 /* Disable IOMMU GA_LOG */ 476 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 477 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 478 479 /* Disable IOMMU hardware itself */ 480 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 481 } 482 483 /* 484 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 485 * the system has one. 486 */ 487 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 488 { 489 if (!request_mem_region(address, end, "amd_iommu")) { 490 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 491 address, end); 492 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 493 return NULL; 494 } 495 496 return (u8 __iomem *)ioremap(address, end); 497 } 498 499 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 500 { 501 if (iommu->mmio_base) 502 iounmap(iommu->mmio_base); 503 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 504 } 505 506 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 507 { 508 u32 size = 0; 509 510 switch (h->type) { 511 case 0x10: 512 size = 24; 513 break; 514 case 0x11: 515 case 0x40: 516 size = 40; 517 break; 518 } 519 return size; 520 } 521 522 /**************************************************************************** 523 * 524 * The functions below belong to the first pass of AMD IOMMU ACPI table 525 * parsing. In this pass we try to find out the highest device id this 526 * code has to handle. Upon this information the size of the shared data 527 * structures is determined later. 528 * 529 ****************************************************************************/ 530 531 /* 532 * This function calculates the length of a given IVHD entry 533 */ 534 static inline int ivhd_entry_length(u8 *ivhd) 535 { 536 u32 type = ((struct ivhd_entry *)ivhd)->type; 537 538 if (type < 0x80) { 539 return 0x04 << (*ivhd >> 6); 540 } else if (type == IVHD_DEV_ACPI_HID) { 541 /* For ACPI_HID, offset 21 is uid len */ 542 return *((u8 *)ivhd + 21) + 22; 543 } 544 return 0; 545 } 546 547 /* 548 * After reading the highest device id from the IOMMU PCI capability header 549 * this function looks if there is a higher device id defined in the ACPI table 550 */ 551 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 552 { 553 u8 *p = (void *)h, *end = (void *)h; 554 struct ivhd_entry *dev; 555 556 u32 ivhd_size = get_ivhd_header_size(h); 557 558 if (!ivhd_size) { 559 pr_err("Unsupported IVHD type %#x\n", h->type); 560 return -EINVAL; 561 } 562 563 p += ivhd_size; 564 end += h->length; 565 566 while (p < end) { 567 dev = (struct ivhd_entry *)p; 568 switch (dev->type) { 569 case IVHD_DEV_ALL: 570 /* Use maximum BDF value for DEV_ALL */ 571 update_last_devid(0xffff); 572 break; 573 case IVHD_DEV_SELECT: 574 case IVHD_DEV_RANGE_END: 575 case IVHD_DEV_ALIAS: 576 case IVHD_DEV_EXT_SELECT: 577 /* all the above subfield types refer to device ids */ 578 update_last_devid(dev->devid); 579 break; 580 default: 581 break; 582 } 583 p += ivhd_entry_length(p); 584 } 585 586 WARN_ON(p != end); 587 588 return 0; 589 } 590 591 static int __init check_ivrs_checksum(struct acpi_table_header *table) 592 { 593 int i; 594 u8 checksum = 0, *p = (u8 *)table; 595 596 for (i = 0; i < table->length; ++i) 597 checksum += p[i]; 598 if (checksum != 0) { 599 /* ACPI table corrupt */ 600 pr_err(FW_BUG "IVRS invalid checksum\n"); 601 return -ENODEV; 602 } 603 604 return 0; 605 } 606 607 /* 608 * Iterate over all IVHD entries in the ACPI table and find the highest device 609 * id which we need to handle. This is the first of three functions which parse 610 * the ACPI table. So we check the checksum here. 611 */ 612 static int __init find_last_devid_acpi(struct acpi_table_header *table) 613 { 614 u8 *p = (u8 *)table, *end = (u8 *)table; 615 struct ivhd_header *h; 616 617 p += IVRS_HEADER_LENGTH; 618 619 end += table->length; 620 while (p < end) { 621 h = (struct ivhd_header *)p; 622 if (h->type == amd_iommu_target_ivhd_type) { 623 int ret = find_last_devid_from_ivhd(h); 624 625 if (ret) 626 return ret; 627 } 628 p += h->length; 629 } 630 WARN_ON(p != end); 631 632 return 0; 633 } 634 635 /**************************************************************************** 636 * 637 * The following functions belong to the code path which parses the ACPI table 638 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 639 * data structures, initialize the device/alias/rlookup table and also 640 * basically initialize the hardware. 641 * 642 ****************************************************************************/ 643 644 /* 645 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 646 * write commands to that buffer later and the IOMMU will execute them 647 * asynchronously 648 */ 649 static int __init alloc_command_buffer(struct amd_iommu *iommu) 650 { 651 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 652 get_order(CMD_BUFFER_SIZE)); 653 654 return iommu->cmd_buf ? 0 : -ENOMEM; 655 } 656 657 /* 658 * This function resets the command buffer if the IOMMU stopped fetching 659 * commands from it. 660 */ 661 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 662 { 663 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 664 665 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 666 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 667 iommu->cmd_buf_head = 0; 668 iommu->cmd_buf_tail = 0; 669 670 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 671 } 672 673 /* 674 * This function writes the command buffer address to the hardware and 675 * enables it. 676 */ 677 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 678 { 679 u64 entry; 680 681 BUG_ON(iommu->cmd_buf == NULL); 682 683 entry = iommu_virt_to_phys(iommu->cmd_buf); 684 entry |= MMIO_CMD_SIZE_512; 685 686 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 687 &entry, sizeof(entry)); 688 689 amd_iommu_reset_cmd_buffer(iommu); 690 } 691 692 /* 693 * This function disables the command buffer 694 */ 695 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 696 { 697 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 698 } 699 700 static void __init free_command_buffer(struct amd_iommu *iommu) 701 { 702 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); 703 } 704 705 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, 706 gfp_t gfp, size_t size) 707 { 708 int order = get_order(size); 709 void *buf = (void *)__get_free_pages(gfp, order); 710 711 if (buf && 712 iommu_feature(iommu, FEATURE_SNP) && 713 set_memory_4k((unsigned long)buf, (1 << order))) { 714 free_pages((unsigned long)buf, order); 715 buf = NULL; 716 } 717 718 return buf; 719 } 720 721 /* allocates the memory where the IOMMU will log its events to */ 722 static int __init alloc_event_buffer(struct amd_iommu *iommu) 723 { 724 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 725 EVT_BUFFER_SIZE); 726 727 return iommu->evt_buf ? 0 : -ENOMEM; 728 } 729 730 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 731 { 732 u64 entry; 733 734 BUG_ON(iommu->evt_buf == NULL); 735 736 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 737 738 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 739 &entry, sizeof(entry)); 740 741 /* set head and tail to zero manually */ 742 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 743 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 744 745 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 746 } 747 748 /* 749 * This function disables the event log buffer 750 */ 751 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 752 { 753 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 754 } 755 756 static void __init free_event_buffer(struct amd_iommu *iommu) 757 { 758 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); 759 } 760 761 /* allocates the memory where the IOMMU will log its events to */ 762 static int __init alloc_ppr_log(struct amd_iommu *iommu) 763 { 764 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 765 PPR_LOG_SIZE); 766 767 return iommu->ppr_log ? 0 : -ENOMEM; 768 } 769 770 static void iommu_enable_ppr_log(struct amd_iommu *iommu) 771 { 772 u64 entry; 773 774 if (iommu->ppr_log == NULL) 775 return; 776 777 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; 778 779 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, 780 &entry, sizeof(entry)); 781 782 /* set head and tail to zero manually */ 783 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 784 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 785 786 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); 787 iommu_feature_enable(iommu, CONTROL_PPR_EN); 788 } 789 790 static void __init free_ppr_log(struct amd_iommu *iommu) 791 { 792 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); 793 } 794 795 static void free_ga_log(struct amd_iommu *iommu) 796 { 797 #ifdef CONFIG_IRQ_REMAP 798 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); 799 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); 800 #endif 801 } 802 803 static int iommu_ga_log_enable(struct amd_iommu *iommu) 804 { 805 #ifdef CONFIG_IRQ_REMAP 806 u32 status, i; 807 808 if (!iommu->ga_log) 809 return -EINVAL; 810 811 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 812 813 /* Check if already running */ 814 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 815 return 0; 816 817 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 818 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 819 820 for (i = 0; i < LOOP_TIMEOUT; ++i) { 821 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 822 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 823 break; 824 } 825 826 if (i >= LOOP_TIMEOUT) 827 return -EINVAL; 828 #endif /* CONFIG_IRQ_REMAP */ 829 return 0; 830 } 831 832 static int iommu_init_ga_log(struct amd_iommu *iommu) 833 { 834 #ifdef CONFIG_IRQ_REMAP 835 u64 entry; 836 837 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 838 return 0; 839 840 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 841 get_order(GA_LOG_SIZE)); 842 if (!iommu->ga_log) 843 goto err_out; 844 845 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 846 get_order(8)); 847 if (!iommu->ga_log_tail) 848 goto err_out; 849 850 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 851 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 852 &entry, sizeof(entry)); 853 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 854 (BIT_ULL(52)-1)) & ~7ULL; 855 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 856 &entry, sizeof(entry)); 857 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 858 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 859 860 return 0; 861 err_out: 862 free_ga_log(iommu); 863 return -EINVAL; 864 #else 865 return 0; 866 #endif /* CONFIG_IRQ_REMAP */ 867 } 868 869 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 870 { 871 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); 872 873 return iommu->cmd_sem ? 0 : -ENOMEM; 874 } 875 876 static void __init free_cwwb_sem(struct amd_iommu *iommu) 877 { 878 if (iommu->cmd_sem) 879 free_page((unsigned long)iommu->cmd_sem); 880 } 881 882 static void iommu_enable_xt(struct amd_iommu *iommu) 883 { 884 #ifdef CONFIG_IRQ_REMAP 885 /* 886 * XT mode (32-bit APIC destination ID) requires 887 * GA mode (128-bit IRTE support) as a prerequisite. 888 */ 889 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 890 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 891 iommu_feature_enable(iommu, CONTROL_XT_EN); 892 #endif /* CONFIG_IRQ_REMAP */ 893 } 894 895 static void iommu_enable_gt(struct amd_iommu *iommu) 896 { 897 if (!iommu_feature(iommu, FEATURE_GT)) 898 return; 899 900 iommu_feature_enable(iommu, CONTROL_GT_EN); 901 } 902 903 /* sets a specific bit in the device table entry. */ 904 static void set_dev_entry_bit(u16 devid, u8 bit) 905 { 906 int i = (bit >> 6) & 0x03; 907 int _bit = bit & 0x3f; 908 909 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); 910 } 911 912 static int get_dev_entry_bit(u16 devid, u8 bit) 913 { 914 int i = (bit >> 6) & 0x03; 915 int _bit = bit & 0x3f; 916 917 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; 918 } 919 920 921 static bool copy_device_table(void) 922 { 923 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0; 924 struct dev_table_entry *old_devtb = NULL; 925 u32 lo, hi, devid, old_devtb_size; 926 phys_addr_t old_devtb_phys; 927 struct amd_iommu *iommu; 928 u16 dom_id, dte_v, irq_v; 929 gfp_t gfp_flag; 930 u64 tmp; 931 932 if (!amd_iommu_pre_enabled) 933 return false; 934 935 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 936 for_each_iommu(iommu) { 937 /* All IOMMUs should use the same device table with the same size */ 938 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 939 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 940 entry = (((u64) hi) << 32) + lo; 941 if (last_entry && last_entry != entry) { 942 pr_err("IOMMU:%d should use the same dev table as others!\n", 943 iommu->index); 944 return false; 945 } 946 last_entry = entry; 947 948 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 949 if (old_devtb_size != dev_table_size) { 950 pr_err("The device table size of IOMMU:%d is not expected!\n", 951 iommu->index); 952 return false; 953 } 954 } 955 956 /* 957 * When SME is enabled in the first kernel, the entry includes the 958 * memory encryption mask(sme_me_mask), we must remove the memory 959 * encryption mask to obtain the true physical address in kdump kernel. 960 */ 961 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 962 963 if (old_devtb_phys >= 0x100000000ULL) { 964 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 965 return false; 966 } 967 old_devtb = (sme_active() && is_kdump_kernel()) 968 ? (__force void *)ioremap_encrypted(old_devtb_phys, 969 dev_table_size) 970 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB); 971 972 if (!old_devtb) 973 return false; 974 975 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32; 976 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag, 977 get_order(dev_table_size)); 978 if (old_dev_tbl_cpy == NULL) { 979 pr_err("Failed to allocate memory for copying old device table!\n"); 980 return false; 981 } 982 983 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 984 old_dev_tbl_cpy[devid] = old_devtb[devid]; 985 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 986 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 987 988 if (dte_v && dom_id) { 989 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 990 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 991 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap); 992 /* If gcr3 table existed, mask it out */ 993 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 994 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 995 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 996 old_dev_tbl_cpy[devid].data[1] &= ~tmp; 997 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; 998 tmp |= DTE_FLAG_GV; 999 old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1000 } 1001 } 1002 1003 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1004 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1005 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; 1006 if (irq_v && (int_ctl || int_tab_len)) { 1007 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1008 (int_tab_len != DTE_INTTABLEN)) { 1009 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1010 return false; 1011 } 1012 1013 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1014 } 1015 } 1016 memunmap(old_devtb); 1017 1018 return true; 1019 } 1020 1021 void amd_iommu_apply_erratum_63(u16 devid) 1022 { 1023 int sysmgt; 1024 1025 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | 1026 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); 1027 1028 if (sysmgt == 0x01) 1029 set_dev_entry_bit(devid, DEV_ENTRY_IW); 1030 } 1031 1032 /* Writes the specific IOMMU for a device into the rlookup table */ 1033 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) 1034 { 1035 amd_iommu_rlookup_table[devid] = iommu; 1036 } 1037 1038 /* 1039 * This function takes the device specific flags read from the ACPI 1040 * table and sets up the device table entry with that information 1041 */ 1042 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1043 u16 devid, u32 flags, u32 ext_flags) 1044 { 1045 if (flags & ACPI_DEVFLAG_INITPASS) 1046 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); 1047 if (flags & ACPI_DEVFLAG_EXTINT) 1048 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); 1049 if (flags & ACPI_DEVFLAG_NMI) 1050 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); 1051 if (flags & ACPI_DEVFLAG_SYSMGT1) 1052 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); 1053 if (flags & ACPI_DEVFLAG_SYSMGT2) 1054 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); 1055 if (flags & ACPI_DEVFLAG_LINT0) 1056 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); 1057 if (flags & ACPI_DEVFLAG_LINT1) 1058 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); 1059 1060 amd_iommu_apply_erratum_63(devid); 1061 1062 set_iommu_for_device(iommu, devid); 1063 } 1064 1065 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line) 1066 { 1067 struct devid_map *entry; 1068 struct list_head *list; 1069 1070 if (type == IVHD_SPECIAL_IOAPIC) 1071 list = &ioapic_map; 1072 else if (type == IVHD_SPECIAL_HPET) 1073 list = &hpet_map; 1074 else 1075 return -EINVAL; 1076 1077 list_for_each_entry(entry, list, list) { 1078 if (!(entry->id == id && entry->cmd_line)) 1079 continue; 1080 1081 pr_info("Command-line override present for %s id %d - ignoring\n", 1082 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1083 1084 *devid = entry->devid; 1085 1086 return 0; 1087 } 1088 1089 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1090 if (!entry) 1091 return -ENOMEM; 1092 1093 entry->id = id; 1094 entry->devid = *devid; 1095 entry->cmd_line = cmd_line; 1096 1097 list_add_tail(&entry->list, list); 1098 1099 return 0; 1100 } 1101 1102 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid, 1103 bool cmd_line) 1104 { 1105 struct acpihid_map_entry *entry; 1106 struct list_head *list = &acpihid_map; 1107 1108 list_for_each_entry(entry, list, list) { 1109 if (strcmp(entry->hid, hid) || 1110 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1111 !entry->cmd_line) 1112 continue; 1113 1114 pr_info("Command-line override for hid:%s uid:%s\n", 1115 hid, uid); 1116 *devid = entry->devid; 1117 return 0; 1118 } 1119 1120 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1121 if (!entry) 1122 return -ENOMEM; 1123 1124 memcpy(entry->uid, uid, strlen(uid)); 1125 memcpy(entry->hid, hid, strlen(hid)); 1126 entry->devid = *devid; 1127 entry->cmd_line = cmd_line; 1128 entry->root_devid = (entry->devid & (~0x7)); 1129 1130 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n", 1131 entry->cmd_line ? "cmd" : "ivrs", 1132 entry->hid, entry->uid, entry->root_devid); 1133 1134 list_add_tail(&entry->list, list); 1135 return 0; 1136 } 1137 1138 static int __init add_early_maps(void) 1139 { 1140 int i, ret; 1141 1142 for (i = 0; i < early_ioapic_map_size; ++i) { 1143 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1144 early_ioapic_map[i].id, 1145 &early_ioapic_map[i].devid, 1146 early_ioapic_map[i].cmd_line); 1147 if (ret) 1148 return ret; 1149 } 1150 1151 for (i = 0; i < early_hpet_map_size; ++i) { 1152 ret = add_special_device(IVHD_SPECIAL_HPET, 1153 early_hpet_map[i].id, 1154 &early_hpet_map[i].devid, 1155 early_hpet_map[i].cmd_line); 1156 if (ret) 1157 return ret; 1158 } 1159 1160 for (i = 0; i < early_acpihid_map_size; ++i) { 1161 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1162 early_acpihid_map[i].uid, 1163 &early_acpihid_map[i].devid, 1164 early_acpihid_map[i].cmd_line); 1165 if (ret) 1166 return ret; 1167 } 1168 1169 return 0; 1170 } 1171 1172 /* 1173 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1174 * initializes the hardware and our data structures with it. 1175 */ 1176 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1177 struct ivhd_header *h) 1178 { 1179 u8 *p = (u8 *)h; 1180 u8 *end = p, flags = 0; 1181 u16 devid = 0, devid_start = 0, devid_to = 0; 1182 u32 dev_i, ext_flags = 0; 1183 bool alias = false; 1184 struct ivhd_entry *e; 1185 u32 ivhd_size; 1186 int ret; 1187 1188 1189 ret = add_early_maps(); 1190 if (ret) 1191 return ret; 1192 1193 amd_iommu_apply_ivrs_quirks(); 1194 1195 /* 1196 * First save the recommended feature enable bits from ACPI 1197 */ 1198 iommu->acpi_flags = h->flags; 1199 1200 /* 1201 * Done. Now parse the device entries 1202 */ 1203 ivhd_size = get_ivhd_header_size(h); 1204 if (!ivhd_size) { 1205 pr_err("Unsupported IVHD type %#x\n", h->type); 1206 return -EINVAL; 1207 } 1208 1209 p += ivhd_size; 1210 1211 end += h->length; 1212 1213 1214 while (p < end) { 1215 e = (struct ivhd_entry *)p; 1216 switch (e->type) { 1217 case IVHD_DEV_ALL: 1218 1219 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); 1220 1221 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i) 1222 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); 1223 break; 1224 case IVHD_DEV_SELECT: 1225 1226 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " 1227 "flags: %02x\n", 1228 PCI_BUS_NUM(e->devid), 1229 PCI_SLOT(e->devid), 1230 PCI_FUNC(e->devid), 1231 e->flags); 1232 1233 devid = e->devid; 1234 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1235 break; 1236 case IVHD_DEV_SELECT_RANGE_START: 1237 1238 DUMP_printk(" DEV_SELECT_RANGE_START\t " 1239 "devid: %02x:%02x.%x flags: %02x\n", 1240 PCI_BUS_NUM(e->devid), 1241 PCI_SLOT(e->devid), 1242 PCI_FUNC(e->devid), 1243 e->flags); 1244 1245 devid_start = e->devid; 1246 flags = e->flags; 1247 ext_flags = 0; 1248 alias = false; 1249 break; 1250 case IVHD_DEV_ALIAS: 1251 1252 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " 1253 "flags: %02x devid_to: %02x:%02x.%x\n", 1254 PCI_BUS_NUM(e->devid), 1255 PCI_SLOT(e->devid), 1256 PCI_FUNC(e->devid), 1257 e->flags, 1258 PCI_BUS_NUM(e->ext >> 8), 1259 PCI_SLOT(e->ext >> 8), 1260 PCI_FUNC(e->ext >> 8)); 1261 1262 devid = e->devid; 1263 devid_to = e->ext >> 8; 1264 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1265 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1266 amd_iommu_alias_table[devid] = devid_to; 1267 break; 1268 case IVHD_DEV_ALIAS_RANGE: 1269 1270 DUMP_printk(" DEV_ALIAS_RANGE\t\t " 1271 "devid: %02x:%02x.%x flags: %02x " 1272 "devid_to: %02x:%02x.%x\n", 1273 PCI_BUS_NUM(e->devid), 1274 PCI_SLOT(e->devid), 1275 PCI_FUNC(e->devid), 1276 e->flags, 1277 PCI_BUS_NUM(e->ext >> 8), 1278 PCI_SLOT(e->ext >> 8), 1279 PCI_FUNC(e->ext >> 8)); 1280 1281 devid_start = e->devid; 1282 flags = e->flags; 1283 devid_to = e->ext >> 8; 1284 ext_flags = 0; 1285 alias = true; 1286 break; 1287 case IVHD_DEV_EXT_SELECT: 1288 1289 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " 1290 "flags: %02x ext: %08x\n", 1291 PCI_BUS_NUM(e->devid), 1292 PCI_SLOT(e->devid), 1293 PCI_FUNC(e->devid), 1294 e->flags, e->ext); 1295 1296 devid = e->devid; 1297 set_dev_entry_from_acpi(iommu, devid, e->flags, 1298 e->ext); 1299 break; 1300 case IVHD_DEV_EXT_SELECT_RANGE: 1301 1302 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " 1303 "%02x:%02x.%x flags: %02x ext: %08x\n", 1304 PCI_BUS_NUM(e->devid), 1305 PCI_SLOT(e->devid), 1306 PCI_FUNC(e->devid), 1307 e->flags, e->ext); 1308 1309 devid_start = e->devid; 1310 flags = e->flags; 1311 ext_flags = e->ext; 1312 alias = false; 1313 break; 1314 case IVHD_DEV_RANGE_END: 1315 1316 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", 1317 PCI_BUS_NUM(e->devid), 1318 PCI_SLOT(e->devid), 1319 PCI_FUNC(e->devid)); 1320 1321 devid = e->devid; 1322 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1323 if (alias) { 1324 amd_iommu_alias_table[dev_i] = devid_to; 1325 set_dev_entry_from_acpi(iommu, 1326 devid_to, flags, ext_flags); 1327 } 1328 set_dev_entry_from_acpi(iommu, dev_i, 1329 flags, ext_flags); 1330 } 1331 break; 1332 case IVHD_DEV_SPECIAL: { 1333 u8 handle, type; 1334 const char *var; 1335 u16 devid; 1336 int ret; 1337 1338 handle = e->ext & 0xff; 1339 devid = (e->ext >> 8) & 0xffff; 1340 type = (e->ext >> 24) & 0xff; 1341 1342 if (type == IVHD_SPECIAL_IOAPIC) 1343 var = "IOAPIC"; 1344 else if (type == IVHD_SPECIAL_HPET) 1345 var = "HPET"; 1346 else 1347 var = "UNKNOWN"; 1348 1349 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", 1350 var, (int)handle, 1351 PCI_BUS_NUM(devid), 1352 PCI_SLOT(devid), 1353 PCI_FUNC(devid)); 1354 1355 ret = add_special_device(type, handle, &devid, false); 1356 if (ret) 1357 return ret; 1358 1359 /* 1360 * add_special_device might update the devid in case a 1361 * command-line override is present. So call 1362 * set_dev_entry_from_acpi after add_special_device. 1363 */ 1364 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1365 1366 break; 1367 } 1368 case IVHD_DEV_ACPI_HID: { 1369 u16 devid; 1370 u8 hid[ACPIHID_HID_LEN]; 1371 u8 uid[ACPIHID_UID_LEN]; 1372 int ret; 1373 1374 if (h->type != 0x40) { 1375 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1376 e->type); 1377 break; 1378 } 1379 1380 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1); 1381 hid[ACPIHID_HID_LEN - 1] = '\0'; 1382 1383 if (!(*hid)) { 1384 pr_err(FW_BUG "Invalid HID.\n"); 1385 break; 1386 } 1387 1388 uid[0] = '\0'; 1389 switch (e->uidf) { 1390 case UID_NOT_PRESENT: 1391 1392 if (e->uidl != 0) 1393 pr_warn(FW_BUG "Invalid UID length.\n"); 1394 1395 break; 1396 case UID_IS_INTEGER: 1397 1398 sprintf(uid, "%d", e->uid); 1399 1400 break; 1401 case UID_IS_CHARACTER: 1402 1403 memcpy(uid, &e->uid, e->uidl); 1404 uid[e->uidl] = '\0'; 1405 1406 break; 1407 default: 1408 break; 1409 } 1410 1411 devid = e->devid; 1412 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n", 1413 hid, uid, 1414 PCI_BUS_NUM(devid), 1415 PCI_SLOT(devid), 1416 PCI_FUNC(devid)); 1417 1418 flags = e->flags; 1419 1420 ret = add_acpi_hid_device(hid, uid, &devid, false); 1421 if (ret) 1422 return ret; 1423 1424 /* 1425 * add_special_device might update the devid in case a 1426 * command-line override is present. So call 1427 * set_dev_entry_from_acpi after add_special_device. 1428 */ 1429 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1430 1431 break; 1432 } 1433 default: 1434 break; 1435 } 1436 1437 p += ivhd_entry_length(p); 1438 } 1439 1440 return 0; 1441 } 1442 1443 static void __init free_iommu_one(struct amd_iommu *iommu) 1444 { 1445 free_cwwb_sem(iommu); 1446 free_command_buffer(iommu); 1447 free_event_buffer(iommu); 1448 free_ppr_log(iommu); 1449 free_ga_log(iommu); 1450 iommu_unmap_mmio_space(iommu); 1451 } 1452 1453 static void __init free_iommu_all(void) 1454 { 1455 struct amd_iommu *iommu, *next; 1456 1457 for_each_iommu_safe(iommu, next) { 1458 list_del(&iommu->list); 1459 free_iommu_one(iommu); 1460 kfree(iommu); 1461 } 1462 } 1463 1464 /* 1465 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1466 * Workaround: 1467 * BIOS should disable L2B micellaneous clock gating by setting 1468 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1469 */ 1470 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1471 { 1472 u32 value; 1473 1474 if ((boot_cpu_data.x86 != 0x15) || 1475 (boot_cpu_data.x86_model < 0x10) || 1476 (boot_cpu_data.x86_model > 0x1f)) 1477 return; 1478 1479 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1480 pci_read_config_dword(iommu->dev, 0xf4, &value); 1481 1482 if (value & BIT(2)) 1483 return; 1484 1485 /* Select NB indirect register 0x90 and enable writing */ 1486 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1487 1488 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1489 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1490 1491 /* Clear the enable writing bit */ 1492 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1493 } 1494 1495 /* 1496 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1497 * Workaround: 1498 * BIOS should enable ATS write permission check by setting 1499 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1500 */ 1501 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1502 { 1503 u32 value; 1504 1505 if ((boot_cpu_data.x86 != 0x15) || 1506 (boot_cpu_data.x86_model < 0x30) || 1507 (boot_cpu_data.x86_model > 0x3f)) 1508 return; 1509 1510 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1511 value = iommu_read_l2(iommu, 0x47); 1512 1513 if (value & BIT(0)) 1514 return; 1515 1516 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1517 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1518 1519 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1520 } 1521 1522 /* 1523 * This function clues the initialization function for one IOMMU 1524 * together and also allocates the command buffer and programs the 1525 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1526 */ 1527 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) 1528 { 1529 int ret; 1530 1531 raw_spin_lock_init(&iommu->lock); 1532 iommu->cmd_sem_val = 0; 1533 1534 /* Add IOMMU to internal data structures */ 1535 list_add_tail(&iommu->list, &amd_iommu_list); 1536 iommu->index = amd_iommus_present++; 1537 1538 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1539 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1540 return -ENOSYS; 1541 } 1542 1543 /* Index is fine - add IOMMU to the array */ 1544 amd_iommus[iommu->index] = iommu; 1545 1546 /* 1547 * Copy data from ACPI table entry to the iommu struct 1548 */ 1549 iommu->devid = h->devid; 1550 iommu->cap_ptr = h->cap_ptr; 1551 iommu->pci_seg = h->pci_seg; 1552 iommu->mmio_phys = h->mmio_phys; 1553 1554 switch (h->type) { 1555 case 0x10: 1556 /* Check if IVHD EFR contains proper max banks/counters */ 1557 if ((h->efr_attr != 0) && 1558 ((h->efr_attr & (0xF << 13)) != 0) && 1559 ((h->efr_attr & (0x3F << 17)) != 0)) 1560 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1561 else 1562 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1563 1564 /* 1565 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1566 * GAM also requires GA mode. Therefore, we need to 1567 * check cmpxchg16b support before enabling it. 1568 */ 1569 if (!boot_cpu_has(X86_FEATURE_CX16) || 1570 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) 1571 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1572 break; 1573 case 0x11: 1574 case 0x40: 1575 if (h->efr_reg & (1 << 9)) 1576 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1577 else 1578 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1579 1580 /* 1581 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1582 * XT, GAM also requires GA mode. Therefore, we need to 1583 * check cmpxchg16b support before enabling them. 1584 */ 1585 if (!boot_cpu_has(X86_FEATURE_CX16) || 1586 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) { 1587 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1588 break; 1589 } 1590 1591 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1592 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1593 1594 early_iommu_features_init(iommu, h); 1595 1596 break; 1597 default: 1598 return -EINVAL; 1599 } 1600 1601 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1602 iommu->mmio_phys_end); 1603 if (!iommu->mmio_base) 1604 return -ENOMEM; 1605 1606 if (alloc_cwwb_sem(iommu)) 1607 return -ENOMEM; 1608 1609 if (alloc_command_buffer(iommu)) 1610 return -ENOMEM; 1611 1612 if (alloc_event_buffer(iommu)) 1613 return -ENOMEM; 1614 1615 iommu->int_enabled = false; 1616 1617 init_translation_status(iommu); 1618 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1619 iommu_disable(iommu); 1620 clear_translation_pre_enabled(iommu); 1621 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1622 iommu->index); 1623 } 1624 if (amd_iommu_pre_enabled) 1625 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1626 1627 ret = init_iommu_from_acpi(iommu, h); 1628 if (ret) 1629 return ret; 1630 1631 if (amd_iommu_irq_remap) { 1632 ret = amd_iommu_create_irq_domain(iommu); 1633 if (ret) 1634 return ret; 1635 } 1636 1637 /* 1638 * Make sure IOMMU is not considered to translate itself. The IVRS 1639 * table tells us so, but this is a lie! 1640 */ 1641 amd_iommu_rlookup_table[iommu->devid] = NULL; 1642 1643 return 0; 1644 } 1645 1646 /** 1647 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1648 * @ivrs: Pointer to the IVRS header 1649 * 1650 * This function search through all IVDB of the maximum supported IVHD 1651 */ 1652 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1653 { 1654 u8 *base = (u8 *)ivrs; 1655 struct ivhd_header *ivhd = (struct ivhd_header *) 1656 (base + IVRS_HEADER_LENGTH); 1657 u8 last_type = ivhd->type; 1658 u16 devid = ivhd->devid; 1659 1660 while (((u8 *)ivhd - base < ivrs->length) && 1661 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1662 u8 *p = (u8 *) ivhd; 1663 1664 if (ivhd->devid == devid) 1665 last_type = ivhd->type; 1666 ivhd = (struct ivhd_header *)(p + ivhd->length); 1667 } 1668 1669 return last_type; 1670 } 1671 1672 /* 1673 * Iterates over all IOMMU entries in the ACPI table, allocates the 1674 * IOMMU structure and initializes it with init_iommu_one() 1675 */ 1676 static int __init init_iommu_all(struct acpi_table_header *table) 1677 { 1678 u8 *p = (u8 *)table, *end = (u8 *)table; 1679 struct ivhd_header *h; 1680 struct amd_iommu *iommu; 1681 int ret; 1682 1683 end += table->length; 1684 p += IVRS_HEADER_LENGTH; 1685 1686 while (p < end) { 1687 h = (struct ivhd_header *)p; 1688 if (*p == amd_iommu_target_ivhd_type) { 1689 1690 DUMP_printk("device: %02x:%02x.%01x cap: %04x " 1691 "seg: %d flags: %01x info %04x\n", 1692 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid), 1693 PCI_FUNC(h->devid), h->cap_ptr, 1694 h->pci_seg, h->flags, h->info); 1695 DUMP_printk(" mmio-addr: %016llx\n", 1696 h->mmio_phys); 1697 1698 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1699 if (iommu == NULL) 1700 return -ENOMEM; 1701 1702 ret = init_iommu_one(iommu, h); 1703 if (ret) 1704 return ret; 1705 } 1706 p += h->length; 1707 1708 } 1709 WARN_ON(p != end); 1710 1711 return 0; 1712 } 1713 1714 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1715 { 1716 u64 val; 1717 struct pci_dev *pdev = iommu->dev; 1718 1719 if (!iommu_feature(iommu, FEATURE_PC)) 1720 return; 1721 1722 amd_iommu_pc_present = true; 1723 1724 pci_info(pdev, "IOMMU performance counters supported\n"); 1725 1726 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1727 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1728 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1729 1730 return; 1731 } 1732 1733 static ssize_t amd_iommu_show_cap(struct device *dev, 1734 struct device_attribute *attr, 1735 char *buf) 1736 { 1737 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1738 return sprintf(buf, "%x\n", iommu->cap); 1739 } 1740 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1741 1742 static ssize_t amd_iommu_show_features(struct device *dev, 1743 struct device_attribute *attr, 1744 char *buf) 1745 { 1746 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1747 return sprintf(buf, "%llx\n", iommu->features); 1748 } 1749 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1750 1751 static struct attribute *amd_iommu_attrs[] = { 1752 &dev_attr_cap.attr, 1753 &dev_attr_features.attr, 1754 NULL, 1755 }; 1756 1757 static struct attribute_group amd_iommu_group = { 1758 .name = "amd-iommu", 1759 .attrs = amd_iommu_attrs, 1760 }; 1761 1762 static const struct attribute_group *amd_iommu_groups[] = { 1763 &amd_iommu_group, 1764 NULL, 1765 }; 1766 1767 /* 1768 * Note: IVHD 0x11 and 0x40 also contains exact copy 1769 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1770 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1771 */ 1772 static void __init late_iommu_features_init(struct amd_iommu *iommu) 1773 { 1774 u64 features; 1775 1776 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 1777 return; 1778 1779 /* read extended feature bits */ 1780 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1781 1782 if (!iommu->features) { 1783 iommu->features = features; 1784 return; 1785 } 1786 1787 /* 1788 * Sanity check and warn if EFR values from 1789 * IVHD and MMIO conflict. 1790 */ 1791 if (features != iommu->features) 1792 pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx).\n", 1793 features, iommu->features); 1794 } 1795 1796 static int __init iommu_init_pci(struct amd_iommu *iommu) 1797 { 1798 int cap_ptr = iommu->cap_ptr; 1799 int ret; 1800 1801 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), 1802 iommu->devid & 0xff); 1803 if (!iommu->dev) 1804 return -ENODEV; 1805 1806 /* Prevent binding other PCI device drivers to IOMMU devices */ 1807 iommu->dev->match_driver = false; 1808 1809 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 1810 &iommu->cap); 1811 1812 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 1813 amd_iommu_iotlb_sup = false; 1814 1815 late_iommu_features_init(iommu); 1816 1817 if (iommu_feature(iommu, FEATURE_GT)) { 1818 int glxval; 1819 u32 max_pasid; 1820 u64 pasmax; 1821 1822 pasmax = iommu->features & FEATURE_PASID_MASK; 1823 pasmax >>= FEATURE_PASID_SHIFT; 1824 max_pasid = (1 << (pasmax + 1)) - 1; 1825 1826 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); 1827 1828 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); 1829 1830 glxval = iommu->features & FEATURE_GLXVAL_MASK; 1831 glxval >>= FEATURE_GLXVAL_SHIFT; 1832 1833 if (amd_iommu_max_glx_val == -1) 1834 amd_iommu_max_glx_val = glxval; 1835 else 1836 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 1837 } 1838 1839 if (iommu_feature(iommu, FEATURE_GT) && 1840 iommu_feature(iommu, FEATURE_PPR)) { 1841 iommu->is_iommu_v2 = true; 1842 amd_iommu_v2_present = true; 1843 } 1844 1845 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) 1846 return -ENOMEM; 1847 1848 ret = iommu_init_ga_log(iommu); 1849 if (ret) 1850 return ret; 1851 1852 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 1853 pr_info("Using strict mode due to virtualization\n"); 1854 iommu_set_dma_strict(); 1855 amd_iommu_np_cache = true; 1856 } 1857 1858 init_iommu_perf_ctr(iommu); 1859 1860 if (is_rd890_iommu(iommu->dev)) { 1861 int i, j; 1862 1863 iommu->root_pdev = 1864 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, 1865 PCI_DEVFN(0, 0)); 1866 1867 /* 1868 * Some rd890 systems may not be fully reconfigured by the 1869 * BIOS, so it's necessary for us to store this information so 1870 * it can be reprogrammed on resume 1871 */ 1872 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 1873 &iommu->stored_addr_lo); 1874 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 1875 &iommu->stored_addr_hi); 1876 1877 /* Low bit locks writes to configuration space */ 1878 iommu->stored_addr_lo &= ~1; 1879 1880 for (i = 0; i < 6; i++) 1881 for (j = 0; j < 0x12; j++) 1882 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 1883 1884 for (i = 0; i < 0x83; i++) 1885 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 1886 } 1887 1888 amd_iommu_erratum_746_workaround(iommu); 1889 amd_iommu_ats_write_check_workaround(iommu); 1890 1891 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 1892 amd_iommu_groups, "ivhd%d", iommu->index); 1893 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 1894 1895 return pci_enable_device(iommu->dev); 1896 } 1897 1898 static void print_iommu_info(void) 1899 { 1900 static const char * const feat_str[] = { 1901 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 1902 "IA", "GA", "HE", "PC" 1903 }; 1904 struct amd_iommu *iommu; 1905 1906 for_each_iommu(iommu) { 1907 struct pci_dev *pdev = iommu->dev; 1908 int i; 1909 1910 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr); 1911 1912 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { 1913 pr_info("Extended features (%#llx):", iommu->features); 1914 1915 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 1916 if (iommu_feature(iommu, (1ULL << i))) 1917 pr_cont(" %s", feat_str[i]); 1918 } 1919 1920 if (iommu->features & FEATURE_GAM_VAPIC) 1921 pr_cont(" GA_vAPIC"); 1922 1923 pr_cont("\n"); 1924 } 1925 } 1926 if (irq_remapping_enabled) { 1927 pr_info("Interrupt remapping enabled\n"); 1928 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 1929 pr_info("Virtual APIC enabled\n"); 1930 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 1931 pr_info("X2APIC enabled\n"); 1932 } 1933 } 1934 1935 static int __init amd_iommu_init_pci(void) 1936 { 1937 struct amd_iommu *iommu; 1938 int ret; 1939 1940 for_each_iommu(iommu) { 1941 ret = iommu_init_pci(iommu); 1942 if (ret) 1943 break; 1944 1945 /* Need to setup range after PCI init */ 1946 iommu_set_cwwb_range(iommu); 1947 } 1948 1949 /* 1950 * Order is important here to make sure any unity map requirements are 1951 * fulfilled. The unity mappings are created and written to the device 1952 * table during the amd_iommu_init_api() call. 1953 * 1954 * After that we call init_device_table_dma() to make sure any 1955 * uninitialized DTE will block DMA, and in the end we flush the caches 1956 * of all IOMMUs to make sure the changes to the device table are 1957 * active. 1958 */ 1959 ret = amd_iommu_init_api(); 1960 1961 init_device_table_dma(); 1962 1963 for_each_iommu(iommu) 1964 iommu_flush_all_caches(iommu); 1965 1966 if (!ret) 1967 print_iommu_info(); 1968 1969 return ret; 1970 } 1971 1972 /**************************************************************************** 1973 * 1974 * The following functions initialize the MSI interrupts for all IOMMUs 1975 * in the system. It's a bit challenging because there could be multiple 1976 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 1977 * pci_dev. 1978 * 1979 ****************************************************************************/ 1980 1981 static int iommu_setup_msi(struct amd_iommu *iommu) 1982 { 1983 int r; 1984 1985 r = pci_enable_msi(iommu->dev); 1986 if (r) 1987 return r; 1988 1989 r = request_threaded_irq(iommu->dev->irq, 1990 amd_iommu_int_handler, 1991 amd_iommu_int_thread, 1992 0, "AMD-Vi", 1993 iommu); 1994 1995 if (r) { 1996 pci_disable_msi(iommu->dev); 1997 return r; 1998 } 1999 2000 return 0; 2001 } 2002 2003 union intcapxt { 2004 u64 capxt; 2005 struct { 2006 u64 reserved_0 : 2, 2007 dest_mode_logical : 1, 2008 reserved_1 : 5, 2009 destid_0_23 : 24, 2010 vector : 8, 2011 reserved_2 : 16, 2012 destid_24_31 : 8; 2013 }; 2014 } __attribute__ ((packed)); 2015 2016 /* 2017 * There isn't really any need to mask/unmask at the irqchip level because 2018 * the 64-bit INTCAPXT registers can be updated atomically without tearing 2019 * when the affinity is being updated. 2020 */ 2021 static void intcapxt_unmask_irq(struct irq_data *data) 2022 { 2023 } 2024 2025 static void intcapxt_mask_irq(struct irq_data *data) 2026 { 2027 } 2028 2029 static struct irq_chip intcapxt_controller; 2030 2031 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2032 struct irq_data *irqd, bool reserve) 2033 { 2034 struct amd_iommu *iommu = irqd->chip_data; 2035 struct irq_cfg *cfg = irqd_cfg(irqd); 2036 union intcapxt xt; 2037 2038 xt.capxt = 0ULL; 2039 xt.dest_mode_logical = apic->dest_mode_logical; 2040 xt.vector = cfg->vector; 2041 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2042 xt.destid_24_31 = cfg->dest_apicid >> 24; 2043 2044 /** 2045 * Current IOMMU implemtation uses the same IRQ for all 2046 * 3 IOMMU interrupts. 2047 */ 2048 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2049 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2050 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2051 return 0; 2052 } 2053 2054 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2055 struct irq_data *irqd) 2056 { 2057 intcapxt_mask_irq(irqd); 2058 } 2059 2060 2061 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2062 unsigned int nr_irqs, void *arg) 2063 { 2064 struct irq_alloc_info *info = arg; 2065 int i, ret; 2066 2067 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2068 return -EINVAL; 2069 2070 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2071 if (ret < 0) 2072 return ret; 2073 2074 for (i = virq; i < virq + nr_irqs; i++) { 2075 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2076 2077 irqd->chip = &intcapxt_controller; 2078 irqd->chip_data = info->data; 2079 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2080 } 2081 2082 return ret; 2083 } 2084 2085 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2086 unsigned int nr_irqs) 2087 { 2088 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2089 } 2090 2091 static int intcapxt_set_affinity(struct irq_data *irqd, 2092 const struct cpumask *mask, bool force) 2093 { 2094 struct irq_data *parent = irqd->parent_data; 2095 int ret; 2096 2097 ret = parent->chip->irq_set_affinity(parent, mask, force); 2098 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2099 return ret; 2100 2101 return intcapxt_irqdomain_activate(irqd->domain, irqd, false); 2102 } 2103 2104 static struct irq_chip intcapxt_controller = { 2105 .name = "IOMMU-MSI", 2106 .irq_unmask = intcapxt_unmask_irq, 2107 .irq_mask = intcapxt_mask_irq, 2108 .irq_ack = irq_chip_ack_parent, 2109 .irq_retrigger = irq_chip_retrigger_hierarchy, 2110 .irq_set_affinity = intcapxt_set_affinity, 2111 .flags = IRQCHIP_SKIP_SET_WAKE, 2112 }; 2113 2114 static const struct irq_domain_ops intcapxt_domain_ops = { 2115 .alloc = intcapxt_irqdomain_alloc, 2116 .free = intcapxt_irqdomain_free, 2117 .activate = intcapxt_irqdomain_activate, 2118 .deactivate = intcapxt_irqdomain_deactivate, 2119 }; 2120 2121 2122 static struct irq_domain *iommu_irqdomain; 2123 2124 static struct irq_domain *iommu_get_irqdomain(void) 2125 { 2126 struct fwnode_handle *fn; 2127 2128 /* No need for locking here (yet) as the init is single-threaded */ 2129 if (iommu_irqdomain) 2130 return iommu_irqdomain; 2131 2132 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2133 if (!fn) 2134 return NULL; 2135 2136 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2137 fn, &intcapxt_domain_ops, 2138 NULL); 2139 if (!iommu_irqdomain) 2140 irq_domain_free_fwnode(fn); 2141 2142 return iommu_irqdomain; 2143 } 2144 2145 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2146 { 2147 struct irq_domain *domain; 2148 struct irq_alloc_info info; 2149 int irq, ret; 2150 2151 domain = iommu_get_irqdomain(); 2152 if (!domain) 2153 return -ENXIO; 2154 2155 init_irq_alloc_info(&info, NULL); 2156 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2157 info.data = iommu; 2158 2159 irq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 2160 if (irq < 0) { 2161 irq_domain_remove(domain); 2162 return irq; 2163 } 2164 2165 ret = request_threaded_irq(irq, amd_iommu_int_handler, 2166 amd_iommu_int_thread, 0, "AMD-Vi", iommu); 2167 if (ret) { 2168 irq_domain_free_irqs(irq, 1); 2169 irq_domain_remove(domain); 2170 return ret; 2171 } 2172 2173 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2174 return 0; 2175 } 2176 2177 static int iommu_init_irq(struct amd_iommu *iommu) 2178 { 2179 int ret; 2180 2181 if (iommu->int_enabled) 2182 goto enable_faults; 2183 2184 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2185 ret = iommu_setup_intcapxt(iommu); 2186 else if (iommu->dev->msi_cap) 2187 ret = iommu_setup_msi(iommu); 2188 else 2189 ret = -ENODEV; 2190 2191 if (ret) 2192 return ret; 2193 2194 iommu->int_enabled = true; 2195 enable_faults: 2196 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2197 2198 if (iommu->ppr_log != NULL) 2199 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); 2200 2201 iommu_ga_log_enable(iommu); 2202 2203 return 0; 2204 } 2205 2206 /**************************************************************************** 2207 * 2208 * The next functions belong to the third pass of parsing the ACPI 2209 * table. In this last pass the memory mapping requirements are 2210 * gathered (like exclusion and unity mapping ranges). 2211 * 2212 ****************************************************************************/ 2213 2214 static void __init free_unity_maps(void) 2215 { 2216 struct unity_map_entry *entry, *next; 2217 2218 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { 2219 list_del(&entry->list); 2220 kfree(entry); 2221 } 2222 } 2223 2224 /* called for unity map ACPI definition */ 2225 static int __init init_unity_map_range(struct ivmd_header *m) 2226 { 2227 struct unity_map_entry *e = NULL; 2228 char *s; 2229 2230 e = kzalloc(sizeof(*e), GFP_KERNEL); 2231 if (e == NULL) 2232 return -ENOMEM; 2233 2234 switch (m->type) { 2235 default: 2236 kfree(e); 2237 return 0; 2238 case ACPI_IVMD_TYPE: 2239 s = "IVMD_TYPEi\t\t\t"; 2240 e->devid_start = e->devid_end = m->devid; 2241 break; 2242 case ACPI_IVMD_TYPE_ALL: 2243 s = "IVMD_TYPE_ALL\t\t"; 2244 e->devid_start = 0; 2245 e->devid_end = amd_iommu_last_bdf; 2246 break; 2247 case ACPI_IVMD_TYPE_RANGE: 2248 s = "IVMD_TYPE_RANGE\t\t"; 2249 e->devid_start = m->devid; 2250 e->devid_end = m->aux; 2251 break; 2252 } 2253 e->address_start = PAGE_ALIGN(m->range_start); 2254 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2255 e->prot = m->flags >> 1; 2256 2257 /* 2258 * Treat per-device exclusion ranges as r/w unity-mapped regions 2259 * since some buggy BIOSes might lead to the overwritten exclusion 2260 * range (exclusion_start and exclusion_length members). This 2261 * happens when there are multiple exclusion ranges (IVMD entries) 2262 * defined in ACPI table. 2263 */ 2264 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2265 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2266 2267 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" 2268 " range_start: %016llx range_end: %016llx flags: %x\n", s, 2269 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2270 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end), 2271 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2272 e->address_start, e->address_end, m->flags); 2273 2274 list_add_tail(&e->list, &amd_iommu_unity_map); 2275 2276 return 0; 2277 } 2278 2279 /* iterates over all memory definitions we find in the ACPI table */ 2280 static int __init init_memory_definitions(struct acpi_table_header *table) 2281 { 2282 u8 *p = (u8 *)table, *end = (u8 *)table; 2283 struct ivmd_header *m; 2284 2285 end += table->length; 2286 p += IVRS_HEADER_LENGTH; 2287 2288 while (p < end) { 2289 m = (struct ivmd_header *)p; 2290 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2291 init_unity_map_range(m); 2292 2293 p += m->length; 2294 } 2295 2296 return 0; 2297 } 2298 2299 /* 2300 * Init the device table to not allow DMA access for devices 2301 */ 2302 static void init_device_table_dma(void) 2303 { 2304 u32 devid; 2305 2306 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2307 set_dev_entry_bit(devid, DEV_ENTRY_VALID); 2308 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); 2309 } 2310 } 2311 2312 static void __init uninit_device_table_dma(void) 2313 { 2314 u32 devid; 2315 2316 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2317 amd_iommu_dev_table[devid].data[0] = 0ULL; 2318 amd_iommu_dev_table[devid].data[1] = 0ULL; 2319 } 2320 } 2321 2322 static void init_device_table(void) 2323 { 2324 u32 devid; 2325 2326 if (!amd_iommu_irq_remap) 2327 return; 2328 2329 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) 2330 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); 2331 } 2332 2333 static void iommu_init_flags(struct amd_iommu *iommu) 2334 { 2335 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2336 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2337 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2338 2339 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2340 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2341 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2342 2343 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2344 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2345 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2346 2347 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2348 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2349 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2350 2351 /* 2352 * make IOMMU memory accesses cache coherent 2353 */ 2354 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2355 2356 /* Set IOTLB invalidation timeout to 1s */ 2357 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); 2358 } 2359 2360 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2361 { 2362 int i, j; 2363 u32 ioc_feature_control; 2364 struct pci_dev *pdev = iommu->root_pdev; 2365 2366 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2367 if (!is_rd890_iommu(iommu->dev) || !pdev) 2368 return; 2369 2370 /* 2371 * First, we need to ensure that the iommu is enabled. This is 2372 * controlled by a register in the northbridge 2373 */ 2374 2375 /* Select Northbridge indirect register 0x75 and enable writing */ 2376 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2377 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2378 2379 /* Enable the iommu */ 2380 if (!(ioc_feature_control & 0x1)) 2381 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2382 2383 /* Restore the iommu BAR */ 2384 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2385 iommu->stored_addr_lo); 2386 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2387 iommu->stored_addr_hi); 2388 2389 /* Restore the l1 indirect regs for each of the 6 l1s */ 2390 for (i = 0; i < 6; i++) 2391 for (j = 0; j < 0x12; j++) 2392 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2393 2394 /* Restore the l2 indirect regs */ 2395 for (i = 0; i < 0x83; i++) 2396 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2397 2398 /* Lock PCI setup registers */ 2399 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2400 iommu->stored_addr_lo | 1); 2401 } 2402 2403 static void iommu_enable_ga(struct amd_iommu *iommu) 2404 { 2405 #ifdef CONFIG_IRQ_REMAP 2406 switch (amd_iommu_guest_ir) { 2407 case AMD_IOMMU_GUEST_IR_VAPIC: 2408 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2409 fallthrough; 2410 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2411 iommu_feature_enable(iommu, CONTROL_GA_EN); 2412 iommu->irte_ops = &irte_128_ops; 2413 break; 2414 default: 2415 iommu->irte_ops = &irte_32_ops; 2416 break; 2417 } 2418 #endif 2419 } 2420 2421 static void early_enable_iommu(struct amd_iommu *iommu) 2422 { 2423 iommu_disable(iommu); 2424 iommu_init_flags(iommu); 2425 iommu_set_device_table(iommu); 2426 iommu_enable_command_buffer(iommu); 2427 iommu_enable_event_buffer(iommu); 2428 iommu_set_exclusion_range(iommu); 2429 iommu_enable_ga(iommu); 2430 iommu_enable_xt(iommu); 2431 iommu_enable(iommu); 2432 iommu_flush_all_caches(iommu); 2433 } 2434 2435 /* 2436 * This function finally enables all IOMMUs found in the system after 2437 * they have been initialized. 2438 * 2439 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2440 * the old content of device table entries. Not this case or copy failed, 2441 * just continue as normal kernel does. 2442 */ 2443 static void early_enable_iommus(void) 2444 { 2445 struct amd_iommu *iommu; 2446 2447 2448 if (!copy_device_table()) { 2449 /* 2450 * If come here because of failure in copying device table from old 2451 * kernel with all IOMMUs enabled, print error message and try to 2452 * free allocated old_dev_tbl_cpy. 2453 */ 2454 if (amd_iommu_pre_enabled) 2455 pr_err("Failed to copy DEV table from previous kernel.\n"); 2456 if (old_dev_tbl_cpy != NULL) 2457 free_pages((unsigned long)old_dev_tbl_cpy, 2458 get_order(dev_table_size)); 2459 2460 for_each_iommu(iommu) { 2461 clear_translation_pre_enabled(iommu); 2462 early_enable_iommu(iommu); 2463 } 2464 } else { 2465 pr_info("Copied DEV table from previous kernel.\n"); 2466 free_pages((unsigned long)amd_iommu_dev_table, 2467 get_order(dev_table_size)); 2468 amd_iommu_dev_table = old_dev_tbl_cpy; 2469 for_each_iommu(iommu) { 2470 iommu_disable_command_buffer(iommu); 2471 iommu_disable_event_buffer(iommu); 2472 iommu_enable_command_buffer(iommu); 2473 iommu_enable_event_buffer(iommu); 2474 iommu_enable_ga(iommu); 2475 iommu_enable_xt(iommu); 2476 iommu_set_device_table(iommu); 2477 iommu_flush_all_caches(iommu); 2478 } 2479 } 2480 2481 #ifdef CONFIG_IRQ_REMAP 2482 /* 2483 * Note: We have already checked GASup from IVRS table. 2484 * Now, we need to make sure that GAMSup is set. 2485 */ 2486 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 2487 !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) 2488 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2489 2490 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2491 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2492 #endif 2493 } 2494 2495 static void enable_iommus_v2(void) 2496 { 2497 struct amd_iommu *iommu; 2498 2499 for_each_iommu(iommu) { 2500 iommu_enable_ppr_log(iommu); 2501 iommu_enable_gt(iommu); 2502 } 2503 } 2504 2505 static void enable_iommus(void) 2506 { 2507 early_enable_iommus(); 2508 2509 enable_iommus_v2(); 2510 } 2511 2512 static void disable_iommus(void) 2513 { 2514 struct amd_iommu *iommu; 2515 2516 for_each_iommu(iommu) 2517 iommu_disable(iommu); 2518 2519 #ifdef CONFIG_IRQ_REMAP 2520 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2521 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2522 #endif 2523 } 2524 2525 /* 2526 * Suspend/Resume support 2527 * disable suspend until real resume implemented 2528 */ 2529 2530 static void amd_iommu_resume(void) 2531 { 2532 struct amd_iommu *iommu; 2533 2534 for_each_iommu(iommu) 2535 iommu_apply_resume_quirks(iommu); 2536 2537 /* re-load the hardware */ 2538 enable_iommus(); 2539 2540 amd_iommu_enable_interrupts(); 2541 } 2542 2543 static int amd_iommu_suspend(void) 2544 { 2545 /* disable IOMMUs to go out of the way for BIOS */ 2546 disable_iommus(); 2547 2548 return 0; 2549 } 2550 2551 static struct syscore_ops amd_iommu_syscore_ops = { 2552 .suspend = amd_iommu_suspend, 2553 .resume = amd_iommu_resume, 2554 }; 2555 2556 static void __init free_iommu_resources(void) 2557 { 2558 kmemleak_free(irq_lookup_table); 2559 free_pages((unsigned long)irq_lookup_table, 2560 get_order(rlookup_table_size)); 2561 irq_lookup_table = NULL; 2562 2563 kmem_cache_destroy(amd_iommu_irq_cache); 2564 amd_iommu_irq_cache = NULL; 2565 2566 free_pages((unsigned long)amd_iommu_rlookup_table, 2567 get_order(rlookup_table_size)); 2568 amd_iommu_rlookup_table = NULL; 2569 2570 free_pages((unsigned long)amd_iommu_alias_table, 2571 get_order(alias_table_size)); 2572 amd_iommu_alias_table = NULL; 2573 2574 free_pages((unsigned long)amd_iommu_dev_table, 2575 get_order(dev_table_size)); 2576 amd_iommu_dev_table = NULL; 2577 2578 free_iommu_all(); 2579 } 2580 2581 /* SB IOAPIC is always on this device in AMD systems */ 2582 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2583 2584 static bool __init check_ioapic_information(void) 2585 { 2586 const char *fw_bug = FW_BUG; 2587 bool ret, has_sb_ioapic; 2588 int idx; 2589 2590 has_sb_ioapic = false; 2591 ret = false; 2592 2593 /* 2594 * If we have map overrides on the kernel command line the 2595 * messages in this function might not describe firmware bugs 2596 * anymore - so be careful 2597 */ 2598 if (cmdline_maps) 2599 fw_bug = ""; 2600 2601 for (idx = 0; idx < nr_ioapics; idx++) { 2602 int devid, id = mpc_ioapic_id(idx); 2603 2604 devid = get_ioapic_devid(id); 2605 if (devid < 0) { 2606 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2607 fw_bug, id); 2608 ret = false; 2609 } else if (devid == IOAPIC_SB_DEVID) { 2610 has_sb_ioapic = true; 2611 ret = true; 2612 } 2613 } 2614 2615 if (!has_sb_ioapic) { 2616 /* 2617 * We expect the SB IOAPIC to be listed in the IVRS 2618 * table. The system timer is connected to the SB IOAPIC 2619 * and if we don't have it in the list the system will 2620 * panic at boot time. This situation usually happens 2621 * when the BIOS is buggy and provides us the wrong 2622 * device id for the IOAPIC in the system. 2623 */ 2624 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2625 } 2626 2627 if (!ret) 2628 pr_err("Disabling interrupt remapping\n"); 2629 2630 return ret; 2631 } 2632 2633 static void __init free_dma_resources(void) 2634 { 2635 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 2636 get_order(MAX_DOMAIN_ID/8)); 2637 amd_iommu_pd_alloc_bitmap = NULL; 2638 2639 free_unity_maps(); 2640 } 2641 2642 static void __init ivinfo_init(void *ivrs) 2643 { 2644 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 2645 } 2646 2647 /* 2648 * This is the hardware init function for AMD IOMMU in the system. 2649 * This function is called either from amd_iommu_init or from the interrupt 2650 * remapping setup code. 2651 * 2652 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 2653 * four times: 2654 * 2655 * 1 pass) Discover the most comprehensive IVHD type to use. 2656 * 2657 * 2 pass) Find the highest PCI device id the driver has to handle. 2658 * Upon this information the size of the data structures is 2659 * determined that needs to be allocated. 2660 * 2661 * 3 pass) Initialize the data structures just allocated with the 2662 * information in the ACPI table about available AMD IOMMUs 2663 * in the system. It also maps the PCI devices in the 2664 * system to specific IOMMUs 2665 * 2666 * 4 pass) After the basic data structures are allocated and 2667 * initialized we update them with information about memory 2668 * remapping requirements parsed out of the ACPI table in 2669 * this last pass. 2670 * 2671 * After everything is set up the IOMMUs are enabled and the necessary 2672 * hotplug and suspend notifiers are registered. 2673 */ 2674 static int __init early_amd_iommu_init(void) 2675 { 2676 struct acpi_table_header *ivrs_base; 2677 int i, remap_cache_sz, ret; 2678 acpi_status status; 2679 2680 if (!amd_iommu_detected) 2681 return -ENODEV; 2682 2683 status = acpi_get_table("IVRS", 0, &ivrs_base); 2684 if (status == AE_NOT_FOUND) 2685 return -ENODEV; 2686 else if (ACPI_FAILURE(status)) { 2687 const char *err = acpi_format_exception(status); 2688 pr_err("IVRS table error: %s\n", err); 2689 return -EINVAL; 2690 } 2691 2692 /* 2693 * Validate checksum here so we don't need to do it when 2694 * we actually parse the table 2695 */ 2696 ret = check_ivrs_checksum(ivrs_base); 2697 if (ret) 2698 goto out; 2699 2700 ivinfo_init(ivrs_base); 2701 2702 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 2703 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 2704 2705 /* 2706 * First parse ACPI tables to find the largest Bus/Dev/Func 2707 * we need to handle. Upon this information the shared data 2708 * structures for the IOMMUs in the system will be allocated 2709 */ 2710 ret = find_last_devid_acpi(ivrs_base); 2711 if (ret) 2712 goto out; 2713 2714 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 2715 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 2716 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); 2717 2718 /* Device table - directly used by all IOMMUs */ 2719 ret = -ENOMEM; 2720 amd_iommu_dev_table = (void *)__get_free_pages( 2721 GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 2722 get_order(dev_table_size)); 2723 if (amd_iommu_dev_table == NULL) 2724 goto out; 2725 2726 /* 2727 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the 2728 * IOMMU see for that device 2729 */ 2730 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, 2731 get_order(alias_table_size)); 2732 if (amd_iommu_alias_table == NULL) 2733 goto out; 2734 2735 /* IOMMU rlookup table - find the IOMMU for a specific device */ 2736 amd_iommu_rlookup_table = (void *)__get_free_pages( 2737 GFP_KERNEL | __GFP_ZERO, 2738 get_order(rlookup_table_size)); 2739 if (amd_iommu_rlookup_table == NULL) 2740 goto out; 2741 2742 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( 2743 GFP_KERNEL | __GFP_ZERO, 2744 get_order(MAX_DOMAIN_ID/8)); 2745 if (amd_iommu_pd_alloc_bitmap == NULL) 2746 goto out; 2747 2748 /* 2749 * let all alias entries point to itself 2750 */ 2751 for (i = 0; i <= amd_iommu_last_bdf; ++i) 2752 amd_iommu_alias_table[i] = i; 2753 2754 /* 2755 * never allocate domain 0 because its used as the non-allocated and 2756 * error value placeholder 2757 */ 2758 __set_bit(0, amd_iommu_pd_alloc_bitmap); 2759 2760 /* 2761 * now the data structures are allocated and basically initialized 2762 * start the real acpi table scan 2763 */ 2764 ret = init_iommu_all(ivrs_base); 2765 if (ret) 2766 goto out; 2767 2768 /* Disable any previously enabled IOMMUs */ 2769 if (!is_kdump_kernel() || amd_iommu_disabled) 2770 disable_iommus(); 2771 2772 if (amd_iommu_irq_remap) 2773 amd_iommu_irq_remap = check_ioapic_information(); 2774 2775 if (amd_iommu_irq_remap) { 2776 /* 2777 * Interrupt remapping enabled, create kmem_cache for the 2778 * remapping tables. 2779 */ 2780 ret = -ENOMEM; 2781 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 2782 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32); 2783 else 2784 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2); 2785 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", 2786 remap_cache_sz, 2787 DTE_INTTAB_ALIGNMENT, 2788 0, NULL); 2789 if (!amd_iommu_irq_cache) 2790 goto out; 2791 2792 irq_lookup_table = (void *)__get_free_pages( 2793 GFP_KERNEL | __GFP_ZERO, 2794 get_order(rlookup_table_size)); 2795 kmemleak_alloc(irq_lookup_table, rlookup_table_size, 2796 1, GFP_KERNEL); 2797 if (!irq_lookup_table) 2798 goto out; 2799 } 2800 2801 ret = init_memory_definitions(ivrs_base); 2802 if (ret) 2803 goto out; 2804 2805 /* init the device table */ 2806 init_device_table(); 2807 2808 out: 2809 /* Don't leak any ACPI memory */ 2810 acpi_put_table(ivrs_base); 2811 2812 return ret; 2813 } 2814 2815 static int amd_iommu_enable_interrupts(void) 2816 { 2817 struct amd_iommu *iommu; 2818 int ret = 0; 2819 2820 for_each_iommu(iommu) { 2821 ret = iommu_init_irq(iommu); 2822 if (ret) 2823 goto out; 2824 } 2825 2826 out: 2827 return ret; 2828 } 2829 2830 static bool __init detect_ivrs(void) 2831 { 2832 struct acpi_table_header *ivrs_base; 2833 acpi_status status; 2834 int i; 2835 2836 status = acpi_get_table("IVRS", 0, &ivrs_base); 2837 if (status == AE_NOT_FOUND) 2838 return false; 2839 else if (ACPI_FAILURE(status)) { 2840 const char *err = acpi_format_exception(status); 2841 pr_err("IVRS table error: %s\n", err); 2842 return false; 2843 } 2844 2845 acpi_put_table(ivrs_base); 2846 2847 if (amd_iommu_force_enable) 2848 goto out; 2849 2850 /* Don't use IOMMU if there is Stoney Ridge graphics */ 2851 for (i = 0; i < 32; i++) { 2852 u32 pci_id; 2853 2854 pci_id = read_pci_config(0, i, 0, 0); 2855 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 2856 pr_info("Disable IOMMU on Stoney Ridge\n"); 2857 return false; 2858 } 2859 } 2860 2861 out: 2862 /* Make sure ACS will be enabled during PCI probe */ 2863 pci_request_acs(); 2864 2865 return true; 2866 } 2867 2868 /**************************************************************************** 2869 * 2870 * AMD IOMMU Initialization State Machine 2871 * 2872 ****************************************************************************/ 2873 2874 static int __init state_next(void) 2875 { 2876 int ret = 0; 2877 2878 switch (init_state) { 2879 case IOMMU_START_STATE: 2880 if (!detect_ivrs()) { 2881 init_state = IOMMU_NOT_FOUND; 2882 ret = -ENODEV; 2883 } else { 2884 init_state = IOMMU_IVRS_DETECTED; 2885 } 2886 break; 2887 case IOMMU_IVRS_DETECTED: 2888 if (amd_iommu_disabled) { 2889 init_state = IOMMU_CMDLINE_DISABLED; 2890 ret = -EINVAL; 2891 } else { 2892 ret = early_amd_iommu_init(); 2893 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 2894 } 2895 break; 2896 case IOMMU_ACPI_FINISHED: 2897 early_enable_iommus(); 2898 x86_platform.iommu_shutdown = disable_iommus; 2899 init_state = IOMMU_ENABLED; 2900 break; 2901 case IOMMU_ENABLED: 2902 register_syscore_ops(&amd_iommu_syscore_ops); 2903 ret = amd_iommu_init_pci(); 2904 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 2905 enable_iommus_v2(); 2906 break; 2907 case IOMMU_PCI_INIT: 2908 ret = amd_iommu_enable_interrupts(); 2909 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 2910 break; 2911 case IOMMU_INTERRUPTS_EN: 2912 init_state = IOMMU_INITIALIZED; 2913 break; 2914 case IOMMU_INITIALIZED: 2915 /* Nothing to do */ 2916 break; 2917 case IOMMU_NOT_FOUND: 2918 case IOMMU_INIT_ERROR: 2919 case IOMMU_CMDLINE_DISABLED: 2920 /* Error states => do nothing */ 2921 ret = -EINVAL; 2922 break; 2923 default: 2924 /* Unknown state */ 2925 BUG(); 2926 } 2927 2928 if (ret) { 2929 free_dma_resources(); 2930 if (!irq_remapping_enabled) { 2931 disable_iommus(); 2932 free_iommu_resources(); 2933 } else { 2934 struct amd_iommu *iommu; 2935 2936 uninit_device_table_dma(); 2937 for_each_iommu(iommu) 2938 iommu_flush_all_caches(iommu); 2939 } 2940 } 2941 return ret; 2942 } 2943 2944 static int __init iommu_go_to_state(enum iommu_init_state state) 2945 { 2946 int ret = -EINVAL; 2947 2948 while (init_state != state) { 2949 if (init_state == IOMMU_NOT_FOUND || 2950 init_state == IOMMU_INIT_ERROR || 2951 init_state == IOMMU_CMDLINE_DISABLED) 2952 break; 2953 ret = state_next(); 2954 } 2955 2956 return ret; 2957 } 2958 2959 #ifdef CONFIG_IRQ_REMAP 2960 int __init amd_iommu_prepare(void) 2961 { 2962 int ret; 2963 2964 amd_iommu_irq_remap = true; 2965 2966 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 2967 if (ret) { 2968 amd_iommu_irq_remap = false; 2969 return ret; 2970 } 2971 2972 return amd_iommu_irq_remap ? 0 : -ENODEV; 2973 } 2974 2975 int __init amd_iommu_enable(void) 2976 { 2977 int ret; 2978 2979 ret = iommu_go_to_state(IOMMU_ENABLED); 2980 if (ret) 2981 return ret; 2982 2983 irq_remapping_enabled = 1; 2984 return amd_iommu_xt_mode; 2985 } 2986 2987 void amd_iommu_disable(void) 2988 { 2989 amd_iommu_suspend(); 2990 } 2991 2992 int amd_iommu_reenable(int mode) 2993 { 2994 amd_iommu_resume(); 2995 2996 return 0; 2997 } 2998 2999 int __init amd_iommu_enable_faulting(void) 3000 { 3001 /* We enable MSI later when PCI is initialized */ 3002 return 0; 3003 } 3004 #endif 3005 3006 /* 3007 * This is the core init function for AMD IOMMU hardware in the system. 3008 * This function is called from the generic x86 DMA layer initialization 3009 * code. 3010 */ 3011 static int __init amd_iommu_init(void) 3012 { 3013 struct amd_iommu *iommu; 3014 int ret; 3015 3016 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3017 #ifdef CONFIG_GART_IOMMU 3018 if (ret && list_empty(&amd_iommu_list)) { 3019 /* 3020 * We failed to initialize the AMD IOMMU - try fallback 3021 * to GART if possible. 3022 */ 3023 gart_iommu_init(); 3024 } 3025 #endif 3026 3027 for_each_iommu(iommu) 3028 amd_iommu_debugfs_setup(iommu); 3029 3030 return ret; 3031 } 3032 3033 static bool amd_iommu_sme_check(void) 3034 { 3035 if (!sme_active() || (boot_cpu_data.x86 != 0x17)) 3036 return true; 3037 3038 /* For Fam17h, a specific level of support is required */ 3039 if (boot_cpu_data.microcode >= 0x08001205) 3040 return true; 3041 3042 if ((boot_cpu_data.microcode >= 0x08001126) && 3043 (boot_cpu_data.microcode <= 0x080011ff)) 3044 return true; 3045 3046 pr_notice("IOMMU not currently supported when SME is active\n"); 3047 3048 return false; 3049 } 3050 3051 /**************************************************************************** 3052 * 3053 * Early detect code. This code runs at IOMMU detection time in the DMA 3054 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3055 * IOMMUs 3056 * 3057 ****************************************************************************/ 3058 int __init amd_iommu_detect(void) 3059 { 3060 int ret; 3061 3062 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3063 return -ENODEV; 3064 3065 if (!amd_iommu_sme_check()) 3066 return -ENODEV; 3067 3068 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3069 if (ret) 3070 return ret; 3071 3072 amd_iommu_detected = true; 3073 iommu_detected = 1; 3074 x86_init.iommu.iommu_init = amd_iommu_init; 3075 3076 return 1; 3077 } 3078 3079 /**************************************************************************** 3080 * 3081 * Parsing functions for the AMD IOMMU specific kernel command line 3082 * options. 3083 * 3084 ****************************************************************************/ 3085 3086 static int __init parse_amd_iommu_dump(char *str) 3087 { 3088 amd_iommu_dump = true; 3089 3090 return 1; 3091 } 3092 3093 static int __init parse_amd_iommu_intr(char *str) 3094 { 3095 for (; *str; ++str) { 3096 if (strncmp(str, "legacy", 6) == 0) { 3097 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3098 break; 3099 } 3100 if (strncmp(str, "vapic", 5) == 0) { 3101 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3102 break; 3103 } 3104 } 3105 return 1; 3106 } 3107 3108 static int __init parse_amd_iommu_options(char *str) 3109 { 3110 for (; *str; ++str) { 3111 if (strncmp(str, "fullflush", 9) == 0) { 3112 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3113 iommu_set_dma_strict(); 3114 } 3115 if (strncmp(str, "force_enable", 12) == 0) 3116 amd_iommu_force_enable = true; 3117 if (strncmp(str, "off", 3) == 0) 3118 amd_iommu_disabled = true; 3119 if (strncmp(str, "force_isolation", 15) == 0) 3120 amd_iommu_force_isolation = true; 3121 } 3122 3123 return 1; 3124 } 3125 3126 static int __init parse_ivrs_ioapic(char *str) 3127 { 3128 unsigned int bus, dev, fn; 3129 int ret, id, i; 3130 u16 devid; 3131 3132 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3133 3134 if (ret != 4) { 3135 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3136 return 1; 3137 } 3138 3139 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3140 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3141 str); 3142 return 1; 3143 } 3144 3145 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3146 3147 cmdline_maps = true; 3148 i = early_ioapic_map_size++; 3149 early_ioapic_map[i].id = id; 3150 early_ioapic_map[i].devid = devid; 3151 early_ioapic_map[i].cmd_line = true; 3152 3153 return 1; 3154 } 3155 3156 static int __init parse_ivrs_hpet(char *str) 3157 { 3158 unsigned int bus, dev, fn; 3159 int ret, id, i; 3160 u16 devid; 3161 3162 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3163 3164 if (ret != 4) { 3165 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3166 return 1; 3167 } 3168 3169 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3170 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3171 str); 3172 return 1; 3173 } 3174 3175 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3176 3177 cmdline_maps = true; 3178 i = early_hpet_map_size++; 3179 early_hpet_map[i].id = id; 3180 early_hpet_map[i].devid = devid; 3181 early_hpet_map[i].cmd_line = true; 3182 3183 return 1; 3184 } 3185 3186 static int __init parse_ivrs_acpihid(char *str) 3187 { 3188 u32 bus, dev, fn; 3189 char *hid, *uid, *p; 3190 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0}; 3191 int ret, i; 3192 3193 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid); 3194 if (ret != 4) { 3195 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str); 3196 return 1; 3197 } 3198 3199 p = acpiid; 3200 hid = strsep(&p, ":"); 3201 uid = p; 3202 3203 if (!hid || !(*hid) || !uid) { 3204 pr_err("Invalid command line: hid or uid\n"); 3205 return 1; 3206 } 3207 3208 i = early_acpihid_map_size++; 3209 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3210 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3211 early_acpihid_map[i].devid = 3212 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3213 early_acpihid_map[i].cmd_line = true; 3214 3215 return 1; 3216 } 3217 3218 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3219 __setup("amd_iommu=", parse_amd_iommu_options); 3220 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3221 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3222 __setup("ivrs_hpet", parse_ivrs_hpet); 3223 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3224 3225 IOMMU_INIT_FINISH(amd_iommu_detect, 3226 gart_iommu_hole_init, 3227 NULL, 3228 NULL); 3229 3230 bool amd_iommu_v2_supported(void) 3231 { 3232 return amd_iommu_v2_present; 3233 } 3234 EXPORT_SYMBOL(amd_iommu_v2_supported); 3235 3236 struct amd_iommu *get_amd_iommu(unsigned int idx) 3237 { 3238 unsigned int i = 0; 3239 struct amd_iommu *iommu; 3240 3241 for_each_iommu(iommu) 3242 if (i++ == idx) 3243 return iommu; 3244 return NULL; 3245 } 3246 3247 /**************************************************************************** 3248 * 3249 * IOMMU EFR Performance Counter support functionality. This code allows 3250 * access to the IOMMU PC functionality. 3251 * 3252 ****************************************************************************/ 3253 3254 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3255 { 3256 struct amd_iommu *iommu = get_amd_iommu(idx); 3257 3258 if (iommu) 3259 return iommu->max_banks; 3260 3261 return 0; 3262 } 3263 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks); 3264 3265 bool amd_iommu_pc_supported(void) 3266 { 3267 return amd_iommu_pc_present; 3268 } 3269 EXPORT_SYMBOL(amd_iommu_pc_supported); 3270 3271 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3272 { 3273 struct amd_iommu *iommu = get_amd_iommu(idx); 3274 3275 if (iommu) 3276 return iommu->max_counters; 3277 3278 return 0; 3279 } 3280 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters); 3281 3282 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3283 u8 fxn, u64 *value, bool is_write) 3284 { 3285 u32 offset; 3286 u32 max_offset_lim; 3287 3288 /* Make sure the IOMMU PC resource is available */ 3289 if (!amd_iommu_pc_present) 3290 return -ENODEV; 3291 3292 /* Check for valid iommu and pc register indexing */ 3293 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3294 return -ENODEV; 3295 3296 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3297 3298 /* Limit the offset to the hw defined mmio region aperture */ 3299 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3300 (iommu->max_counters << 8) | 0x28); 3301 if ((offset < MMIO_CNTR_REG_OFFSET) || 3302 (offset > max_offset_lim)) 3303 return -EINVAL; 3304 3305 if (is_write) { 3306 u64 val = *value & GENMASK_ULL(47, 0); 3307 3308 writel((u32)val, iommu->mmio_base + offset); 3309 writel((val >> 32), iommu->mmio_base + offset + 4); 3310 } else { 3311 *value = readl(iommu->mmio_base + offset + 4); 3312 *value <<= 32; 3313 *value |= readl(iommu->mmio_base + offset); 3314 *value &= GENMASK_ULL(47, 0); 3315 } 3316 3317 return 0; 3318 } 3319 3320 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3321 { 3322 if (!iommu) 3323 return -EINVAL; 3324 3325 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3326 } 3327 3328 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3329 { 3330 if (!iommu) 3331 return -EINVAL; 3332 3333 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3334 } 3335