1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/slab.h> 16 #include <linux/syscore_ops.h> 17 #include <linux/interrupt.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/amd-iommu.h> 21 #include <linux/export.h> 22 #include <linux/kmemleak.h> 23 #include <linux/mem_encrypt.h> 24 #include <asm/pci-direct.h> 25 #include <asm/iommu.h> 26 #include <asm/apic.h> 27 #include <asm/gart.h> 28 #include <asm/x86_init.h> 29 #include <asm/iommu_table.h> 30 #include <asm/io_apic.h> 31 #include <asm/irq_remapping.h> 32 #include <asm/set_memory.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 39 /* 40 * definitions for the ACPI scanning code 41 */ 42 #define IVRS_HEADER_LENGTH 48 43 44 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 45 #define ACPI_IVMD_TYPE_ALL 0x20 46 #define ACPI_IVMD_TYPE 0x21 47 #define ACPI_IVMD_TYPE_RANGE 0x22 48 49 #define IVHD_DEV_ALL 0x01 50 #define IVHD_DEV_SELECT 0x02 51 #define IVHD_DEV_SELECT_RANGE_START 0x03 52 #define IVHD_DEV_RANGE_END 0x04 53 #define IVHD_DEV_ALIAS 0x42 54 #define IVHD_DEV_ALIAS_RANGE 0x43 55 #define IVHD_DEV_EXT_SELECT 0x46 56 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 57 #define IVHD_DEV_SPECIAL 0x48 58 #define IVHD_DEV_ACPI_HID 0xf0 59 60 #define UID_NOT_PRESENT 0 61 #define UID_IS_INTEGER 1 62 #define UID_IS_CHARACTER 2 63 64 #define IVHD_SPECIAL_IOAPIC 1 65 #define IVHD_SPECIAL_HPET 2 66 67 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 68 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 69 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 70 #define IVHD_FLAG_ISOC_EN_MASK 0x08 71 72 #define IVMD_FLAG_EXCL_RANGE 0x08 73 #define IVMD_FLAG_IW 0x04 74 #define IVMD_FLAG_IR 0x02 75 #define IVMD_FLAG_UNITY_MAP 0x01 76 77 #define ACPI_DEVFLAG_INITPASS 0x01 78 #define ACPI_DEVFLAG_EXTINT 0x02 79 #define ACPI_DEVFLAG_NMI 0x04 80 #define ACPI_DEVFLAG_SYSMGT1 0x10 81 #define ACPI_DEVFLAG_SYSMGT2 0x20 82 #define ACPI_DEVFLAG_LINT0 0x40 83 #define ACPI_DEVFLAG_LINT1 0x80 84 #define ACPI_DEVFLAG_ATSDIS 0x10000000 85 86 #define LOOP_TIMEOUT 100000 87 /* 88 * ACPI table definitions 89 * 90 * These data structures are laid over the table to parse the important values 91 * out of it. 92 */ 93 94 extern const struct iommu_ops amd_iommu_ops; 95 96 /* 97 * structure describing one IOMMU in the ACPI table. Typically followed by one 98 * or more ivhd_entrys. 99 */ 100 struct ivhd_header { 101 u8 type; 102 u8 flags; 103 u16 length; 104 u16 devid; 105 u16 cap_ptr; 106 u64 mmio_phys; 107 u16 pci_seg; 108 u16 info; 109 u32 efr_attr; 110 111 /* Following only valid on IVHD type 11h and 40h */ 112 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 113 u64 res; 114 } __attribute__((packed)); 115 116 /* 117 * A device entry describing which devices a specific IOMMU translates and 118 * which requestor ids they use. 119 */ 120 struct ivhd_entry { 121 u8 type; 122 u16 devid; 123 u8 flags; 124 u32 ext; 125 u32 hidh; 126 u64 cid; 127 u8 uidf; 128 u8 uidl; 129 u8 uid; 130 } __attribute__((packed)); 131 132 /* 133 * An AMD IOMMU memory definition structure. It defines things like exclusion 134 * ranges for devices and regions that should be unity mapped. 135 */ 136 struct ivmd_header { 137 u8 type; 138 u8 flags; 139 u16 length; 140 u16 devid; 141 u16 aux; 142 u64 resv; 143 u64 range_start; 144 u64 range_length; 145 } __attribute__((packed)); 146 147 bool amd_iommu_dump; 148 bool amd_iommu_irq_remap __read_mostly; 149 150 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 151 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 152 153 static bool amd_iommu_detected; 154 static bool __initdata amd_iommu_disabled; 155 static int amd_iommu_target_ivhd_type; 156 157 u16 amd_iommu_last_bdf; /* largest PCI device id we have 158 to handle */ 159 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings 160 we find in ACPI */ 161 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ 162 163 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 164 system */ 165 166 /* Array to assign indices to IOMMUs*/ 167 struct amd_iommu *amd_iommus[MAX_IOMMUS]; 168 169 /* Number of IOMMUs present in the system */ 170 static int amd_iommus_present; 171 172 /* IOMMUs have a non-present cache? */ 173 bool amd_iommu_np_cache __read_mostly; 174 bool amd_iommu_iotlb_sup __read_mostly = true; 175 176 u32 amd_iommu_max_pasid __read_mostly = ~0; 177 178 bool amd_iommu_v2_present __read_mostly; 179 static bool amd_iommu_pc_present __read_mostly; 180 181 bool amd_iommu_force_isolation __read_mostly; 182 183 /* 184 * Pointer to the device table which is shared by all AMD IOMMUs 185 * it is indexed by the PCI device id or the HT unit id and contains 186 * information about the domain the device belongs to as well as the 187 * page table root pointer. 188 */ 189 struct dev_table_entry *amd_iommu_dev_table; 190 /* 191 * Pointer to a device table which the content of old device table 192 * will be copied to. It's only be used in kdump kernel. 193 */ 194 static struct dev_table_entry *old_dev_tbl_cpy; 195 196 /* 197 * The alias table is a driver specific data structure which contains the 198 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 199 * More than one device can share the same requestor id. 200 */ 201 u16 *amd_iommu_alias_table; 202 203 /* 204 * The rlookup table is used to find the IOMMU which is responsible 205 * for a specific device. It is also indexed by the PCI device id. 206 */ 207 struct amd_iommu **amd_iommu_rlookup_table; 208 EXPORT_SYMBOL(amd_iommu_rlookup_table); 209 210 /* 211 * This table is used to find the irq remapping table for a given device id 212 * quickly. 213 */ 214 struct irq_remap_table **irq_lookup_table; 215 216 /* 217 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap 218 * to know which ones are already in use. 219 */ 220 unsigned long *amd_iommu_pd_alloc_bitmap; 221 222 static u32 dev_table_size; /* size of the device table */ 223 static u32 alias_table_size; /* size of the alias table */ 224 static u32 rlookup_table_size; /* size if the rlookup table */ 225 226 enum iommu_init_state { 227 IOMMU_START_STATE, 228 IOMMU_IVRS_DETECTED, 229 IOMMU_ACPI_FINISHED, 230 IOMMU_ENABLED, 231 IOMMU_PCI_INIT, 232 IOMMU_INTERRUPTS_EN, 233 IOMMU_DMA_OPS, 234 IOMMU_INITIALIZED, 235 IOMMU_NOT_FOUND, 236 IOMMU_INIT_ERROR, 237 IOMMU_CMDLINE_DISABLED, 238 }; 239 240 /* Early ioapic and hpet maps from kernel command line */ 241 #define EARLY_MAP_SIZE 4 242 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 243 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 244 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 245 246 static int __initdata early_ioapic_map_size; 247 static int __initdata early_hpet_map_size; 248 static int __initdata early_acpihid_map_size; 249 250 static bool __initdata cmdline_maps; 251 252 static enum iommu_init_state init_state = IOMMU_START_STATE; 253 254 static int amd_iommu_enable_interrupts(void); 255 static int __init iommu_go_to_state(enum iommu_init_state state); 256 static void init_device_table_dma(void); 257 258 static bool amd_iommu_pre_enabled = true; 259 260 bool translation_pre_enabled(struct amd_iommu *iommu) 261 { 262 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 263 } 264 EXPORT_SYMBOL(translation_pre_enabled); 265 266 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 267 { 268 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 269 } 270 271 static void init_translation_status(struct amd_iommu *iommu) 272 { 273 u64 ctrl; 274 275 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 276 if (ctrl & (1<<CONTROL_IOMMU_EN)) 277 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 278 } 279 280 static inline void update_last_devid(u16 devid) 281 { 282 if (devid > amd_iommu_last_bdf) 283 amd_iommu_last_bdf = devid; 284 } 285 286 static inline unsigned long tbl_size(int entry_size) 287 { 288 unsigned shift = PAGE_SHIFT + 289 get_order(((int)amd_iommu_last_bdf + 1) * entry_size); 290 291 return 1UL << shift; 292 } 293 294 int amd_iommu_get_num_iommus(void) 295 { 296 return amd_iommus_present; 297 } 298 299 /* Access to l1 and l2 indexed register spaces */ 300 301 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 302 { 303 u32 val; 304 305 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 306 pci_read_config_dword(iommu->dev, 0xfc, &val); 307 return val; 308 } 309 310 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 311 { 312 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 313 pci_write_config_dword(iommu->dev, 0xfc, val); 314 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 315 } 316 317 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 318 { 319 u32 val; 320 321 pci_write_config_dword(iommu->dev, 0xf0, address); 322 pci_read_config_dword(iommu->dev, 0xf4, &val); 323 return val; 324 } 325 326 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 327 { 328 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 329 pci_write_config_dword(iommu->dev, 0xf4, val); 330 } 331 332 /**************************************************************************** 333 * 334 * AMD IOMMU MMIO register space handling functions 335 * 336 * These functions are used to program the IOMMU device registers in 337 * MMIO space required for that driver. 338 * 339 ****************************************************************************/ 340 341 /* 342 * This function set the exclusion range in the IOMMU. DMA accesses to the 343 * exclusion range are passed through untranslated 344 */ 345 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 346 { 347 u64 start = iommu->exclusion_start & PAGE_MASK; 348 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 349 u64 entry; 350 351 if (!iommu->exclusion_start) 352 return; 353 354 entry = start | MMIO_EXCL_ENABLE_MASK; 355 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 356 &entry, sizeof(entry)); 357 358 entry = limit; 359 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 360 &entry, sizeof(entry)); 361 } 362 363 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 364 { 365 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 366 u64 entry = start & PM_ADDR_MASK; 367 368 if (!iommu_feature(iommu, FEATURE_SNP)) 369 return; 370 371 /* Note: 372 * Re-purpose Exclusion base/limit registers for Completion wait 373 * write-back base/limit. 374 */ 375 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 376 &entry, sizeof(entry)); 377 378 /* Note: 379 * Default to 4 Kbytes, which can be specified by setting base 380 * address equal to the limit address. 381 */ 382 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 383 &entry, sizeof(entry)); 384 } 385 386 /* Programs the physical address of the device table into the IOMMU hardware */ 387 static void iommu_set_device_table(struct amd_iommu *iommu) 388 { 389 u64 entry; 390 391 BUG_ON(iommu->mmio_base == NULL); 392 393 entry = iommu_virt_to_phys(amd_iommu_dev_table); 394 entry |= (dev_table_size >> 12) - 1; 395 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 396 &entry, sizeof(entry)); 397 } 398 399 /* Generic functions to enable/disable certain features of the IOMMU. */ 400 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 401 { 402 u64 ctrl; 403 404 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 405 ctrl |= (1ULL << bit); 406 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 407 } 408 409 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 410 { 411 u64 ctrl; 412 413 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 414 ctrl &= ~(1ULL << bit); 415 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 416 } 417 418 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) 419 { 420 u64 ctrl; 421 422 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 423 ctrl &= ~CTRL_INV_TO_MASK; 424 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; 425 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 426 } 427 428 /* Function to enable the hardware */ 429 static void iommu_enable(struct amd_iommu *iommu) 430 { 431 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 432 } 433 434 static void iommu_disable(struct amd_iommu *iommu) 435 { 436 if (!iommu->mmio_base) 437 return; 438 439 /* Disable command buffer */ 440 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 441 442 /* Disable event logging and event interrupts */ 443 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 444 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 445 446 /* Disable IOMMU GA_LOG */ 447 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 448 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 449 450 /* Disable IOMMU hardware itself */ 451 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 452 } 453 454 /* 455 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 456 * the system has one. 457 */ 458 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 459 { 460 if (!request_mem_region(address, end, "amd_iommu")) { 461 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 462 address, end); 463 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 464 return NULL; 465 } 466 467 return (u8 __iomem *)ioremap(address, end); 468 } 469 470 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 471 { 472 if (iommu->mmio_base) 473 iounmap(iommu->mmio_base); 474 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 475 } 476 477 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 478 { 479 u32 size = 0; 480 481 switch (h->type) { 482 case 0x10: 483 size = 24; 484 break; 485 case 0x11: 486 case 0x40: 487 size = 40; 488 break; 489 } 490 return size; 491 } 492 493 /**************************************************************************** 494 * 495 * The functions below belong to the first pass of AMD IOMMU ACPI table 496 * parsing. In this pass we try to find out the highest device id this 497 * code has to handle. Upon this information the size of the shared data 498 * structures is determined later. 499 * 500 ****************************************************************************/ 501 502 /* 503 * This function calculates the length of a given IVHD entry 504 */ 505 static inline int ivhd_entry_length(u8 *ivhd) 506 { 507 u32 type = ((struct ivhd_entry *)ivhd)->type; 508 509 if (type < 0x80) { 510 return 0x04 << (*ivhd >> 6); 511 } else if (type == IVHD_DEV_ACPI_HID) { 512 /* For ACPI_HID, offset 21 is uid len */ 513 return *((u8 *)ivhd + 21) + 22; 514 } 515 return 0; 516 } 517 518 /* 519 * After reading the highest device id from the IOMMU PCI capability header 520 * this function looks if there is a higher device id defined in the ACPI table 521 */ 522 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 523 { 524 u8 *p = (void *)h, *end = (void *)h; 525 struct ivhd_entry *dev; 526 527 u32 ivhd_size = get_ivhd_header_size(h); 528 529 if (!ivhd_size) { 530 pr_err("Unsupported IVHD type %#x\n", h->type); 531 return -EINVAL; 532 } 533 534 p += ivhd_size; 535 end += h->length; 536 537 while (p < end) { 538 dev = (struct ivhd_entry *)p; 539 switch (dev->type) { 540 case IVHD_DEV_ALL: 541 /* Use maximum BDF value for DEV_ALL */ 542 update_last_devid(0xffff); 543 break; 544 case IVHD_DEV_SELECT: 545 case IVHD_DEV_RANGE_END: 546 case IVHD_DEV_ALIAS: 547 case IVHD_DEV_EXT_SELECT: 548 /* all the above subfield types refer to device ids */ 549 update_last_devid(dev->devid); 550 break; 551 default: 552 break; 553 } 554 p += ivhd_entry_length(p); 555 } 556 557 WARN_ON(p != end); 558 559 return 0; 560 } 561 562 static int __init check_ivrs_checksum(struct acpi_table_header *table) 563 { 564 int i; 565 u8 checksum = 0, *p = (u8 *)table; 566 567 for (i = 0; i < table->length; ++i) 568 checksum += p[i]; 569 if (checksum != 0) { 570 /* ACPI table corrupt */ 571 pr_err(FW_BUG "IVRS invalid checksum\n"); 572 return -ENODEV; 573 } 574 575 return 0; 576 } 577 578 /* 579 * Iterate over all IVHD entries in the ACPI table and find the highest device 580 * id which we need to handle. This is the first of three functions which parse 581 * the ACPI table. So we check the checksum here. 582 */ 583 static int __init find_last_devid_acpi(struct acpi_table_header *table) 584 { 585 u8 *p = (u8 *)table, *end = (u8 *)table; 586 struct ivhd_header *h; 587 588 p += IVRS_HEADER_LENGTH; 589 590 end += table->length; 591 while (p < end) { 592 h = (struct ivhd_header *)p; 593 if (h->type == amd_iommu_target_ivhd_type) { 594 int ret = find_last_devid_from_ivhd(h); 595 596 if (ret) 597 return ret; 598 } 599 p += h->length; 600 } 601 WARN_ON(p != end); 602 603 return 0; 604 } 605 606 /**************************************************************************** 607 * 608 * The following functions belong to the code path which parses the ACPI table 609 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 610 * data structures, initialize the device/alias/rlookup table and also 611 * basically initialize the hardware. 612 * 613 ****************************************************************************/ 614 615 /* 616 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 617 * write commands to that buffer later and the IOMMU will execute them 618 * asynchronously 619 */ 620 static int __init alloc_command_buffer(struct amd_iommu *iommu) 621 { 622 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 623 get_order(CMD_BUFFER_SIZE)); 624 625 return iommu->cmd_buf ? 0 : -ENOMEM; 626 } 627 628 /* 629 * This function resets the command buffer if the IOMMU stopped fetching 630 * commands from it. 631 */ 632 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 633 { 634 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 635 636 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 637 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 638 iommu->cmd_buf_head = 0; 639 iommu->cmd_buf_tail = 0; 640 641 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 642 } 643 644 /* 645 * This function writes the command buffer address to the hardware and 646 * enables it. 647 */ 648 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 649 { 650 u64 entry; 651 652 BUG_ON(iommu->cmd_buf == NULL); 653 654 entry = iommu_virt_to_phys(iommu->cmd_buf); 655 entry |= MMIO_CMD_SIZE_512; 656 657 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 658 &entry, sizeof(entry)); 659 660 amd_iommu_reset_cmd_buffer(iommu); 661 } 662 663 /* 664 * This function disables the command buffer 665 */ 666 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 667 { 668 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 669 } 670 671 static void __init free_command_buffer(struct amd_iommu *iommu) 672 { 673 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); 674 } 675 676 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, 677 gfp_t gfp, size_t size) 678 { 679 int order = get_order(size); 680 void *buf = (void *)__get_free_pages(gfp, order); 681 682 if (buf && 683 iommu_feature(iommu, FEATURE_SNP) && 684 set_memory_4k((unsigned long)buf, (1 << order))) { 685 free_pages((unsigned long)buf, order); 686 buf = NULL; 687 } 688 689 return buf; 690 } 691 692 /* allocates the memory where the IOMMU will log its events to */ 693 static int __init alloc_event_buffer(struct amd_iommu *iommu) 694 { 695 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 696 EVT_BUFFER_SIZE); 697 698 return iommu->evt_buf ? 0 : -ENOMEM; 699 } 700 701 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 702 { 703 u64 entry; 704 705 BUG_ON(iommu->evt_buf == NULL); 706 707 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 708 709 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 710 &entry, sizeof(entry)); 711 712 /* set head and tail to zero manually */ 713 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 714 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 715 716 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 717 } 718 719 /* 720 * This function disables the event log buffer 721 */ 722 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 723 { 724 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 725 } 726 727 static void __init free_event_buffer(struct amd_iommu *iommu) 728 { 729 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); 730 } 731 732 /* allocates the memory where the IOMMU will log its events to */ 733 static int __init alloc_ppr_log(struct amd_iommu *iommu) 734 { 735 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 736 PPR_LOG_SIZE); 737 738 return iommu->ppr_log ? 0 : -ENOMEM; 739 } 740 741 static void iommu_enable_ppr_log(struct amd_iommu *iommu) 742 { 743 u64 entry; 744 745 if (iommu->ppr_log == NULL) 746 return; 747 748 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; 749 750 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, 751 &entry, sizeof(entry)); 752 753 /* set head and tail to zero manually */ 754 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 755 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 756 757 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); 758 iommu_feature_enable(iommu, CONTROL_PPR_EN); 759 } 760 761 static void __init free_ppr_log(struct amd_iommu *iommu) 762 { 763 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); 764 } 765 766 static void free_ga_log(struct amd_iommu *iommu) 767 { 768 #ifdef CONFIG_IRQ_REMAP 769 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); 770 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); 771 #endif 772 } 773 774 static int iommu_ga_log_enable(struct amd_iommu *iommu) 775 { 776 #ifdef CONFIG_IRQ_REMAP 777 u32 status, i; 778 779 if (!iommu->ga_log) 780 return -EINVAL; 781 782 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 783 784 /* Check if already running */ 785 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 786 return 0; 787 788 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 789 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 790 791 for (i = 0; i < LOOP_TIMEOUT; ++i) { 792 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 793 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 794 break; 795 } 796 797 if (i >= LOOP_TIMEOUT) 798 return -EINVAL; 799 #endif /* CONFIG_IRQ_REMAP */ 800 return 0; 801 } 802 803 #ifdef CONFIG_IRQ_REMAP 804 static int iommu_init_ga_log(struct amd_iommu *iommu) 805 { 806 u64 entry; 807 808 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 809 return 0; 810 811 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 812 get_order(GA_LOG_SIZE)); 813 if (!iommu->ga_log) 814 goto err_out; 815 816 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 817 get_order(8)); 818 if (!iommu->ga_log_tail) 819 goto err_out; 820 821 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 822 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 823 &entry, sizeof(entry)); 824 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 825 (BIT_ULL(52)-1)) & ~7ULL; 826 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 827 &entry, sizeof(entry)); 828 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 829 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 830 831 return 0; 832 err_out: 833 free_ga_log(iommu); 834 return -EINVAL; 835 } 836 #endif /* CONFIG_IRQ_REMAP */ 837 838 static int iommu_init_ga(struct amd_iommu *iommu) 839 { 840 int ret = 0; 841 842 #ifdef CONFIG_IRQ_REMAP 843 /* Note: We have already checked GASup from IVRS table. 844 * Now, we need to make sure that GAMSup is set. 845 */ 846 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 847 !iommu_feature(iommu, FEATURE_GAM_VAPIC)) 848 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 849 850 ret = iommu_init_ga_log(iommu); 851 #endif /* CONFIG_IRQ_REMAP */ 852 853 return ret; 854 } 855 856 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 857 { 858 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); 859 860 return iommu->cmd_sem ? 0 : -ENOMEM; 861 } 862 863 static void __init free_cwwb_sem(struct amd_iommu *iommu) 864 { 865 if (iommu->cmd_sem) 866 free_page((unsigned long)iommu->cmd_sem); 867 } 868 869 static void iommu_enable_xt(struct amd_iommu *iommu) 870 { 871 #ifdef CONFIG_IRQ_REMAP 872 /* 873 * XT mode (32-bit APIC destination ID) requires 874 * GA mode (128-bit IRTE support) as a prerequisite. 875 */ 876 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 877 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 878 iommu_feature_enable(iommu, CONTROL_XT_EN); 879 #endif /* CONFIG_IRQ_REMAP */ 880 } 881 882 static void iommu_enable_gt(struct amd_iommu *iommu) 883 { 884 if (!iommu_feature(iommu, FEATURE_GT)) 885 return; 886 887 iommu_feature_enable(iommu, CONTROL_GT_EN); 888 } 889 890 /* sets a specific bit in the device table entry. */ 891 static void set_dev_entry_bit(u16 devid, u8 bit) 892 { 893 int i = (bit >> 6) & 0x03; 894 int _bit = bit & 0x3f; 895 896 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); 897 } 898 899 static int get_dev_entry_bit(u16 devid, u8 bit) 900 { 901 int i = (bit >> 6) & 0x03; 902 int _bit = bit & 0x3f; 903 904 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; 905 } 906 907 908 static bool copy_device_table(void) 909 { 910 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0; 911 struct dev_table_entry *old_devtb = NULL; 912 u32 lo, hi, devid, old_devtb_size; 913 phys_addr_t old_devtb_phys; 914 struct amd_iommu *iommu; 915 u16 dom_id, dte_v, irq_v; 916 gfp_t gfp_flag; 917 u64 tmp; 918 919 if (!amd_iommu_pre_enabled) 920 return false; 921 922 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 923 for_each_iommu(iommu) { 924 /* All IOMMUs should use the same device table with the same size */ 925 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 926 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 927 entry = (((u64) hi) << 32) + lo; 928 if (last_entry && last_entry != entry) { 929 pr_err("IOMMU:%d should use the same dev table as others!\n", 930 iommu->index); 931 return false; 932 } 933 last_entry = entry; 934 935 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 936 if (old_devtb_size != dev_table_size) { 937 pr_err("The device table size of IOMMU:%d is not expected!\n", 938 iommu->index); 939 return false; 940 } 941 } 942 943 /* 944 * When SME is enabled in the first kernel, the entry includes the 945 * memory encryption mask(sme_me_mask), we must remove the memory 946 * encryption mask to obtain the true physical address in kdump kernel. 947 */ 948 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 949 950 if (old_devtb_phys >= 0x100000000ULL) { 951 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 952 return false; 953 } 954 old_devtb = (sme_active() && is_kdump_kernel()) 955 ? (__force void *)ioremap_encrypted(old_devtb_phys, 956 dev_table_size) 957 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB); 958 959 if (!old_devtb) 960 return false; 961 962 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32; 963 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag, 964 get_order(dev_table_size)); 965 if (old_dev_tbl_cpy == NULL) { 966 pr_err("Failed to allocate memory for copying old device table!\n"); 967 return false; 968 } 969 970 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 971 old_dev_tbl_cpy[devid] = old_devtb[devid]; 972 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 973 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 974 975 if (dte_v && dom_id) { 976 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 977 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 978 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap); 979 /* If gcr3 table existed, mask it out */ 980 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 981 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 982 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 983 old_dev_tbl_cpy[devid].data[1] &= ~tmp; 984 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; 985 tmp |= DTE_FLAG_GV; 986 old_dev_tbl_cpy[devid].data[0] &= ~tmp; 987 } 988 } 989 990 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 991 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 992 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; 993 if (irq_v && (int_ctl || int_tab_len)) { 994 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 995 (int_tab_len != DTE_INTTABLEN)) { 996 pr_err("Wrong old irq remapping flag: %#x\n", devid); 997 return false; 998 } 999 1000 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1001 } 1002 } 1003 memunmap(old_devtb); 1004 1005 return true; 1006 } 1007 1008 void amd_iommu_apply_erratum_63(u16 devid) 1009 { 1010 int sysmgt; 1011 1012 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | 1013 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); 1014 1015 if (sysmgt == 0x01) 1016 set_dev_entry_bit(devid, DEV_ENTRY_IW); 1017 } 1018 1019 /* Writes the specific IOMMU for a device into the rlookup table */ 1020 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) 1021 { 1022 amd_iommu_rlookup_table[devid] = iommu; 1023 } 1024 1025 /* 1026 * This function takes the device specific flags read from the ACPI 1027 * table and sets up the device table entry with that information 1028 */ 1029 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1030 u16 devid, u32 flags, u32 ext_flags) 1031 { 1032 if (flags & ACPI_DEVFLAG_INITPASS) 1033 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); 1034 if (flags & ACPI_DEVFLAG_EXTINT) 1035 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); 1036 if (flags & ACPI_DEVFLAG_NMI) 1037 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); 1038 if (flags & ACPI_DEVFLAG_SYSMGT1) 1039 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); 1040 if (flags & ACPI_DEVFLAG_SYSMGT2) 1041 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); 1042 if (flags & ACPI_DEVFLAG_LINT0) 1043 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); 1044 if (flags & ACPI_DEVFLAG_LINT1) 1045 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); 1046 1047 amd_iommu_apply_erratum_63(devid); 1048 1049 set_iommu_for_device(iommu, devid); 1050 } 1051 1052 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line) 1053 { 1054 struct devid_map *entry; 1055 struct list_head *list; 1056 1057 if (type == IVHD_SPECIAL_IOAPIC) 1058 list = &ioapic_map; 1059 else if (type == IVHD_SPECIAL_HPET) 1060 list = &hpet_map; 1061 else 1062 return -EINVAL; 1063 1064 list_for_each_entry(entry, list, list) { 1065 if (!(entry->id == id && entry->cmd_line)) 1066 continue; 1067 1068 pr_info("Command-line override present for %s id %d - ignoring\n", 1069 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1070 1071 *devid = entry->devid; 1072 1073 return 0; 1074 } 1075 1076 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1077 if (!entry) 1078 return -ENOMEM; 1079 1080 entry->id = id; 1081 entry->devid = *devid; 1082 entry->cmd_line = cmd_line; 1083 1084 list_add_tail(&entry->list, list); 1085 1086 return 0; 1087 } 1088 1089 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid, 1090 bool cmd_line) 1091 { 1092 struct acpihid_map_entry *entry; 1093 struct list_head *list = &acpihid_map; 1094 1095 list_for_each_entry(entry, list, list) { 1096 if (strcmp(entry->hid, hid) || 1097 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1098 !entry->cmd_line) 1099 continue; 1100 1101 pr_info("Command-line override for hid:%s uid:%s\n", 1102 hid, uid); 1103 *devid = entry->devid; 1104 return 0; 1105 } 1106 1107 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1108 if (!entry) 1109 return -ENOMEM; 1110 1111 memcpy(entry->uid, uid, strlen(uid)); 1112 memcpy(entry->hid, hid, strlen(hid)); 1113 entry->devid = *devid; 1114 entry->cmd_line = cmd_line; 1115 entry->root_devid = (entry->devid & (~0x7)); 1116 1117 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n", 1118 entry->cmd_line ? "cmd" : "ivrs", 1119 entry->hid, entry->uid, entry->root_devid); 1120 1121 list_add_tail(&entry->list, list); 1122 return 0; 1123 } 1124 1125 static int __init add_early_maps(void) 1126 { 1127 int i, ret; 1128 1129 for (i = 0; i < early_ioapic_map_size; ++i) { 1130 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1131 early_ioapic_map[i].id, 1132 &early_ioapic_map[i].devid, 1133 early_ioapic_map[i].cmd_line); 1134 if (ret) 1135 return ret; 1136 } 1137 1138 for (i = 0; i < early_hpet_map_size; ++i) { 1139 ret = add_special_device(IVHD_SPECIAL_HPET, 1140 early_hpet_map[i].id, 1141 &early_hpet_map[i].devid, 1142 early_hpet_map[i].cmd_line); 1143 if (ret) 1144 return ret; 1145 } 1146 1147 for (i = 0; i < early_acpihid_map_size; ++i) { 1148 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1149 early_acpihid_map[i].uid, 1150 &early_acpihid_map[i].devid, 1151 early_acpihid_map[i].cmd_line); 1152 if (ret) 1153 return ret; 1154 } 1155 1156 return 0; 1157 } 1158 1159 /* 1160 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1161 * initializes the hardware and our data structures with it. 1162 */ 1163 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1164 struct ivhd_header *h) 1165 { 1166 u8 *p = (u8 *)h; 1167 u8 *end = p, flags = 0; 1168 u16 devid = 0, devid_start = 0, devid_to = 0; 1169 u32 dev_i, ext_flags = 0; 1170 bool alias = false; 1171 struct ivhd_entry *e; 1172 u32 ivhd_size; 1173 int ret; 1174 1175 1176 ret = add_early_maps(); 1177 if (ret) 1178 return ret; 1179 1180 amd_iommu_apply_ivrs_quirks(); 1181 1182 /* 1183 * First save the recommended feature enable bits from ACPI 1184 */ 1185 iommu->acpi_flags = h->flags; 1186 1187 /* 1188 * Done. Now parse the device entries 1189 */ 1190 ivhd_size = get_ivhd_header_size(h); 1191 if (!ivhd_size) { 1192 pr_err("Unsupported IVHD type %#x\n", h->type); 1193 return -EINVAL; 1194 } 1195 1196 p += ivhd_size; 1197 1198 end += h->length; 1199 1200 1201 while (p < end) { 1202 e = (struct ivhd_entry *)p; 1203 switch (e->type) { 1204 case IVHD_DEV_ALL: 1205 1206 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); 1207 1208 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i) 1209 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); 1210 break; 1211 case IVHD_DEV_SELECT: 1212 1213 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " 1214 "flags: %02x\n", 1215 PCI_BUS_NUM(e->devid), 1216 PCI_SLOT(e->devid), 1217 PCI_FUNC(e->devid), 1218 e->flags); 1219 1220 devid = e->devid; 1221 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1222 break; 1223 case IVHD_DEV_SELECT_RANGE_START: 1224 1225 DUMP_printk(" DEV_SELECT_RANGE_START\t " 1226 "devid: %02x:%02x.%x flags: %02x\n", 1227 PCI_BUS_NUM(e->devid), 1228 PCI_SLOT(e->devid), 1229 PCI_FUNC(e->devid), 1230 e->flags); 1231 1232 devid_start = e->devid; 1233 flags = e->flags; 1234 ext_flags = 0; 1235 alias = false; 1236 break; 1237 case IVHD_DEV_ALIAS: 1238 1239 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " 1240 "flags: %02x devid_to: %02x:%02x.%x\n", 1241 PCI_BUS_NUM(e->devid), 1242 PCI_SLOT(e->devid), 1243 PCI_FUNC(e->devid), 1244 e->flags, 1245 PCI_BUS_NUM(e->ext >> 8), 1246 PCI_SLOT(e->ext >> 8), 1247 PCI_FUNC(e->ext >> 8)); 1248 1249 devid = e->devid; 1250 devid_to = e->ext >> 8; 1251 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1252 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1253 amd_iommu_alias_table[devid] = devid_to; 1254 break; 1255 case IVHD_DEV_ALIAS_RANGE: 1256 1257 DUMP_printk(" DEV_ALIAS_RANGE\t\t " 1258 "devid: %02x:%02x.%x flags: %02x " 1259 "devid_to: %02x:%02x.%x\n", 1260 PCI_BUS_NUM(e->devid), 1261 PCI_SLOT(e->devid), 1262 PCI_FUNC(e->devid), 1263 e->flags, 1264 PCI_BUS_NUM(e->ext >> 8), 1265 PCI_SLOT(e->ext >> 8), 1266 PCI_FUNC(e->ext >> 8)); 1267 1268 devid_start = e->devid; 1269 flags = e->flags; 1270 devid_to = e->ext >> 8; 1271 ext_flags = 0; 1272 alias = true; 1273 break; 1274 case IVHD_DEV_EXT_SELECT: 1275 1276 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " 1277 "flags: %02x ext: %08x\n", 1278 PCI_BUS_NUM(e->devid), 1279 PCI_SLOT(e->devid), 1280 PCI_FUNC(e->devid), 1281 e->flags, e->ext); 1282 1283 devid = e->devid; 1284 set_dev_entry_from_acpi(iommu, devid, e->flags, 1285 e->ext); 1286 break; 1287 case IVHD_DEV_EXT_SELECT_RANGE: 1288 1289 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " 1290 "%02x:%02x.%x flags: %02x ext: %08x\n", 1291 PCI_BUS_NUM(e->devid), 1292 PCI_SLOT(e->devid), 1293 PCI_FUNC(e->devid), 1294 e->flags, e->ext); 1295 1296 devid_start = e->devid; 1297 flags = e->flags; 1298 ext_flags = e->ext; 1299 alias = false; 1300 break; 1301 case IVHD_DEV_RANGE_END: 1302 1303 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", 1304 PCI_BUS_NUM(e->devid), 1305 PCI_SLOT(e->devid), 1306 PCI_FUNC(e->devid)); 1307 1308 devid = e->devid; 1309 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1310 if (alias) { 1311 amd_iommu_alias_table[dev_i] = devid_to; 1312 set_dev_entry_from_acpi(iommu, 1313 devid_to, flags, ext_flags); 1314 } 1315 set_dev_entry_from_acpi(iommu, dev_i, 1316 flags, ext_flags); 1317 } 1318 break; 1319 case IVHD_DEV_SPECIAL: { 1320 u8 handle, type; 1321 const char *var; 1322 u16 devid; 1323 int ret; 1324 1325 handle = e->ext & 0xff; 1326 devid = (e->ext >> 8) & 0xffff; 1327 type = (e->ext >> 24) & 0xff; 1328 1329 if (type == IVHD_SPECIAL_IOAPIC) 1330 var = "IOAPIC"; 1331 else if (type == IVHD_SPECIAL_HPET) 1332 var = "HPET"; 1333 else 1334 var = "UNKNOWN"; 1335 1336 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", 1337 var, (int)handle, 1338 PCI_BUS_NUM(devid), 1339 PCI_SLOT(devid), 1340 PCI_FUNC(devid)); 1341 1342 ret = add_special_device(type, handle, &devid, false); 1343 if (ret) 1344 return ret; 1345 1346 /* 1347 * add_special_device might update the devid in case a 1348 * command-line override is present. So call 1349 * set_dev_entry_from_acpi after add_special_device. 1350 */ 1351 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1352 1353 break; 1354 } 1355 case IVHD_DEV_ACPI_HID: { 1356 u16 devid; 1357 u8 hid[ACPIHID_HID_LEN]; 1358 u8 uid[ACPIHID_UID_LEN]; 1359 int ret; 1360 1361 if (h->type != 0x40) { 1362 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1363 e->type); 1364 break; 1365 } 1366 1367 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1); 1368 hid[ACPIHID_HID_LEN - 1] = '\0'; 1369 1370 if (!(*hid)) { 1371 pr_err(FW_BUG "Invalid HID.\n"); 1372 break; 1373 } 1374 1375 uid[0] = '\0'; 1376 switch (e->uidf) { 1377 case UID_NOT_PRESENT: 1378 1379 if (e->uidl != 0) 1380 pr_warn(FW_BUG "Invalid UID length.\n"); 1381 1382 break; 1383 case UID_IS_INTEGER: 1384 1385 sprintf(uid, "%d", e->uid); 1386 1387 break; 1388 case UID_IS_CHARACTER: 1389 1390 memcpy(uid, &e->uid, e->uidl); 1391 uid[e->uidl] = '\0'; 1392 1393 break; 1394 default: 1395 break; 1396 } 1397 1398 devid = e->devid; 1399 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n", 1400 hid, uid, 1401 PCI_BUS_NUM(devid), 1402 PCI_SLOT(devid), 1403 PCI_FUNC(devid)); 1404 1405 flags = e->flags; 1406 1407 ret = add_acpi_hid_device(hid, uid, &devid, false); 1408 if (ret) 1409 return ret; 1410 1411 /* 1412 * add_special_device might update the devid in case a 1413 * command-line override is present. So call 1414 * set_dev_entry_from_acpi after add_special_device. 1415 */ 1416 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1417 1418 break; 1419 } 1420 default: 1421 break; 1422 } 1423 1424 p += ivhd_entry_length(p); 1425 } 1426 1427 return 0; 1428 } 1429 1430 static void __init free_iommu_one(struct amd_iommu *iommu) 1431 { 1432 free_cwwb_sem(iommu); 1433 free_command_buffer(iommu); 1434 free_event_buffer(iommu); 1435 free_ppr_log(iommu); 1436 free_ga_log(iommu); 1437 iommu_unmap_mmio_space(iommu); 1438 } 1439 1440 static void __init free_iommu_all(void) 1441 { 1442 struct amd_iommu *iommu, *next; 1443 1444 for_each_iommu_safe(iommu, next) { 1445 list_del(&iommu->list); 1446 free_iommu_one(iommu); 1447 kfree(iommu); 1448 } 1449 } 1450 1451 /* 1452 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1453 * Workaround: 1454 * BIOS should disable L2B micellaneous clock gating by setting 1455 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1456 */ 1457 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1458 { 1459 u32 value; 1460 1461 if ((boot_cpu_data.x86 != 0x15) || 1462 (boot_cpu_data.x86_model < 0x10) || 1463 (boot_cpu_data.x86_model > 0x1f)) 1464 return; 1465 1466 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1467 pci_read_config_dword(iommu->dev, 0xf4, &value); 1468 1469 if (value & BIT(2)) 1470 return; 1471 1472 /* Select NB indirect register 0x90 and enable writing */ 1473 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1474 1475 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1476 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1477 1478 /* Clear the enable writing bit */ 1479 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1480 } 1481 1482 /* 1483 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1484 * Workaround: 1485 * BIOS should enable ATS write permission check by setting 1486 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1487 */ 1488 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1489 { 1490 u32 value; 1491 1492 if ((boot_cpu_data.x86 != 0x15) || 1493 (boot_cpu_data.x86_model < 0x30) || 1494 (boot_cpu_data.x86_model > 0x3f)) 1495 return; 1496 1497 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1498 value = iommu_read_l2(iommu, 0x47); 1499 1500 if (value & BIT(0)) 1501 return; 1502 1503 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1504 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1505 1506 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1507 } 1508 1509 /* 1510 * This function clues the initialization function for one IOMMU 1511 * together and also allocates the command buffer and programs the 1512 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1513 */ 1514 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) 1515 { 1516 int ret; 1517 1518 raw_spin_lock_init(&iommu->lock); 1519 iommu->cmd_sem_val = 0; 1520 1521 /* Add IOMMU to internal data structures */ 1522 list_add_tail(&iommu->list, &amd_iommu_list); 1523 iommu->index = amd_iommus_present++; 1524 1525 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1526 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1527 return -ENOSYS; 1528 } 1529 1530 /* Index is fine - add IOMMU to the array */ 1531 amd_iommus[iommu->index] = iommu; 1532 1533 /* 1534 * Copy data from ACPI table entry to the iommu struct 1535 */ 1536 iommu->devid = h->devid; 1537 iommu->cap_ptr = h->cap_ptr; 1538 iommu->pci_seg = h->pci_seg; 1539 iommu->mmio_phys = h->mmio_phys; 1540 1541 switch (h->type) { 1542 case 0x10: 1543 /* Check if IVHD EFR contains proper max banks/counters */ 1544 if ((h->efr_attr != 0) && 1545 ((h->efr_attr & (0xF << 13)) != 0) && 1546 ((h->efr_attr & (0x3F << 17)) != 0)) 1547 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1548 else 1549 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1550 1551 /* 1552 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1553 * GAM also requires GA mode. Therefore, we need to 1554 * check cmpxchg16b support before enabling it. 1555 */ 1556 if (!boot_cpu_has(X86_FEATURE_CX16) || 1557 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) 1558 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1559 break; 1560 case 0x11: 1561 case 0x40: 1562 if (h->efr_reg & (1 << 9)) 1563 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1564 else 1565 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1566 1567 /* 1568 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1569 * XT, GAM also requires GA mode. Therefore, we need to 1570 * check cmpxchg16b support before enabling them. 1571 */ 1572 if (!boot_cpu_has(X86_FEATURE_CX16) || 1573 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) { 1574 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1575 break; 1576 } 1577 1578 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1579 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1580 break; 1581 default: 1582 return -EINVAL; 1583 } 1584 1585 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1586 iommu->mmio_phys_end); 1587 if (!iommu->mmio_base) 1588 return -ENOMEM; 1589 1590 if (alloc_cwwb_sem(iommu)) 1591 return -ENOMEM; 1592 1593 if (alloc_command_buffer(iommu)) 1594 return -ENOMEM; 1595 1596 if (alloc_event_buffer(iommu)) 1597 return -ENOMEM; 1598 1599 iommu->int_enabled = false; 1600 1601 init_translation_status(iommu); 1602 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1603 iommu_disable(iommu); 1604 clear_translation_pre_enabled(iommu); 1605 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1606 iommu->index); 1607 } 1608 if (amd_iommu_pre_enabled) 1609 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1610 1611 ret = init_iommu_from_acpi(iommu, h); 1612 if (ret) 1613 return ret; 1614 1615 if (amd_iommu_irq_remap) { 1616 ret = amd_iommu_create_irq_domain(iommu); 1617 if (ret) 1618 return ret; 1619 } 1620 1621 /* 1622 * Make sure IOMMU is not considered to translate itself. The IVRS 1623 * table tells us so, but this is a lie! 1624 */ 1625 amd_iommu_rlookup_table[iommu->devid] = NULL; 1626 1627 return 0; 1628 } 1629 1630 /** 1631 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1632 * @ivrs: Pointer to the IVRS header 1633 * 1634 * This function search through all IVDB of the maximum supported IVHD 1635 */ 1636 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1637 { 1638 u8 *base = (u8 *)ivrs; 1639 struct ivhd_header *ivhd = (struct ivhd_header *) 1640 (base + IVRS_HEADER_LENGTH); 1641 u8 last_type = ivhd->type; 1642 u16 devid = ivhd->devid; 1643 1644 while (((u8 *)ivhd - base < ivrs->length) && 1645 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1646 u8 *p = (u8 *) ivhd; 1647 1648 if (ivhd->devid == devid) 1649 last_type = ivhd->type; 1650 ivhd = (struct ivhd_header *)(p + ivhd->length); 1651 } 1652 1653 return last_type; 1654 } 1655 1656 /* 1657 * Iterates over all IOMMU entries in the ACPI table, allocates the 1658 * IOMMU structure and initializes it with init_iommu_one() 1659 */ 1660 static int __init init_iommu_all(struct acpi_table_header *table) 1661 { 1662 u8 *p = (u8 *)table, *end = (u8 *)table; 1663 struct ivhd_header *h; 1664 struct amd_iommu *iommu; 1665 int ret; 1666 1667 end += table->length; 1668 p += IVRS_HEADER_LENGTH; 1669 1670 while (p < end) { 1671 h = (struct ivhd_header *)p; 1672 if (*p == amd_iommu_target_ivhd_type) { 1673 1674 DUMP_printk("device: %02x:%02x.%01x cap: %04x " 1675 "seg: %d flags: %01x info %04x\n", 1676 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid), 1677 PCI_FUNC(h->devid), h->cap_ptr, 1678 h->pci_seg, h->flags, h->info); 1679 DUMP_printk(" mmio-addr: %016llx\n", 1680 h->mmio_phys); 1681 1682 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1683 if (iommu == NULL) 1684 return -ENOMEM; 1685 1686 ret = init_iommu_one(iommu, h); 1687 if (ret) 1688 return ret; 1689 } 1690 p += h->length; 1691 1692 } 1693 WARN_ON(p != end); 1694 1695 return 0; 1696 } 1697 1698 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 1699 u8 fxn, u64 *value, bool is_write); 1700 1701 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1702 { 1703 struct pci_dev *pdev = iommu->dev; 1704 u64 val = 0xabcd, val2 = 0, save_reg = 0; 1705 1706 if (!iommu_feature(iommu, FEATURE_PC)) 1707 return; 1708 1709 amd_iommu_pc_present = true; 1710 1711 /* save the value to restore, if writable */ 1712 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false)) 1713 goto pc_false; 1714 1715 /* Check if the performance counters can be written to */ 1716 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) || 1717 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) || 1718 (val != val2)) 1719 goto pc_false; 1720 1721 /* restore */ 1722 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true)) 1723 goto pc_false; 1724 1725 pci_info(pdev, "IOMMU performance counters supported\n"); 1726 1727 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1728 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1729 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1730 1731 return; 1732 1733 pc_false: 1734 pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n"); 1735 amd_iommu_pc_present = false; 1736 return; 1737 } 1738 1739 static ssize_t amd_iommu_show_cap(struct device *dev, 1740 struct device_attribute *attr, 1741 char *buf) 1742 { 1743 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1744 return sprintf(buf, "%x\n", iommu->cap); 1745 } 1746 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1747 1748 static ssize_t amd_iommu_show_features(struct device *dev, 1749 struct device_attribute *attr, 1750 char *buf) 1751 { 1752 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1753 return sprintf(buf, "%llx\n", iommu->features); 1754 } 1755 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1756 1757 static struct attribute *amd_iommu_attrs[] = { 1758 &dev_attr_cap.attr, 1759 &dev_attr_features.attr, 1760 NULL, 1761 }; 1762 1763 static struct attribute_group amd_iommu_group = { 1764 .name = "amd-iommu", 1765 .attrs = amd_iommu_attrs, 1766 }; 1767 1768 static const struct attribute_group *amd_iommu_groups[] = { 1769 &amd_iommu_group, 1770 NULL, 1771 }; 1772 1773 static int __init iommu_init_pci(struct amd_iommu *iommu) 1774 { 1775 int cap_ptr = iommu->cap_ptr; 1776 int ret; 1777 1778 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), 1779 iommu->devid & 0xff); 1780 if (!iommu->dev) 1781 return -ENODEV; 1782 1783 /* Prevent binding other PCI device drivers to IOMMU devices */ 1784 iommu->dev->match_driver = false; 1785 1786 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 1787 &iommu->cap); 1788 1789 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 1790 amd_iommu_iotlb_sup = false; 1791 1792 /* read extended feature bits */ 1793 iommu->features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1794 1795 if (iommu_feature(iommu, FEATURE_GT)) { 1796 int glxval; 1797 u32 max_pasid; 1798 u64 pasmax; 1799 1800 pasmax = iommu->features & FEATURE_PASID_MASK; 1801 pasmax >>= FEATURE_PASID_SHIFT; 1802 max_pasid = (1 << (pasmax + 1)) - 1; 1803 1804 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); 1805 1806 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); 1807 1808 glxval = iommu->features & FEATURE_GLXVAL_MASK; 1809 glxval >>= FEATURE_GLXVAL_SHIFT; 1810 1811 if (amd_iommu_max_glx_val == -1) 1812 amd_iommu_max_glx_val = glxval; 1813 else 1814 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 1815 } 1816 1817 if (iommu_feature(iommu, FEATURE_GT) && 1818 iommu_feature(iommu, FEATURE_PPR)) { 1819 iommu->is_iommu_v2 = true; 1820 amd_iommu_v2_present = true; 1821 } 1822 1823 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) 1824 return -ENOMEM; 1825 1826 ret = iommu_init_ga(iommu); 1827 if (ret) 1828 return ret; 1829 1830 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) 1831 amd_iommu_np_cache = true; 1832 1833 init_iommu_perf_ctr(iommu); 1834 1835 if (is_rd890_iommu(iommu->dev)) { 1836 int i, j; 1837 1838 iommu->root_pdev = 1839 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, 1840 PCI_DEVFN(0, 0)); 1841 1842 /* 1843 * Some rd890 systems may not be fully reconfigured by the 1844 * BIOS, so it's necessary for us to store this information so 1845 * it can be reprogrammed on resume 1846 */ 1847 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 1848 &iommu->stored_addr_lo); 1849 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 1850 &iommu->stored_addr_hi); 1851 1852 /* Low bit locks writes to configuration space */ 1853 iommu->stored_addr_lo &= ~1; 1854 1855 for (i = 0; i < 6; i++) 1856 for (j = 0; j < 0x12; j++) 1857 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 1858 1859 for (i = 0; i < 0x83; i++) 1860 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 1861 } 1862 1863 amd_iommu_erratum_746_workaround(iommu); 1864 amd_iommu_ats_write_check_workaround(iommu); 1865 1866 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 1867 amd_iommu_groups, "ivhd%d", iommu->index); 1868 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops); 1869 iommu_device_register(&iommu->iommu); 1870 1871 return pci_enable_device(iommu->dev); 1872 } 1873 1874 static void print_iommu_info(void) 1875 { 1876 static const char * const feat_str[] = { 1877 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 1878 "IA", "GA", "HE", "PC" 1879 }; 1880 struct amd_iommu *iommu; 1881 1882 for_each_iommu(iommu) { 1883 struct pci_dev *pdev = iommu->dev; 1884 int i; 1885 1886 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr); 1887 1888 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { 1889 pci_info(pdev, "Extended features (%#llx):", 1890 iommu->features); 1891 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 1892 if (iommu_feature(iommu, (1ULL << i))) 1893 pr_cont(" %s", feat_str[i]); 1894 } 1895 1896 if (iommu->features & FEATURE_GAM_VAPIC) 1897 pr_cont(" GA_vAPIC"); 1898 1899 pr_cont("\n"); 1900 } 1901 } 1902 if (irq_remapping_enabled) { 1903 pr_info("Interrupt remapping enabled\n"); 1904 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 1905 pr_info("Virtual APIC enabled\n"); 1906 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 1907 pr_info("X2APIC enabled\n"); 1908 } 1909 } 1910 1911 static int __init amd_iommu_init_pci(void) 1912 { 1913 struct amd_iommu *iommu; 1914 int ret = 0; 1915 1916 for_each_iommu(iommu) { 1917 ret = iommu_init_pci(iommu); 1918 if (ret) 1919 break; 1920 1921 /* Need to setup range after PCI init */ 1922 iommu_set_cwwb_range(iommu); 1923 } 1924 1925 /* 1926 * Order is important here to make sure any unity map requirements are 1927 * fulfilled. The unity mappings are created and written to the device 1928 * table during the amd_iommu_init_api() call. 1929 * 1930 * After that we call init_device_table_dma() to make sure any 1931 * uninitialized DTE will block DMA, and in the end we flush the caches 1932 * of all IOMMUs to make sure the changes to the device table are 1933 * active. 1934 */ 1935 ret = amd_iommu_init_api(); 1936 1937 init_device_table_dma(); 1938 1939 for_each_iommu(iommu) 1940 iommu_flush_all_caches(iommu); 1941 1942 if (!ret) 1943 print_iommu_info(); 1944 1945 return ret; 1946 } 1947 1948 /**************************************************************************** 1949 * 1950 * The following functions initialize the MSI interrupts for all IOMMUs 1951 * in the system. It's a bit challenging because there could be multiple 1952 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 1953 * pci_dev. 1954 * 1955 ****************************************************************************/ 1956 1957 static int iommu_setup_msi(struct amd_iommu *iommu) 1958 { 1959 int r; 1960 1961 r = pci_enable_msi(iommu->dev); 1962 if (r) 1963 return r; 1964 1965 r = request_threaded_irq(iommu->dev->irq, 1966 amd_iommu_int_handler, 1967 amd_iommu_int_thread, 1968 0, "AMD-Vi", 1969 iommu); 1970 1971 if (r) { 1972 pci_disable_msi(iommu->dev); 1973 return r; 1974 } 1975 1976 return 0; 1977 } 1978 1979 union intcapxt { 1980 u64 capxt; 1981 struct { 1982 u64 reserved_0 : 2, 1983 dest_mode_logical : 1, 1984 reserved_1 : 5, 1985 destid_0_23 : 24, 1986 vector : 8, 1987 reserved_2 : 16, 1988 destid_24_31 : 8; 1989 }; 1990 } __attribute__ ((packed)); 1991 1992 /* 1993 * There isn't really any need to mask/unmask at the irqchip level because 1994 * the 64-bit INTCAPXT registers can be updated atomically without tearing 1995 * when the affinity is being updated. 1996 */ 1997 static void intcapxt_unmask_irq(struct irq_data *data) 1998 { 1999 } 2000 2001 static void intcapxt_mask_irq(struct irq_data *data) 2002 { 2003 } 2004 2005 static struct irq_chip intcapxt_controller; 2006 2007 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2008 struct irq_data *irqd, bool reserve) 2009 { 2010 struct amd_iommu *iommu = irqd->chip_data; 2011 struct irq_cfg *cfg = irqd_cfg(irqd); 2012 union intcapxt xt; 2013 2014 xt.capxt = 0ULL; 2015 xt.dest_mode_logical = apic->dest_mode_logical; 2016 xt.vector = cfg->vector; 2017 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2018 xt.destid_24_31 = cfg->dest_apicid >> 24; 2019 2020 /** 2021 * Current IOMMU implemtation uses the same IRQ for all 2022 * 3 IOMMU interrupts. 2023 */ 2024 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2025 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2026 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2027 return 0; 2028 } 2029 2030 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2031 struct irq_data *irqd) 2032 { 2033 intcapxt_mask_irq(irqd); 2034 } 2035 2036 2037 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2038 unsigned int nr_irqs, void *arg) 2039 { 2040 struct irq_alloc_info *info = arg; 2041 int i, ret; 2042 2043 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2044 return -EINVAL; 2045 2046 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2047 if (ret < 0) 2048 return ret; 2049 2050 for (i = virq; i < virq + nr_irqs; i++) { 2051 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2052 2053 irqd->chip = &intcapxt_controller; 2054 irqd->chip_data = info->data; 2055 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2056 } 2057 2058 return ret; 2059 } 2060 2061 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2062 unsigned int nr_irqs) 2063 { 2064 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2065 } 2066 2067 static int intcapxt_set_affinity(struct irq_data *irqd, 2068 const struct cpumask *mask, bool force) 2069 { 2070 struct irq_data *parent = irqd->parent_data; 2071 int ret; 2072 2073 ret = parent->chip->irq_set_affinity(parent, mask, force); 2074 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2075 return ret; 2076 2077 return intcapxt_irqdomain_activate(irqd->domain, irqd, false); 2078 } 2079 2080 static struct irq_chip intcapxt_controller = { 2081 .name = "IOMMU-MSI", 2082 .irq_unmask = intcapxt_unmask_irq, 2083 .irq_mask = intcapxt_mask_irq, 2084 .irq_ack = irq_chip_ack_parent, 2085 .irq_retrigger = irq_chip_retrigger_hierarchy, 2086 .irq_set_affinity = intcapxt_set_affinity, 2087 .flags = IRQCHIP_SKIP_SET_WAKE, 2088 }; 2089 2090 static const struct irq_domain_ops intcapxt_domain_ops = { 2091 .alloc = intcapxt_irqdomain_alloc, 2092 .free = intcapxt_irqdomain_free, 2093 .activate = intcapxt_irqdomain_activate, 2094 .deactivate = intcapxt_irqdomain_deactivate, 2095 }; 2096 2097 2098 static struct irq_domain *iommu_irqdomain; 2099 2100 static struct irq_domain *iommu_get_irqdomain(void) 2101 { 2102 struct fwnode_handle *fn; 2103 2104 /* No need for locking here (yet) as the init is single-threaded */ 2105 if (iommu_irqdomain) 2106 return iommu_irqdomain; 2107 2108 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2109 if (!fn) 2110 return NULL; 2111 2112 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2113 fn, &intcapxt_domain_ops, 2114 NULL); 2115 if (!iommu_irqdomain) 2116 irq_domain_free_fwnode(fn); 2117 2118 return iommu_irqdomain; 2119 } 2120 2121 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2122 { 2123 struct irq_domain *domain; 2124 struct irq_alloc_info info; 2125 int irq, ret; 2126 2127 domain = iommu_get_irqdomain(); 2128 if (!domain) 2129 return -ENXIO; 2130 2131 init_irq_alloc_info(&info, NULL); 2132 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2133 info.data = iommu; 2134 2135 irq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 2136 if (irq < 0) { 2137 irq_domain_remove(domain); 2138 return irq; 2139 } 2140 2141 ret = request_threaded_irq(irq, amd_iommu_int_handler, 2142 amd_iommu_int_thread, 0, "AMD-Vi", iommu); 2143 if (ret) { 2144 irq_domain_free_irqs(irq, 1); 2145 irq_domain_remove(domain); 2146 return ret; 2147 } 2148 2149 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2150 return 0; 2151 } 2152 2153 static int iommu_init_irq(struct amd_iommu *iommu) 2154 { 2155 int ret; 2156 2157 if (iommu->int_enabled) 2158 goto enable_faults; 2159 2160 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2161 ret = iommu_setup_intcapxt(iommu); 2162 else if (iommu->dev->msi_cap) 2163 ret = iommu_setup_msi(iommu); 2164 else 2165 ret = -ENODEV; 2166 2167 if (ret) 2168 return ret; 2169 2170 iommu->int_enabled = true; 2171 enable_faults: 2172 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2173 2174 if (iommu->ppr_log != NULL) 2175 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); 2176 2177 iommu_ga_log_enable(iommu); 2178 2179 return 0; 2180 } 2181 2182 /**************************************************************************** 2183 * 2184 * The next functions belong to the third pass of parsing the ACPI 2185 * table. In this last pass the memory mapping requirements are 2186 * gathered (like exclusion and unity mapping ranges). 2187 * 2188 ****************************************************************************/ 2189 2190 static void __init free_unity_maps(void) 2191 { 2192 struct unity_map_entry *entry, *next; 2193 2194 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { 2195 list_del(&entry->list); 2196 kfree(entry); 2197 } 2198 } 2199 2200 /* called for unity map ACPI definition */ 2201 static int __init init_unity_map_range(struct ivmd_header *m) 2202 { 2203 struct unity_map_entry *e = NULL; 2204 char *s; 2205 2206 e = kzalloc(sizeof(*e), GFP_KERNEL); 2207 if (e == NULL) 2208 return -ENOMEM; 2209 2210 switch (m->type) { 2211 default: 2212 kfree(e); 2213 return 0; 2214 case ACPI_IVMD_TYPE: 2215 s = "IVMD_TYPEi\t\t\t"; 2216 e->devid_start = e->devid_end = m->devid; 2217 break; 2218 case ACPI_IVMD_TYPE_ALL: 2219 s = "IVMD_TYPE_ALL\t\t"; 2220 e->devid_start = 0; 2221 e->devid_end = amd_iommu_last_bdf; 2222 break; 2223 case ACPI_IVMD_TYPE_RANGE: 2224 s = "IVMD_TYPE_RANGE\t\t"; 2225 e->devid_start = m->devid; 2226 e->devid_end = m->aux; 2227 break; 2228 } 2229 e->address_start = PAGE_ALIGN(m->range_start); 2230 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2231 e->prot = m->flags >> 1; 2232 2233 /* 2234 * Treat per-device exclusion ranges as r/w unity-mapped regions 2235 * since some buggy BIOSes might lead to the overwritten exclusion 2236 * range (exclusion_start and exclusion_length members). This 2237 * happens when there are multiple exclusion ranges (IVMD entries) 2238 * defined in ACPI table. 2239 */ 2240 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2241 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2242 2243 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" 2244 " range_start: %016llx range_end: %016llx flags: %x\n", s, 2245 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2246 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end), 2247 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2248 e->address_start, e->address_end, m->flags); 2249 2250 list_add_tail(&e->list, &amd_iommu_unity_map); 2251 2252 return 0; 2253 } 2254 2255 /* iterates over all memory definitions we find in the ACPI table */ 2256 static int __init init_memory_definitions(struct acpi_table_header *table) 2257 { 2258 u8 *p = (u8 *)table, *end = (u8 *)table; 2259 struct ivmd_header *m; 2260 2261 end += table->length; 2262 p += IVRS_HEADER_LENGTH; 2263 2264 while (p < end) { 2265 m = (struct ivmd_header *)p; 2266 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2267 init_unity_map_range(m); 2268 2269 p += m->length; 2270 } 2271 2272 return 0; 2273 } 2274 2275 /* 2276 * Init the device table to not allow DMA access for devices 2277 */ 2278 static void init_device_table_dma(void) 2279 { 2280 u32 devid; 2281 2282 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2283 set_dev_entry_bit(devid, DEV_ENTRY_VALID); 2284 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); 2285 } 2286 } 2287 2288 static void __init uninit_device_table_dma(void) 2289 { 2290 u32 devid; 2291 2292 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2293 amd_iommu_dev_table[devid].data[0] = 0ULL; 2294 amd_iommu_dev_table[devid].data[1] = 0ULL; 2295 } 2296 } 2297 2298 static void init_device_table(void) 2299 { 2300 u32 devid; 2301 2302 if (!amd_iommu_irq_remap) 2303 return; 2304 2305 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) 2306 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); 2307 } 2308 2309 static void iommu_init_flags(struct amd_iommu *iommu) 2310 { 2311 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2312 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2313 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2314 2315 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2316 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2317 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2318 2319 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2320 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2321 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2322 2323 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2324 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2325 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2326 2327 /* 2328 * make IOMMU memory accesses cache coherent 2329 */ 2330 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2331 2332 /* Set IOTLB invalidation timeout to 1s */ 2333 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); 2334 } 2335 2336 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2337 { 2338 int i, j; 2339 u32 ioc_feature_control; 2340 struct pci_dev *pdev = iommu->root_pdev; 2341 2342 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2343 if (!is_rd890_iommu(iommu->dev) || !pdev) 2344 return; 2345 2346 /* 2347 * First, we need to ensure that the iommu is enabled. This is 2348 * controlled by a register in the northbridge 2349 */ 2350 2351 /* Select Northbridge indirect register 0x75 and enable writing */ 2352 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2353 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2354 2355 /* Enable the iommu */ 2356 if (!(ioc_feature_control & 0x1)) 2357 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2358 2359 /* Restore the iommu BAR */ 2360 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2361 iommu->stored_addr_lo); 2362 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2363 iommu->stored_addr_hi); 2364 2365 /* Restore the l1 indirect regs for each of the 6 l1s */ 2366 for (i = 0; i < 6; i++) 2367 for (j = 0; j < 0x12; j++) 2368 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2369 2370 /* Restore the l2 indirect regs */ 2371 for (i = 0; i < 0x83; i++) 2372 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2373 2374 /* Lock PCI setup registers */ 2375 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2376 iommu->stored_addr_lo | 1); 2377 } 2378 2379 static void iommu_enable_ga(struct amd_iommu *iommu) 2380 { 2381 #ifdef CONFIG_IRQ_REMAP 2382 switch (amd_iommu_guest_ir) { 2383 case AMD_IOMMU_GUEST_IR_VAPIC: 2384 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2385 fallthrough; 2386 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2387 iommu_feature_enable(iommu, CONTROL_GA_EN); 2388 iommu->irte_ops = &irte_128_ops; 2389 break; 2390 default: 2391 iommu->irte_ops = &irte_32_ops; 2392 break; 2393 } 2394 #endif 2395 } 2396 2397 static void early_enable_iommu(struct amd_iommu *iommu) 2398 { 2399 iommu_disable(iommu); 2400 iommu_init_flags(iommu); 2401 iommu_set_device_table(iommu); 2402 iommu_enable_command_buffer(iommu); 2403 iommu_enable_event_buffer(iommu); 2404 iommu_set_exclusion_range(iommu); 2405 iommu_enable_ga(iommu); 2406 iommu_enable_xt(iommu); 2407 iommu_enable(iommu); 2408 iommu_flush_all_caches(iommu); 2409 } 2410 2411 /* 2412 * This function finally enables all IOMMUs found in the system after 2413 * they have been initialized. 2414 * 2415 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2416 * the old content of device table entries. Not this case or copy failed, 2417 * just continue as normal kernel does. 2418 */ 2419 static void early_enable_iommus(void) 2420 { 2421 struct amd_iommu *iommu; 2422 2423 2424 if (!copy_device_table()) { 2425 /* 2426 * If come here because of failure in copying device table from old 2427 * kernel with all IOMMUs enabled, print error message and try to 2428 * free allocated old_dev_tbl_cpy. 2429 */ 2430 if (amd_iommu_pre_enabled) 2431 pr_err("Failed to copy DEV table from previous kernel.\n"); 2432 if (old_dev_tbl_cpy != NULL) 2433 free_pages((unsigned long)old_dev_tbl_cpy, 2434 get_order(dev_table_size)); 2435 2436 for_each_iommu(iommu) { 2437 clear_translation_pre_enabled(iommu); 2438 early_enable_iommu(iommu); 2439 } 2440 } else { 2441 pr_info("Copied DEV table from previous kernel.\n"); 2442 free_pages((unsigned long)amd_iommu_dev_table, 2443 get_order(dev_table_size)); 2444 amd_iommu_dev_table = old_dev_tbl_cpy; 2445 for_each_iommu(iommu) { 2446 iommu_disable_command_buffer(iommu); 2447 iommu_disable_event_buffer(iommu); 2448 iommu_enable_command_buffer(iommu); 2449 iommu_enable_event_buffer(iommu); 2450 iommu_enable_ga(iommu); 2451 iommu_enable_xt(iommu); 2452 iommu_set_device_table(iommu); 2453 iommu_flush_all_caches(iommu); 2454 } 2455 } 2456 2457 #ifdef CONFIG_IRQ_REMAP 2458 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2459 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2460 #endif 2461 } 2462 2463 static void enable_iommus_v2(void) 2464 { 2465 struct amd_iommu *iommu; 2466 2467 for_each_iommu(iommu) { 2468 iommu_enable_ppr_log(iommu); 2469 iommu_enable_gt(iommu); 2470 } 2471 } 2472 2473 static void enable_iommus(void) 2474 { 2475 early_enable_iommus(); 2476 2477 enable_iommus_v2(); 2478 } 2479 2480 static void disable_iommus(void) 2481 { 2482 struct amd_iommu *iommu; 2483 2484 for_each_iommu(iommu) 2485 iommu_disable(iommu); 2486 2487 #ifdef CONFIG_IRQ_REMAP 2488 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2489 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2490 #endif 2491 } 2492 2493 /* 2494 * Suspend/Resume support 2495 * disable suspend until real resume implemented 2496 */ 2497 2498 static void amd_iommu_resume(void) 2499 { 2500 struct amd_iommu *iommu; 2501 2502 for_each_iommu(iommu) 2503 iommu_apply_resume_quirks(iommu); 2504 2505 /* re-load the hardware */ 2506 enable_iommus(); 2507 2508 amd_iommu_enable_interrupts(); 2509 } 2510 2511 static int amd_iommu_suspend(void) 2512 { 2513 /* disable IOMMUs to go out of the way for BIOS */ 2514 disable_iommus(); 2515 2516 return 0; 2517 } 2518 2519 static struct syscore_ops amd_iommu_syscore_ops = { 2520 .suspend = amd_iommu_suspend, 2521 .resume = amd_iommu_resume, 2522 }; 2523 2524 static void __init free_iommu_resources(void) 2525 { 2526 kmemleak_free(irq_lookup_table); 2527 free_pages((unsigned long)irq_lookup_table, 2528 get_order(rlookup_table_size)); 2529 irq_lookup_table = NULL; 2530 2531 kmem_cache_destroy(amd_iommu_irq_cache); 2532 amd_iommu_irq_cache = NULL; 2533 2534 free_pages((unsigned long)amd_iommu_rlookup_table, 2535 get_order(rlookup_table_size)); 2536 amd_iommu_rlookup_table = NULL; 2537 2538 free_pages((unsigned long)amd_iommu_alias_table, 2539 get_order(alias_table_size)); 2540 amd_iommu_alias_table = NULL; 2541 2542 free_pages((unsigned long)amd_iommu_dev_table, 2543 get_order(dev_table_size)); 2544 amd_iommu_dev_table = NULL; 2545 2546 free_iommu_all(); 2547 } 2548 2549 /* SB IOAPIC is always on this device in AMD systems */ 2550 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2551 2552 static bool __init check_ioapic_information(void) 2553 { 2554 const char *fw_bug = FW_BUG; 2555 bool ret, has_sb_ioapic; 2556 int idx; 2557 2558 has_sb_ioapic = false; 2559 ret = false; 2560 2561 /* 2562 * If we have map overrides on the kernel command line the 2563 * messages in this function might not describe firmware bugs 2564 * anymore - so be careful 2565 */ 2566 if (cmdline_maps) 2567 fw_bug = ""; 2568 2569 for (idx = 0; idx < nr_ioapics; idx++) { 2570 int devid, id = mpc_ioapic_id(idx); 2571 2572 devid = get_ioapic_devid(id); 2573 if (devid < 0) { 2574 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2575 fw_bug, id); 2576 ret = false; 2577 } else if (devid == IOAPIC_SB_DEVID) { 2578 has_sb_ioapic = true; 2579 ret = true; 2580 } 2581 } 2582 2583 if (!has_sb_ioapic) { 2584 /* 2585 * We expect the SB IOAPIC to be listed in the IVRS 2586 * table. The system timer is connected to the SB IOAPIC 2587 * and if we don't have it in the list the system will 2588 * panic at boot time. This situation usually happens 2589 * when the BIOS is buggy and provides us the wrong 2590 * device id for the IOAPIC in the system. 2591 */ 2592 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2593 } 2594 2595 if (!ret) 2596 pr_err("Disabling interrupt remapping\n"); 2597 2598 return ret; 2599 } 2600 2601 static void __init free_dma_resources(void) 2602 { 2603 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 2604 get_order(MAX_DOMAIN_ID/8)); 2605 amd_iommu_pd_alloc_bitmap = NULL; 2606 2607 free_unity_maps(); 2608 } 2609 2610 /* 2611 * This is the hardware init function for AMD IOMMU in the system. 2612 * This function is called either from amd_iommu_init or from the interrupt 2613 * remapping setup code. 2614 * 2615 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 2616 * four times: 2617 * 2618 * 1 pass) Discover the most comprehensive IVHD type to use. 2619 * 2620 * 2 pass) Find the highest PCI device id the driver has to handle. 2621 * Upon this information the size of the data structures is 2622 * determined that needs to be allocated. 2623 * 2624 * 3 pass) Initialize the data structures just allocated with the 2625 * information in the ACPI table about available AMD IOMMUs 2626 * in the system. It also maps the PCI devices in the 2627 * system to specific IOMMUs 2628 * 2629 * 4 pass) After the basic data structures are allocated and 2630 * initialized we update them with information about memory 2631 * remapping requirements parsed out of the ACPI table in 2632 * this last pass. 2633 * 2634 * After everything is set up the IOMMUs are enabled and the necessary 2635 * hotplug and suspend notifiers are registered. 2636 */ 2637 static int __init early_amd_iommu_init(void) 2638 { 2639 struct acpi_table_header *ivrs_base; 2640 acpi_status status; 2641 int i, remap_cache_sz, ret = 0; 2642 u32 pci_id; 2643 2644 if (!amd_iommu_detected) 2645 return -ENODEV; 2646 2647 status = acpi_get_table("IVRS", 0, &ivrs_base); 2648 if (status == AE_NOT_FOUND) 2649 return -ENODEV; 2650 else if (ACPI_FAILURE(status)) { 2651 const char *err = acpi_format_exception(status); 2652 pr_err("IVRS table error: %s\n", err); 2653 return -EINVAL; 2654 } 2655 2656 /* 2657 * Validate checksum here so we don't need to do it when 2658 * we actually parse the table 2659 */ 2660 ret = check_ivrs_checksum(ivrs_base); 2661 if (ret) 2662 goto out; 2663 2664 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 2665 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 2666 2667 /* 2668 * First parse ACPI tables to find the largest Bus/Dev/Func 2669 * we need to handle. Upon this information the shared data 2670 * structures for the IOMMUs in the system will be allocated 2671 */ 2672 ret = find_last_devid_acpi(ivrs_base); 2673 if (ret) 2674 goto out; 2675 2676 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 2677 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 2678 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); 2679 2680 /* Device table - directly used by all IOMMUs */ 2681 ret = -ENOMEM; 2682 amd_iommu_dev_table = (void *)__get_free_pages( 2683 GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 2684 get_order(dev_table_size)); 2685 if (amd_iommu_dev_table == NULL) 2686 goto out; 2687 2688 /* 2689 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the 2690 * IOMMU see for that device 2691 */ 2692 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, 2693 get_order(alias_table_size)); 2694 if (amd_iommu_alias_table == NULL) 2695 goto out; 2696 2697 /* IOMMU rlookup table - find the IOMMU for a specific device */ 2698 amd_iommu_rlookup_table = (void *)__get_free_pages( 2699 GFP_KERNEL | __GFP_ZERO, 2700 get_order(rlookup_table_size)); 2701 if (amd_iommu_rlookup_table == NULL) 2702 goto out; 2703 2704 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( 2705 GFP_KERNEL | __GFP_ZERO, 2706 get_order(MAX_DOMAIN_ID/8)); 2707 if (amd_iommu_pd_alloc_bitmap == NULL) 2708 goto out; 2709 2710 /* 2711 * let all alias entries point to itself 2712 */ 2713 for (i = 0; i <= amd_iommu_last_bdf; ++i) 2714 amd_iommu_alias_table[i] = i; 2715 2716 /* 2717 * never allocate domain 0 because its used as the non-allocated and 2718 * error value placeholder 2719 */ 2720 __set_bit(0, amd_iommu_pd_alloc_bitmap); 2721 2722 /* 2723 * now the data structures are allocated and basically initialized 2724 * start the real acpi table scan 2725 */ 2726 ret = init_iommu_all(ivrs_base); 2727 if (ret) 2728 goto out; 2729 2730 /* Disable IOMMU if there's Stoney Ridge graphics */ 2731 for (i = 0; i < 32; i++) { 2732 pci_id = read_pci_config(0, i, 0, 0); 2733 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 2734 pr_info("Disable IOMMU on Stoney Ridge\n"); 2735 amd_iommu_disabled = true; 2736 break; 2737 } 2738 } 2739 2740 /* Disable any previously enabled IOMMUs */ 2741 if (!is_kdump_kernel() || amd_iommu_disabled) 2742 disable_iommus(); 2743 2744 if (amd_iommu_irq_remap) 2745 amd_iommu_irq_remap = check_ioapic_information(); 2746 2747 if (amd_iommu_irq_remap) { 2748 /* 2749 * Interrupt remapping enabled, create kmem_cache for the 2750 * remapping tables. 2751 */ 2752 ret = -ENOMEM; 2753 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 2754 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32); 2755 else 2756 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2); 2757 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", 2758 remap_cache_sz, 2759 DTE_INTTAB_ALIGNMENT, 2760 0, NULL); 2761 if (!amd_iommu_irq_cache) 2762 goto out; 2763 2764 irq_lookup_table = (void *)__get_free_pages( 2765 GFP_KERNEL | __GFP_ZERO, 2766 get_order(rlookup_table_size)); 2767 kmemleak_alloc(irq_lookup_table, rlookup_table_size, 2768 1, GFP_KERNEL); 2769 if (!irq_lookup_table) 2770 goto out; 2771 } 2772 2773 ret = init_memory_definitions(ivrs_base); 2774 if (ret) 2775 goto out; 2776 2777 /* init the device table */ 2778 init_device_table(); 2779 2780 out: 2781 /* Don't leak any ACPI memory */ 2782 acpi_put_table(ivrs_base); 2783 ivrs_base = NULL; 2784 2785 return ret; 2786 } 2787 2788 static int amd_iommu_enable_interrupts(void) 2789 { 2790 struct amd_iommu *iommu; 2791 int ret = 0; 2792 2793 for_each_iommu(iommu) { 2794 ret = iommu_init_irq(iommu); 2795 if (ret) 2796 goto out; 2797 } 2798 2799 out: 2800 return ret; 2801 } 2802 2803 static bool detect_ivrs(void) 2804 { 2805 struct acpi_table_header *ivrs_base; 2806 acpi_status status; 2807 2808 status = acpi_get_table("IVRS", 0, &ivrs_base); 2809 if (status == AE_NOT_FOUND) 2810 return false; 2811 else if (ACPI_FAILURE(status)) { 2812 const char *err = acpi_format_exception(status); 2813 pr_err("IVRS table error: %s\n", err); 2814 return false; 2815 } 2816 2817 acpi_put_table(ivrs_base); 2818 2819 /* Make sure ACS will be enabled during PCI probe */ 2820 pci_request_acs(); 2821 2822 return true; 2823 } 2824 2825 /**************************************************************************** 2826 * 2827 * AMD IOMMU Initialization State Machine 2828 * 2829 ****************************************************************************/ 2830 2831 static int __init state_next(void) 2832 { 2833 int ret = 0; 2834 2835 switch (init_state) { 2836 case IOMMU_START_STATE: 2837 if (!detect_ivrs()) { 2838 init_state = IOMMU_NOT_FOUND; 2839 ret = -ENODEV; 2840 } else { 2841 init_state = IOMMU_IVRS_DETECTED; 2842 } 2843 break; 2844 case IOMMU_IVRS_DETECTED: 2845 ret = early_amd_iommu_init(); 2846 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 2847 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) { 2848 pr_info("AMD IOMMU disabled\n"); 2849 init_state = IOMMU_CMDLINE_DISABLED; 2850 ret = -EINVAL; 2851 } 2852 break; 2853 case IOMMU_ACPI_FINISHED: 2854 early_enable_iommus(); 2855 x86_platform.iommu_shutdown = disable_iommus; 2856 init_state = IOMMU_ENABLED; 2857 break; 2858 case IOMMU_ENABLED: 2859 register_syscore_ops(&amd_iommu_syscore_ops); 2860 ret = amd_iommu_init_pci(); 2861 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 2862 enable_iommus_v2(); 2863 break; 2864 case IOMMU_PCI_INIT: 2865 ret = amd_iommu_enable_interrupts(); 2866 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 2867 break; 2868 case IOMMU_INTERRUPTS_EN: 2869 ret = amd_iommu_init_dma_ops(); 2870 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS; 2871 break; 2872 case IOMMU_DMA_OPS: 2873 init_state = IOMMU_INITIALIZED; 2874 break; 2875 case IOMMU_INITIALIZED: 2876 /* Nothing to do */ 2877 break; 2878 case IOMMU_NOT_FOUND: 2879 case IOMMU_INIT_ERROR: 2880 case IOMMU_CMDLINE_DISABLED: 2881 /* Error states => do nothing */ 2882 ret = -EINVAL; 2883 break; 2884 default: 2885 /* Unknown state */ 2886 BUG(); 2887 } 2888 2889 if (ret) { 2890 free_dma_resources(); 2891 if (!irq_remapping_enabled) { 2892 disable_iommus(); 2893 free_iommu_resources(); 2894 } else { 2895 struct amd_iommu *iommu; 2896 2897 uninit_device_table_dma(); 2898 for_each_iommu(iommu) 2899 iommu_flush_all_caches(iommu); 2900 } 2901 } 2902 return ret; 2903 } 2904 2905 static int __init iommu_go_to_state(enum iommu_init_state state) 2906 { 2907 int ret = -EINVAL; 2908 2909 while (init_state != state) { 2910 if (init_state == IOMMU_NOT_FOUND || 2911 init_state == IOMMU_INIT_ERROR || 2912 init_state == IOMMU_CMDLINE_DISABLED) 2913 break; 2914 ret = state_next(); 2915 } 2916 2917 return ret; 2918 } 2919 2920 #ifdef CONFIG_IRQ_REMAP 2921 int __init amd_iommu_prepare(void) 2922 { 2923 int ret; 2924 2925 amd_iommu_irq_remap = true; 2926 2927 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 2928 if (ret) 2929 return ret; 2930 return amd_iommu_irq_remap ? 0 : -ENODEV; 2931 } 2932 2933 int __init amd_iommu_enable(void) 2934 { 2935 int ret; 2936 2937 ret = iommu_go_to_state(IOMMU_ENABLED); 2938 if (ret) 2939 return ret; 2940 2941 irq_remapping_enabled = 1; 2942 return amd_iommu_xt_mode; 2943 } 2944 2945 void amd_iommu_disable(void) 2946 { 2947 amd_iommu_suspend(); 2948 } 2949 2950 int amd_iommu_reenable(int mode) 2951 { 2952 amd_iommu_resume(); 2953 2954 return 0; 2955 } 2956 2957 int __init amd_iommu_enable_faulting(void) 2958 { 2959 /* We enable MSI later when PCI is initialized */ 2960 return 0; 2961 } 2962 #endif 2963 2964 /* 2965 * This is the core init function for AMD IOMMU hardware in the system. 2966 * This function is called from the generic x86 DMA layer initialization 2967 * code. 2968 */ 2969 static int __init amd_iommu_init(void) 2970 { 2971 struct amd_iommu *iommu; 2972 int ret; 2973 2974 ret = iommu_go_to_state(IOMMU_INITIALIZED); 2975 #ifdef CONFIG_GART_IOMMU 2976 if (ret && list_empty(&amd_iommu_list)) { 2977 /* 2978 * We failed to initialize the AMD IOMMU - try fallback 2979 * to GART if possible. 2980 */ 2981 gart_iommu_init(); 2982 } 2983 #endif 2984 2985 for_each_iommu(iommu) 2986 amd_iommu_debugfs_setup(iommu); 2987 2988 return ret; 2989 } 2990 2991 static bool amd_iommu_sme_check(void) 2992 { 2993 if (!sme_active() || (boot_cpu_data.x86 != 0x17)) 2994 return true; 2995 2996 /* For Fam17h, a specific level of support is required */ 2997 if (boot_cpu_data.microcode >= 0x08001205) 2998 return true; 2999 3000 if ((boot_cpu_data.microcode >= 0x08001126) && 3001 (boot_cpu_data.microcode <= 0x080011ff)) 3002 return true; 3003 3004 pr_notice("IOMMU not currently supported when SME is active\n"); 3005 3006 return false; 3007 } 3008 3009 /**************************************************************************** 3010 * 3011 * Early detect code. This code runs at IOMMU detection time in the DMA 3012 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3013 * IOMMUs 3014 * 3015 ****************************************************************************/ 3016 int __init amd_iommu_detect(void) 3017 { 3018 int ret; 3019 3020 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3021 return -ENODEV; 3022 3023 if (!amd_iommu_sme_check()) 3024 return -ENODEV; 3025 3026 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3027 if (ret) 3028 return ret; 3029 3030 amd_iommu_detected = true; 3031 iommu_detected = 1; 3032 x86_init.iommu.iommu_init = amd_iommu_init; 3033 3034 return 1; 3035 } 3036 3037 /**************************************************************************** 3038 * 3039 * Parsing functions for the AMD IOMMU specific kernel command line 3040 * options. 3041 * 3042 ****************************************************************************/ 3043 3044 static int __init parse_amd_iommu_dump(char *str) 3045 { 3046 amd_iommu_dump = true; 3047 3048 return 1; 3049 } 3050 3051 static int __init parse_amd_iommu_intr(char *str) 3052 { 3053 for (; *str; ++str) { 3054 if (strncmp(str, "legacy", 6) == 0) { 3055 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3056 break; 3057 } 3058 if (strncmp(str, "vapic", 5) == 0) { 3059 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3060 break; 3061 } 3062 } 3063 return 1; 3064 } 3065 3066 static int __init parse_amd_iommu_options(char *str) 3067 { 3068 for (; *str; ++str) { 3069 if (strncmp(str, "fullflush", 9) == 0) 3070 amd_iommu_unmap_flush = true; 3071 if (strncmp(str, "off", 3) == 0) 3072 amd_iommu_disabled = true; 3073 if (strncmp(str, "force_isolation", 15) == 0) 3074 amd_iommu_force_isolation = true; 3075 } 3076 3077 return 1; 3078 } 3079 3080 static int __init parse_ivrs_ioapic(char *str) 3081 { 3082 unsigned int bus, dev, fn; 3083 int ret, id, i; 3084 u16 devid; 3085 3086 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3087 3088 if (ret != 4) { 3089 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3090 return 1; 3091 } 3092 3093 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3094 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3095 str); 3096 return 1; 3097 } 3098 3099 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3100 3101 cmdline_maps = true; 3102 i = early_ioapic_map_size++; 3103 early_ioapic_map[i].id = id; 3104 early_ioapic_map[i].devid = devid; 3105 early_ioapic_map[i].cmd_line = true; 3106 3107 return 1; 3108 } 3109 3110 static int __init parse_ivrs_hpet(char *str) 3111 { 3112 unsigned int bus, dev, fn; 3113 int ret, id, i; 3114 u16 devid; 3115 3116 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3117 3118 if (ret != 4) { 3119 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3120 return 1; 3121 } 3122 3123 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3124 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3125 str); 3126 return 1; 3127 } 3128 3129 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3130 3131 cmdline_maps = true; 3132 i = early_hpet_map_size++; 3133 early_hpet_map[i].id = id; 3134 early_hpet_map[i].devid = devid; 3135 early_hpet_map[i].cmd_line = true; 3136 3137 return 1; 3138 } 3139 3140 static int __init parse_ivrs_acpihid(char *str) 3141 { 3142 u32 bus, dev, fn; 3143 char *hid, *uid, *p; 3144 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0}; 3145 int ret, i; 3146 3147 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid); 3148 if (ret != 4) { 3149 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str); 3150 return 1; 3151 } 3152 3153 p = acpiid; 3154 hid = strsep(&p, ":"); 3155 uid = p; 3156 3157 if (!hid || !(*hid) || !uid) { 3158 pr_err("Invalid command line: hid or uid\n"); 3159 return 1; 3160 } 3161 3162 i = early_acpihid_map_size++; 3163 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3164 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3165 early_acpihid_map[i].devid = 3166 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3167 early_acpihid_map[i].cmd_line = true; 3168 3169 return 1; 3170 } 3171 3172 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3173 __setup("amd_iommu=", parse_amd_iommu_options); 3174 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3175 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3176 __setup("ivrs_hpet", parse_ivrs_hpet); 3177 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3178 3179 IOMMU_INIT_FINISH(amd_iommu_detect, 3180 gart_iommu_hole_init, 3181 NULL, 3182 NULL); 3183 3184 bool amd_iommu_v2_supported(void) 3185 { 3186 return amd_iommu_v2_present; 3187 } 3188 EXPORT_SYMBOL(amd_iommu_v2_supported); 3189 3190 struct amd_iommu *get_amd_iommu(unsigned int idx) 3191 { 3192 unsigned int i = 0; 3193 struct amd_iommu *iommu; 3194 3195 for_each_iommu(iommu) 3196 if (i++ == idx) 3197 return iommu; 3198 return NULL; 3199 } 3200 EXPORT_SYMBOL(get_amd_iommu); 3201 3202 /**************************************************************************** 3203 * 3204 * IOMMU EFR Performance Counter support functionality. This code allows 3205 * access to the IOMMU PC functionality. 3206 * 3207 ****************************************************************************/ 3208 3209 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3210 { 3211 struct amd_iommu *iommu = get_amd_iommu(idx); 3212 3213 if (iommu) 3214 return iommu->max_banks; 3215 3216 return 0; 3217 } 3218 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks); 3219 3220 bool amd_iommu_pc_supported(void) 3221 { 3222 return amd_iommu_pc_present; 3223 } 3224 EXPORT_SYMBOL(amd_iommu_pc_supported); 3225 3226 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3227 { 3228 struct amd_iommu *iommu = get_amd_iommu(idx); 3229 3230 if (iommu) 3231 return iommu->max_counters; 3232 3233 return 0; 3234 } 3235 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters); 3236 3237 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3238 u8 fxn, u64 *value, bool is_write) 3239 { 3240 u32 offset; 3241 u32 max_offset_lim; 3242 3243 /* Make sure the IOMMU PC resource is available */ 3244 if (!amd_iommu_pc_present) 3245 return -ENODEV; 3246 3247 /* Check for valid iommu and pc register indexing */ 3248 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3249 return -ENODEV; 3250 3251 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3252 3253 /* Limit the offset to the hw defined mmio region aperture */ 3254 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3255 (iommu->max_counters << 8) | 0x28); 3256 if ((offset < MMIO_CNTR_REG_OFFSET) || 3257 (offset > max_offset_lim)) 3258 return -EINVAL; 3259 3260 if (is_write) { 3261 u64 val = *value & GENMASK_ULL(47, 0); 3262 3263 writel((u32)val, iommu->mmio_base + offset); 3264 writel((val >> 32), iommu->mmio_base + offset + 4); 3265 } else { 3266 *value = readl(iommu->mmio_base + offset + 4); 3267 *value <<= 32; 3268 *value |= readl(iommu->mmio_base + offset); 3269 *value &= GENMASK_ULL(47, 0); 3270 } 3271 3272 return 0; 3273 } 3274 3275 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3276 { 3277 if (!iommu) 3278 return -EINVAL; 3279 3280 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3281 } 3282 EXPORT_SYMBOL(amd_iommu_pc_get_reg); 3283 3284 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3285 { 3286 if (!iommu) 3287 return -EINVAL; 3288 3289 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3290 } 3291 EXPORT_SYMBOL(amd_iommu_pc_set_reg); 3292