1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/delay.h> 16 #include <linux/slab.h> 17 #include <linux/syscore_ops.h> 18 #include <linux/interrupt.h> 19 #include <linux/msi.h> 20 #include <linux/amd-iommu.h> 21 #include <linux/export.h> 22 #include <linux/kmemleak.h> 23 #include <linux/mem_encrypt.h> 24 #include <asm/pci-direct.h> 25 #include <asm/iommu.h> 26 #include <asm/apic.h> 27 #include <asm/msidef.h> 28 #include <asm/gart.h> 29 #include <asm/x86_init.h> 30 #include <asm/iommu_table.h> 31 #include <asm/io_apic.h> 32 #include <asm/irq_remapping.h> 33 #include <asm/set_memory.h> 34 35 #include <linux/crash_dump.h> 36 37 #include "amd_iommu.h" 38 #include "../irq_remapping.h" 39 40 /* 41 * definitions for the ACPI scanning code 42 */ 43 #define IVRS_HEADER_LENGTH 48 44 45 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 46 #define ACPI_IVMD_TYPE_ALL 0x20 47 #define ACPI_IVMD_TYPE 0x21 48 #define ACPI_IVMD_TYPE_RANGE 0x22 49 50 #define IVHD_DEV_ALL 0x01 51 #define IVHD_DEV_SELECT 0x02 52 #define IVHD_DEV_SELECT_RANGE_START 0x03 53 #define IVHD_DEV_RANGE_END 0x04 54 #define IVHD_DEV_ALIAS 0x42 55 #define IVHD_DEV_ALIAS_RANGE 0x43 56 #define IVHD_DEV_EXT_SELECT 0x46 57 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 58 #define IVHD_DEV_SPECIAL 0x48 59 #define IVHD_DEV_ACPI_HID 0xf0 60 61 #define UID_NOT_PRESENT 0 62 #define UID_IS_INTEGER 1 63 #define UID_IS_CHARACTER 2 64 65 #define IVHD_SPECIAL_IOAPIC 1 66 #define IVHD_SPECIAL_HPET 2 67 68 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 69 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 70 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 71 #define IVHD_FLAG_ISOC_EN_MASK 0x08 72 73 #define IVMD_FLAG_EXCL_RANGE 0x08 74 #define IVMD_FLAG_IW 0x04 75 #define IVMD_FLAG_IR 0x02 76 #define IVMD_FLAG_UNITY_MAP 0x01 77 78 #define ACPI_DEVFLAG_INITPASS 0x01 79 #define ACPI_DEVFLAG_EXTINT 0x02 80 #define ACPI_DEVFLAG_NMI 0x04 81 #define ACPI_DEVFLAG_SYSMGT1 0x10 82 #define ACPI_DEVFLAG_SYSMGT2 0x20 83 #define ACPI_DEVFLAG_LINT0 0x40 84 #define ACPI_DEVFLAG_LINT1 0x80 85 #define ACPI_DEVFLAG_ATSDIS 0x10000000 86 87 #define LOOP_TIMEOUT 100000 88 /* 89 * ACPI table definitions 90 * 91 * These data structures are laid over the table to parse the important values 92 * out of it. 93 */ 94 95 extern const struct iommu_ops amd_iommu_ops; 96 97 /* 98 * structure describing one IOMMU in the ACPI table. Typically followed by one 99 * or more ivhd_entrys. 100 */ 101 struct ivhd_header { 102 u8 type; 103 u8 flags; 104 u16 length; 105 u16 devid; 106 u16 cap_ptr; 107 u64 mmio_phys; 108 u16 pci_seg; 109 u16 info; 110 u32 efr_attr; 111 112 /* Following only valid on IVHD type 11h and 40h */ 113 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 114 u64 res; 115 } __attribute__((packed)); 116 117 /* 118 * A device entry describing which devices a specific IOMMU translates and 119 * which requestor ids they use. 120 */ 121 struct ivhd_entry { 122 u8 type; 123 u16 devid; 124 u8 flags; 125 u32 ext; 126 u32 hidh; 127 u64 cid; 128 u8 uidf; 129 u8 uidl; 130 u8 uid; 131 } __attribute__((packed)); 132 133 /* 134 * An AMD IOMMU memory definition structure. It defines things like exclusion 135 * ranges for devices and regions that should be unity mapped. 136 */ 137 struct ivmd_header { 138 u8 type; 139 u8 flags; 140 u16 length; 141 u16 devid; 142 u16 aux; 143 u64 resv; 144 u64 range_start; 145 u64 range_length; 146 } __attribute__((packed)); 147 148 bool amd_iommu_dump; 149 bool amd_iommu_irq_remap __read_mostly; 150 151 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 152 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 153 154 static bool amd_iommu_detected; 155 static bool __initdata amd_iommu_disabled; 156 static int amd_iommu_target_ivhd_type; 157 158 u16 amd_iommu_last_bdf; /* largest PCI device id we have 159 to handle */ 160 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings 161 we find in ACPI */ 162 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ 163 164 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 165 system */ 166 167 /* Array to assign indices to IOMMUs*/ 168 struct amd_iommu *amd_iommus[MAX_IOMMUS]; 169 170 /* Number of IOMMUs present in the system */ 171 static int amd_iommus_present; 172 173 /* IOMMUs have a non-present cache? */ 174 bool amd_iommu_np_cache __read_mostly; 175 bool amd_iommu_iotlb_sup __read_mostly = true; 176 177 u32 amd_iommu_max_pasid __read_mostly = ~0; 178 179 bool amd_iommu_v2_present __read_mostly; 180 static bool amd_iommu_pc_present __read_mostly; 181 182 bool amd_iommu_force_isolation __read_mostly; 183 184 /* 185 * Pointer to the device table which is shared by all AMD IOMMUs 186 * it is indexed by the PCI device id or the HT unit id and contains 187 * information about the domain the device belongs to as well as the 188 * page table root pointer. 189 */ 190 struct dev_table_entry *amd_iommu_dev_table; 191 /* 192 * Pointer to a device table which the content of old device table 193 * will be copied to. It's only be used in kdump kernel. 194 */ 195 static struct dev_table_entry *old_dev_tbl_cpy; 196 197 /* 198 * The alias table is a driver specific data structure which contains the 199 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 200 * More than one device can share the same requestor id. 201 */ 202 u16 *amd_iommu_alias_table; 203 204 /* 205 * The rlookup table is used to find the IOMMU which is responsible 206 * for a specific device. It is also indexed by the PCI device id. 207 */ 208 struct amd_iommu **amd_iommu_rlookup_table; 209 EXPORT_SYMBOL(amd_iommu_rlookup_table); 210 211 /* 212 * This table is used to find the irq remapping table for a given device id 213 * quickly. 214 */ 215 struct irq_remap_table **irq_lookup_table; 216 217 /* 218 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap 219 * to know which ones are already in use. 220 */ 221 unsigned long *amd_iommu_pd_alloc_bitmap; 222 223 static u32 dev_table_size; /* size of the device table */ 224 static u32 alias_table_size; /* size of the alias table */ 225 static u32 rlookup_table_size; /* size if the rlookup table */ 226 227 enum iommu_init_state { 228 IOMMU_START_STATE, 229 IOMMU_IVRS_DETECTED, 230 IOMMU_ACPI_FINISHED, 231 IOMMU_ENABLED, 232 IOMMU_PCI_INIT, 233 IOMMU_INTERRUPTS_EN, 234 IOMMU_DMA_OPS, 235 IOMMU_INITIALIZED, 236 IOMMU_NOT_FOUND, 237 IOMMU_INIT_ERROR, 238 IOMMU_CMDLINE_DISABLED, 239 }; 240 241 /* Early ioapic and hpet maps from kernel command line */ 242 #define EARLY_MAP_SIZE 4 243 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 244 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 245 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 246 247 static int __initdata early_ioapic_map_size; 248 static int __initdata early_hpet_map_size; 249 static int __initdata early_acpihid_map_size; 250 251 static bool __initdata cmdline_maps; 252 253 static enum iommu_init_state init_state = IOMMU_START_STATE; 254 255 static int amd_iommu_enable_interrupts(void); 256 static int __init iommu_go_to_state(enum iommu_init_state state); 257 static void init_device_table_dma(void); 258 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 259 u8 fxn, u64 *value, bool is_write); 260 261 static bool amd_iommu_pre_enabled = true; 262 263 static u32 amd_iommu_ivinfo __initdata; 264 265 bool translation_pre_enabled(struct amd_iommu *iommu) 266 { 267 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 268 } 269 EXPORT_SYMBOL(translation_pre_enabled); 270 271 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 272 { 273 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 274 } 275 276 static void init_translation_status(struct amd_iommu *iommu) 277 { 278 u64 ctrl; 279 280 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 281 if (ctrl & (1<<CONTROL_IOMMU_EN)) 282 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 283 } 284 285 static inline void update_last_devid(u16 devid) 286 { 287 if (devid > amd_iommu_last_bdf) 288 amd_iommu_last_bdf = devid; 289 } 290 291 static inline unsigned long tbl_size(int entry_size) 292 { 293 unsigned shift = PAGE_SHIFT + 294 get_order(((int)amd_iommu_last_bdf + 1) * entry_size); 295 296 return 1UL << shift; 297 } 298 299 int amd_iommu_get_num_iommus(void) 300 { 301 return amd_iommus_present; 302 } 303 304 /* 305 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 306 * Default to IVHD EFR since it is available sooner 307 * (i.e. before PCI init). 308 */ 309 static void __init early_iommu_features_init(struct amd_iommu *iommu, 310 struct ivhd_header *h) 311 { 312 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) 313 iommu->features = h->efr_reg; 314 } 315 316 /* Access to l1 and l2 indexed register spaces */ 317 318 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 319 { 320 u32 val; 321 322 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 323 pci_read_config_dword(iommu->dev, 0xfc, &val); 324 return val; 325 } 326 327 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 328 { 329 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 330 pci_write_config_dword(iommu->dev, 0xfc, val); 331 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 332 } 333 334 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 335 { 336 u32 val; 337 338 pci_write_config_dword(iommu->dev, 0xf0, address); 339 pci_read_config_dword(iommu->dev, 0xf4, &val); 340 return val; 341 } 342 343 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 344 { 345 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 346 pci_write_config_dword(iommu->dev, 0xf4, val); 347 } 348 349 /**************************************************************************** 350 * 351 * AMD IOMMU MMIO register space handling functions 352 * 353 * These functions are used to program the IOMMU device registers in 354 * MMIO space required for that driver. 355 * 356 ****************************************************************************/ 357 358 /* 359 * This function set the exclusion range in the IOMMU. DMA accesses to the 360 * exclusion range are passed through untranslated 361 */ 362 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 363 { 364 u64 start = iommu->exclusion_start & PAGE_MASK; 365 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 366 u64 entry; 367 368 if (!iommu->exclusion_start) 369 return; 370 371 entry = start | MMIO_EXCL_ENABLE_MASK; 372 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 373 &entry, sizeof(entry)); 374 375 entry = limit; 376 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 377 &entry, sizeof(entry)); 378 } 379 380 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 381 { 382 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 383 u64 entry = start & PM_ADDR_MASK; 384 385 if (!iommu_feature(iommu, FEATURE_SNP)) 386 return; 387 388 /* Note: 389 * Re-purpose Exclusion base/limit registers for Completion wait 390 * write-back base/limit. 391 */ 392 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 393 &entry, sizeof(entry)); 394 395 /* Note: 396 * Default to 4 Kbytes, which can be specified by setting base 397 * address equal to the limit address. 398 */ 399 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 400 &entry, sizeof(entry)); 401 } 402 403 /* Programs the physical address of the device table into the IOMMU hardware */ 404 static void iommu_set_device_table(struct amd_iommu *iommu) 405 { 406 u64 entry; 407 408 BUG_ON(iommu->mmio_base == NULL); 409 410 entry = iommu_virt_to_phys(amd_iommu_dev_table); 411 entry |= (dev_table_size >> 12) - 1; 412 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 413 &entry, sizeof(entry)); 414 } 415 416 /* Generic functions to enable/disable certain features of the IOMMU. */ 417 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 418 { 419 u64 ctrl; 420 421 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 422 ctrl |= (1ULL << bit); 423 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 424 } 425 426 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 427 { 428 u64 ctrl; 429 430 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 431 ctrl &= ~(1ULL << bit); 432 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 433 } 434 435 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) 436 { 437 u64 ctrl; 438 439 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 440 ctrl &= ~CTRL_INV_TO_MASK; 441 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; 442 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 443 } 444 445 /* Function to enable the hardware */ 446 static void iommu_enable(struct amd_iommu *iommu) 447 { 448 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 449 } 450 451 static void iommu_disable(struct amd_iommu *iommu) 452 { 453 if (!iommu->mmio_base) 454 return; 455 456 /* Disable command buffer */ 457 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 458 459 /* Disable event logging and event interrupts */ 460 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 461 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 462 463 /* Disable IOMMU GA_LOG */ 464 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 465 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 466 467 /* Disable IOMMU hardware itself */ 468 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 469 } 470 471 /* 472 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 473 * the system has one. 474 */ 475 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 476 { 477 if (!request_mem_region(address, end, "amd_iommu")) { 478 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 479 address, end); 480 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 481 return NULL; 482 } 483 484 return (u8 __iomem *)ioremap(address, end); 485 } 486 487 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 488 { 489 if (iommu->mmio_base) 490 iounmap(iommu->mmio_base); 491 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 492 } 493 494 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 495 { 496 u32 size = 0; 497 498 switch (h->type) { 499 case 0x10: 500 size = 24; 501 break; 502 case 0x11: 503 case 0x40: 504 size = 40; 505 break; 506 } 507 return size; 508 } 509 510 /**************************************************************************** 511 * 512 * The functions below belong to the first pass of AMD IOMMU ACPI table 513 * parsing. In this pass we try to find out the highest device id this 514 * code has to handle. Upon this information the size of the shared data 515 * structures is determined later. 516 * 517 ****************************************************************************/ 518 519 /* 520 * This function calculates the length of a given IVHD entry 521 */ 522 static inline int ivhd_entry_length(u8 *ivhd) 523 { 524 u32 type = ((struct ivhd_entry *)ivhd)->type; 525 526 if (type < 0x80) { 527 return 0x04 << (*ivhd >> 6); 528 } else if (type == IVHD_DEV_ACPI_HID) { 529 /* For ACPI_HID, offset 21 is uid len */ 530 return *((u8 *)ivhd + 21) + 22; 531 } 532 return 0; 533 } 534 535 /* 536 * After reading the highest device id from the IOMMU PCI capability header 537 * this function looks if there is a higher device id defined in the ACPI table 538 */ 539 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 540 { 541 u8 *p = (void *)h, *end = (void *)h; 542 struct ivhd_entry *dev; 543 544 u32 ivhd_size = get_ivhd_header_size(h); 545 546 if (!ivhd_size) { 547 pr_err("Unsupported IVHD type %#x\n", h->type); 548 return -EINVAL; 549 } 550 551 p += ivhd_size; 552 end += h->length; 553 554 while (p < end) { 555 dev = (struct ivhd_entry *)p; 556 switch (dev->type) { 557 case IVHD_DEV_ALL: 558 /* Use maximum BDF value for DEV_ALL */ 559 update_last_devid(0xffff); 560 break; 561 case IVHD_DEV_SELECT: 562 case IVHD_DEV_RANGE_END: 563 case IVHD_DEV_ALIAS: 564 case IVHD_DEV_EXT_SELECT: 565 /* all the above subfield types refer to device ids */ 566 update_last_devid(dev->devid); 567 break; 568 default: 569 break; 570 } 571 p += ivhd_entry_length(p); 572 } 573 574 WARN_ON(p != end); 575 576 return 0; 577 } 578 579 static int __init check_ivrs_checksum(struct acpi_table_header *table) 580 { 581 int i; 582 u8 checksum = 0, *p = (u8 *)table; 583 584 for (i = 0; i < table->length; ++i) 585 checksum += p[i]; 586 if (checksum != 0) { 587 /* ACPI table corrupt */ 588 pr_err(FW_BUG "IVRS invalid checksum\n"); 589 return -ENODEV; 590 } 591 592 return 0; 593 } 594 595 /* 596 * Iterate over all IVHD entries in the ACPI table and find the highest device 597 * id which we need to handle. This is the first of three functions which parse 598 * the ACPI table. So we check the checksum here. 599 */ 600 static int __init find_last_devid_acpi(struct acpi_table_header *table) 601 { 602 u8 *p = (u8 *)table, *end = (u8 *)table; 603 struct ivhd_header *h; 604 605 p += IVRS_HEADER_LENGTH; 606 607 end += table->length; 608 while (p < end) { 609 h = (struct ivhd_header *)p; 610 if (h->type == amd_iommu_target_ivhd_type) { 611 int ret = find_last_devid_from_ivhd(h); 612 613 if (ret) 614 return ret; 615 } 616 p += h->length; 617 } 618 WARN_ON(p != end); 619 620 return 0; 621 } 622 623 /**************************************************************************** 624 * 625 * The following functions belong to the code path which parses the ACPI table 626 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 627 * data structures, initialize the device/alias/rlookup table and also 628 * basically initialize the hardware. 629 * 630 ****************************************************************************/ 631 632 /* 633 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 634 * write commands to that buffer later and the IOMMU will execute them 635 * asynchronously 636 */ 637 static int __init alloc_command_buffer(struct amd_iommu *iommu) 638 { 639 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 640 get_order(CMD_BUFFER_SIZE)); 641 642 return iommu->cmd_buf ? 0 : -ENOMEM; 643 } 644 645 /* 646 * This function resets the command buffer if the IOMMU stopped fetching 647 * commands from it. 648 */ 649 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 650 { 651 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 652 653 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 654 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 655 iommu->cmd_buf_head = 0; 656 iommu->cmd_buf_tail = 0; 657 658 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 659 } 660 661 /* 662 * This function writes the command buffer address to the hardware and 663 * enables it. 664 */ 665 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 666 { 667 u64 entry; 668 669 BUG_ON(iommu->cmd_buf == NULL); 670 671 entry = iommu_virt_to_phys(iommu->cmd_buf); 672 entry |= MMIO_CMD_SIZE_512; 673 674 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 675 &entry, sizeof(entry)); 676 677 amd_iommu_reset_cmd_buffer(iommu); 678 } 679 680 /* 681 * This function disables the command buffer 682 */ 683 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 684 { 685 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 686 } 687 688 static void __init free_command_buffer(struct amd_iommu *iommu) 689 { 690 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); 691 } 692 693 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, 694 gfp_t gfp, size_t size) 695 { 696 int order = get_order(size); 697 void *buf = (void *)__get_free_pages(gfp, order); 698 699 if (buf && 700 iommu_feature(iommu, FEATURE_SNP) && 701 set_memory_4k((unsigned long)buf, (1 << order))) { 702 free_pages((unsigned long)buf, order); 703 buf = NULL; 704 } 705 706 return buf; 707 } 708 709 /* allocates the memory where the IOMMU will log its events to */ 710 static int __init alloc_event_buffer(struct amd_iommu *iommu) 711 { 712 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 713 EVT_BUFFER_SIZE); 714 715 return iommu->evt_buf ? 0 : -ENOMEM; 716 } 717 718 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 719 { 720 u64 entry; 721 722 BUG_ON(iommu->evt_buf == NULL); 723 724 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 725 726 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 727 &entry, sizeof(entry)); 728 729 /* set head and tail to zero manually */ 730 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 731 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 732 733 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 734 } 735 736 /* 737 * This function disables the event log buffer 738 */ 739 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 740 { 741 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 742 } 743 744 static void __init free_event_buffer(struct amd_iommu *iommu) 745 { 746 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); 747 } 748 749 /* allocates the memory where the IOMMU will log its events to */ 750 static int __init alloc_ppr_log(struct amd_iommu *iommu) 751 { 752 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 753 PPR_LOG_SIZE); 754 755 return iommu->ppr_log ? 0 : -ENOMEM; 756 } 757 758 static void iommu_enable_ppr_log(struct amd_iommu *iommu) 759 { 760 u64 entry; 761 762 if (iommu->ppr_log == NULL) 763 return; 764 765 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; 766 767 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, 768 &entry, sizeof(entry)); 769 770 /* set head and tail to zero manually */ 771 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 772 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 773 774 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); 775 iommu_feature_enable(iommu, CONTROL_PPR_EN); 776 } 777 778 static void __init free_ppr_log(struct amd_iommu *iommu) 779 { 780 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); 781 } 782 783 static void free_ga_log(struct amd_iommu *iommu) 784 { 785 #ifdef CONFIG_IRQ_REMAP 786 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); 787 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); 788 #endif 789 } 790 791 static int iommu_ga_log_enable(struct amd_iommu *iommu) 792 { 793 #ifdef CONFIG_IRQ_REMAP 794 u32 status, i; 795 796 if (!iommu->ga_log) 797 return -EINVAL; 798 799 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 800 801 /* Check if already running */ 802 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 803 return 0; 804 805 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 806 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 807 808 for (i = 0; i < LOOP_TIMEOUT; ++i) { 809 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 810 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 811 break; 812 } 813 814 if (i >= LOOP_TIMEOUT) 815 return -EINVAL; 816 #endif /* CONFIG_IRQ_REMAP */ 817 return 0; 818 } 819 820 #ifdef CONFIG_IRQ_REMAP 821 static int iommu_init_ga_log(struct amd_iommu *iommu) 822 { 823 u64 entry; 824 825 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 826 return 0; 827 828 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 829 get_order(GA_LOG_SIZE)); 830 if (!iommu->ga_log) 831 goto err_out; 832 833 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 834 get_order(8)); 835 if (!iommu->ga_log_tail) 836 goto err_out; 837 838 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 839 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 840 &entry, sizeof(entry)); 841 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 842 (BIT_ULL(52)-1)) & ~7ULL; 843 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 844 &entry, sizeof(entry)); 845 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 846 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 847 848 return 0; 849 err_out: 850 free_ga_log(iommu); 851 return -EINVAL; 852 } 853 #endif /* CONFIG_IRQ_REMAP */ 854 855 static int iommu_init_ga(struct amd_iommu *iommu) 856 { 857 int ret = 0; 858 859 #ifdef CONFIG_IRQ_REMAP 860 /* Note: We have already checked GASup from IVRS table. 861 * Now, we need to make sure that GAMSup is set. 862 */ 863 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 864 !iommu_feature(iommu, FEATURE_GAM_VAPIC)) 865 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 866 867 ret = iommu_init_ga_log(iommu); 868 #endif /* CONFIG_IRQ_REMAP */ 869 870 return ret; 871 } 872 873 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 874 { 875 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); 876 877 return iommu->cmd_sem ? 0 : -ENOMEM; 878 } 879 880 static void __init free_cwwb_sem(struct amd_iommu *iommu) 881 { 882 if (iommu->cmd_sem) 883 free_page((unsigned long)iommu->cmd_sem); 884 } 885 886 static void iommu_enable_xt(struct amd_iommu *iommu) 887 { 888 #ifdef CONFIG_IRQ_REMAP 889 /* 890 * XT mode (32-bit APIC destination ID) requires 891 * GA mode (128-bit IRTE support) as a prerequisite. 892 */ 893 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 894 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 895 iommu_feature_enable(iommu, CONTROL_XT_EN); 896 #endif /* CONFIG_IRQ_REMAP */ 897 } 898 899 static void iommu_enable_gt(struct amd_iommu *iommu) 900 { 901 if (!iommu_feature(iommu, FEATURE_GT)) 902 return; 903 904 iommu_feature_enable(iommu, CONTROL_GT_EN); 905 } 906 907 /* sets a specific bit in the device table entry. */ 908 static void set_dev_entry_bit(u16 devid, u8 bit) 909 { 910 int i = (bit >> 6) & 0x03; 911 int _bit = bit & 0x3f; 912 913 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); 914 } 915 916 static int get_dev_entry_bit(u16 devid, u8 bit) 917 { 918 int i = (bit >> 6) & 0x03; 919 int _bit = bit & 0x3f; 920 921 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; 922 } 923 924 925 static bool copy_device_table(void) 926 { 927 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0; 928 struct dev_table_entry *old_devtb = NULL; 929 u32 lo, hi, devid, old_devtb_size; 930 phys_addr_t old_devtb_phys; 931 struct amd_iommu *iommu; 932 u16 dom_id, dte_v, irq_v; 933 gfp_t gfp_flag; 934 u64 tmp; 935 936 if (!amd_iommu_pre_enabled) 937 return false; 938 939 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 940 for_each_iommu(iommu) { 941 /* All IOMMUs should use the same device table with the same size */ 942 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 943 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 944 entry = (((u64) hi) << 32) + lo; 945 if (last_entry && last_entry != entry) { 946 pr_err("IOMMU:%d should use the same dev table as others!\n", 947 iommu->index); 948 return false; 949 } 950 last_entry = entry; 951 952 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 953 if (old_devtb_size != dev_table_size) { 954 pr_err("The device table size of IOMMU:%d is not expected!\n", 955 iommu->index); 956 return false; 957 } 958 } 959 960 /* 961 * When SME is enabled in the first kernel, the entry includes the 962 * memory encryption mask(sme_me_mask), we must remove the memory 963 * encryption mask to obtain the true physical address in kdump kernel. 964 */ 965 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 966 967 if (old_devtb_phys >= 0x100000000ULL) { 968 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 969 return false; 970 } 971 old_devtb = (sme_active() && is_kdump_kernel()) 972 ? (__force void *)ioremap_encrypted(old_devtb_phys, 973 dev_table_size) 974 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB); 975 976 if (!old_devtb) 977 return false; 978 979 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32; 980 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag, 981 get_order(dev_table_size)); 982 if (old_dev_tbl_cpy == NULL) { 983 pr_err("Failed to allocate memory for copying old device table!\n"); 984 return false; 985 } 986 987 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 988 old_dev_tbl_cpy[devid] = old_devtb[devid]; 989 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 990 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 991 992 if (dte_v && dom_id) { 993 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 994 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 995 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap); 996 /* If gcr3 table existed, mask it out */ 997 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 998 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 999 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 1000 old_dev_tbl_cpy[devid].data[1] &= ~tmp; 1001 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; 1002 tmp |= DTE_FLAG_GV; 1003 old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1004 } 1005 } 1006 1007 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1008 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1009 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK; 1010 if (irq_v && (int_ctl || int_tab_len)) { 1011 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1012 (int_tab_len != DTE_IRQ_TABLE_LEN)) { 1013 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1014 return false; 1015 } 1016 1017 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1018 } 1019 } 1020 memunmap(old_devtb); 1021 1022 return true; 1023 } 1024 1025 void amd_iommu_apply_erratum_63(u16 devid) 1026 { 1027 int sysmgt; 1028 1029 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | 1030 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); 1031 1032 if (sysmgt == 0x01) 1033 set_dev_entry_bit(devid, DEV_ENTRY_IW); 1034 } 1035 1036 /* Writes the specific IOMMU for a device into the rlookup table */ 1037 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) 1038 { 1039 amd_iommu_rlookup_table[devid] = iommu; 1040 } 1041 1042 /* 1043 * This function takes the device specific flags read from the ACPI 1044 * table and sets up the device table entry with that information 1045 */ 1046 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1047 u16 devid, u32 flags, u32 ext_flags) 1048 { 1049 if (flags & ACPI_DEVFLAG_INITPASS) 1050 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); 1051 if (flags & ACPI_DEVFLAG_EXTINT) 1052 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); 1053 if (flags & ACPI_DEVFLAG_NMI) 1054 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); 1055 if (flags & ACPI_DEVFLAG_SYSMGT1) 1056 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); 1057 if (flags & ACPI_DEVFLAG_SYSMGT2) 1058 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); 1059 if (flags & ACPI_DEVFLAG_LINT0) 1060 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); 1061 if (flags & ACPI_DEVFLAG_LINT1) 1062 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); 1063 1064 amd_iommu_apply_erratum_63(devid); 1065 1066 set_iommu_for_device(iommu, devid); 1067 } 1068 1069 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line) 1070 { 1071 struct devid_map *entry; 1072 struct list_head *list; 1073 1074 if (type == IVHD_SPECIAL_IOAPIC) 1075 list = &ioapic_map; 1076 else if (type == IVHD_SPECIAL_HPET) 1077 list = &hpet_map; 1078 else 1079 return -EINVAL; 1080 1081 list_for_each_entry(entry, list, list) { 1082 if (!(entry->id == id && entry->cmd_line)) 1083 continue; 1084 1085 pr_info("Command-line override present for %s id %d - ignoring\n", 1086 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1087 1088 *devid = entry->devid; 1089 1090 return 0; 1091 } 1092 1093 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1094 if (!entry) 1095 return -ENOMEM; 1096 1097 entry->id = id; 1098 entry->devid = *devid; 1099 entry->cmd_line = cmd_line; 1100 1101 list_add_tail(&entry->list, list); 1102 1103 return 0; 1104 } 1105 1106 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid, 1107 bool cmd_line) 1108 { 1109 struct acpihid_map_entry *entry; 1110 struct list_head *list = &acpihid_map; 1111 1112 list_for_each_entry(entry, list, list) { 1113 if (strcmp(entry->hid, hid) || 1114 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1115 !entry->cmd_line) 1116 continue; 1117 1118 pr_info("Command-line override for hid:%s uid:%s\n", 1119 hid, uid); 1120 *devid = entry->devid; 1121 return 0; 1122 } 1123 1124 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1125 if (!entry) 1126 return -ENOMEM; 1127 1128 memcpy(entry->uid, uid, strlen(uid)); 1129 memcpy(entry->hid, hid, strlen(hid)); 1130 entry->devid = *devid; 1131 entry->cmd_line = cmd_line; 1132 entry->root_devid = (entry->devid & (~0x7)); 1133 1134 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n", 1135 entry->cmd_line ? "cmd" : "ivrs", 1136 entry->hid, entry->uid, entry->root_devid); 1137 1138 list_add_tail(&entry->list, list); 1139 return 0; 1140 } 1141 1142 static int __init add_early_maps(void) 1143 { 1144 int i, ret; 1145 1146 for (i = 0; i < early_ioapic_map_size; ++i) { 1147 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1148 early_ioapic_map[i].id, 1149 &early_ioapic_map[i].devid, 1150 early_ioapic_map[i].cmd_line); 1151 if (ret) 1152 return ret; 1153 } 1154 1155 for (i = 0; i < early_hpet_map_size; ++i) { 1156 ret = add_special_device(IVHD_SPECIAL_HPET, 1157 early_hpet_map[i].id, 1158 &early_hpet_map[i].devid, 1159 early_hpet_map[i].cmd_line); 1160 if (ret) 1161 return ret; 1162 } 1163 1164 for (i = 0; i < early_acpihid_map_size; ++i) { 1165 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1166 early_acpihid_map[i].uid, 1167 &early_acpihid_map[i].devid, 1168 early_acpihid_map[i].cmd_line); 1169 if (ret) 1170 return ret; 1171 } 1172 1173 return 0; 1174 } 1175 1176 /* 1177 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1178 * initializes the hardware and our data structures with it. 1179 */ 1180 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1181 struct ivhd_header *h) 1182 { 1183 u8 *p = (u8 *)h; 1184 u8 *end = p, flags = 0; 1185 u16 devid = 0, devid_start = 0, devid_to = 0; 1186 u32 dev_i, ext_flags = 0; 1187 bool alias = false; 1188 struct ivhd_entry *e; 1189 u32 ivhd_size; 1190 int ret; 1191 1192 1193 ret = add_early_maps(); 1194 if (ret) 1195 return ret; 1196 1197 amd_iommu_apply_ivrs_quirks(); 1198 1199 /* 1200 * First save the recommended feature enable bits from ACPI 1201 */ 1202 iommu->acpi_flags = h->flags; 1203 1204 /* 1205 * Done. Now parse the device entries 1206 */ 1207 ivhd_size = get_ivhd_header_size(h); 1208 if (!ivhd_size) { 1209 pr_err("Unsupported IVHD type %#x\n", h->type); 1210 return -EINVAL; 1211 } 1212 1213 p += ivhd_size; 1214 1215 end += h->length; 1216 1217 1218 while (p < end) { 1219 e = (struct ivhd_entry *)p; 1220 switch (e->type) { 1221 case IVHD_DEV_ALL: 1222 1223 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); 1224 1225 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i) 1226 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); 1227 break; 1228 case IVHD_DEV_SELECT: 1229 1230 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " 1231 "flags: %02x\n", 1232 PCI_BUS_NUM(e->devid), 1233 PCI_SLOT(e->devid), 1234 PCI_FUNC(e->devid), 1235 e->flags); 1236 1237 devid = e->devid; 1238 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1239 break; 1240 case IVHD_DEV_SELECT_RANGE_START: 1241 1242 DUMP_printk(" DEV_SELECT_RANGE_START\t " 1243 "devid: %02x:%02x.%x flags: %02x\n", 1244 PCI_BUS_NUM(e->devid), 1245 PCI_SLOT(e->devid), 1246 PCI_FUNC(e->devid), 1247 e->flags); 1248 1249 devid_start = e->devid; 1250 flags = e->flags; 1251 ext_flags = 0; 1252 alias = false; 1253 break; 1254 case IVHD_DEV_ALIAS: 1255 1256 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " 1257 "flags: %02x devid_to: %02x:%02x.%x\n", 1258 PCI_BUS_NUM(e->devid), 1259 PCI_SLOT(e->devid), 1260 PCI_FUNC(e->devid), 1261 e->flags, 1262 PCI_BUS_NUM(e->ext >> 8), 1263 PCI_SLOT(e->ext >> 8), 1264 PCI_FUNC(e->ext >> 8)); 1265 1266 devid = e->devid; 1267 devid_to = e->ext >> 8; 1268 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1269 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1270 amd_iommu_alias_table[devid] = devid_to; 1271 break; 1272 case IVHD_DEV_ALIAS_RANGE: 1273 1274 DUMP_printk(" DEV_ALIAS_RANGE\t\t " 1275 "devid: %02x:%02x.%x flags: %02x " 1276 "devid_to: %02x:%02x.%x\n", 1277 PCI_BUS_NUM(e->devid), 1278 PCI_SLOT(e->devid), 1279 PCI_FUNC(e->devid), 1280 e->flags, 1281 PCI_BUS_NUM(e->ext >> 8), 1282 PCI_SLOT(e->ext >> 8), 1283 PCI_FUNC(e->ext >> 8)); 1284 1285 devid_start = e->devid; 1286 flags = e->flags; 1287 devid_to = e->ext >> 8; 1288 ext_flags = 0; 1289 alias = true; 1290 break; 1291 case IVHD_DEV_EXT_SELECT: 1292 1293 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " 1294 "flags: %02x ext: %08x\n", 1295 PCI_BUS_NUM(e->devid), 1296 PCI_SLOT(e->devid), 1297 PCI_FUNC(e->devid), 1298 e->flags, e->ext); 1299 1300 devid = e->devid; 1301 set_dev_entry_from_acpi(iommu, devid, e->flags, 1302 e->ext); 1303 break; 1304 case IVHD_DEV_EXT_SELECT_RANGE: 1305 1306 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " 1307 "%02x:%02x.%x flags: %02x ext: %08x\n", 1308 PCI_BUS_NUM(e->devid), 1309 PCI_SLOT(e->devid), 1310 PCI_FUNC(e->devid), 1311 e->flags, e->ext); 1312 1313 devid_start = e->devid; 1314 flags = e->flags; 1315 ext_flags = e->ext; 1316 alias = false; 1317 break; 1318 case IVHD_DEV_RANGE_END: 1319 1320 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", 1321 PCI_BUS_NUM(e->devid), 1322 PCI_SLOT(e->devid), 1323 PCI_FUNC(e->devid)); 1324 1325 devid = e->devid; 1326 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1327 if (alias) { 1328 amd_iommu_alias_table[dev_i] = devid_to; 1329 set_dev_entry_from_acpi(iommu, 1330 devid_to, flags, ext_flags); 1331 } 1332 set_dev_entry_from_acpi(iommu, dev_i, 1333 flags, ext_flags); 1334 } 1335 break; 1336 case IVHD_DEV_SPECIAL: { 1337 u8 handle, type; 1338 const char *var; 1339 u16 devid; 1340 int ret; 1341 1342 handle = e->ext & 0xff; 1343 devid = (e->ext >> 8) & 0xffff; 1344 type = (e->ext >> 24) & 0xff; 1345 1346 if (type == IVHD_SPECIAL_IOAPIC) 1347 var = "IOAPIC"; 1348 else if (type == IVHD_SPECIAL_HPET) 1349 var = "HPET"; 1350 else 1351 var = "UNKNOWN"; 1352 1353 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", 1354 var, (int)handle, 1355 PCI_BUS_NUM(devid), 1356 PCI_SLOT(devid), 1357 PCI_FUNC(devid)); 1358 1359 ret = add_special_device(type, handle, &devid, false); 1360 if (ret) 1361 return ret; 1362 1363 /* 1364 * add_special_device might update the devid in case a 1365 * command-line override is present. So call 1366 * set_dev_entry_from_acpi after add_special_device. 1367 */ 1368 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1369 1370 break; 1371 } 1372 case IVHD_DEV_ACPI_HID: { 1373 u16 devid; 1374 u8 hid[ACPIHID_HID_LEN]; 1375 u8 uid[ACPIHID_UID_LEN]; 1376 int ret; 1377 1378 if (h->type != 0x40) { 1379 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1380 e->type); 1381 break; 1382 } 1383 1384 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1); 1385 hid[ACPIHID_HID_LEN - 1] = '\0'; 1386 1387 if (!(*hid)) { 1388 pr_err(FW_BUG "Invalid HID.\n"); 1389 break; 1390 } 1391 1392 uid[0] = '\0'; 1393 switch (e->uidf) { 1394 case UID_NOT_PRESENT: 1395 1396 if (e->uidl != 0) 1397 pr_warn(FW_BUG "Invalid UID length.\n"); 1398 1399 break; 1400 case UID_IS_INTEGER: 1401 1402 sprintf(uid, "%d", e->uid); 1403 1404 break; 1405 case UID_IS_CHARACTER: 1406 1407 memcpy(uid, &e->uid, e->uidl); 1408 uid[e->uidl] = '\0'; 1409 1410 break; 1411 default: 1412 break; 1413 } 1414 1415 devid = e->devid; 1416 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n", 1417 hid, uid, 1418 PCI_BUS_NUM(devid), 1419 PCI_SLOT(devid), 1420 PCI_FUNC(devid)); 1421 1422 flags = e->flags; 1423 1424 ret = add_acpi_hid_device(hid, uid, &devid, false); 1425 if (ret) 1426 return ret; 1427 1428 /* 1429 * add_special_device might update the devid in case a 1430 * command-line override is present. So call 1431 * set_dev_entry_from_acpi after add_special_device. 1432 */ 1433 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1434 1435 break; 1436 } 1437 default: 1438 break; 1439 } 1440 1441 p += ivhd_entry_length(p); 1442 } 1443 1444 return 0; 1445 } 1446 1447 static void __init free_iommu_one(struct amd_iommu *iommu) 1448 { 1449 free_cwwb_sem(iommu); 1450 free_command_buffer(iommu); 1451 free_event_buffer(iommu); 1452 free_ppr_log(iommu); 1453 free_ga_log(iommu); 1454 iommu_unmap_mmio_space(iommu); 1455 } 1456 1457 static void __init free_iommu_all(void) 1458 { 1459 struct amd_iommu *iommu, *next; 1460 1461 for_each_iommu_safe(iommu, next) { 1462 list_del(&iommu->list); 1463 free_iommu_one(iommu); 1464 kfree(iommu); 1465 } 1466 } 1467 1468 /* 1469 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1470 * Workaround: 1471 * BIOS should disable L2B micellaneous clock gating by setting 1472 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1473 */ 1474 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1475 { 1476 u32 value; 1477 1478 if ((boot_cpu_data.x86 != 0x15) || 1479 (boot_cpu_data.x86_model < 0x10) || 1480 (boot_cpu_data.x86_model > 0x1f)) 1481 return; 1482 1483 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1484 pci_read_config_dword(iommu->dev, 0xf4, &value); 1485 1486 if (value & BIT(2)) 1487 return; 1488 1489 /* Select NB indirect register 0x90 and enable writing */ 1490 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1491 1492 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1493 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1494 1495 /* Clear the enable writing bit */ 1496 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1497 } 1498 1499 /* 1500 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1501 * Workaround: 1502 * BIOS should enable ATS write permission check by setting 1503 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1504 */ 1505 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1506 { 1507 u32 value; 1508 1509 if ((boot_cpu_data.x86 != 0x15) || 1510 (boot_cpu_data.x86_model < 0x30) || 1511 (boot_cpu_data.x86_model > 0x3f)) 1512 return; 1513 1514 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1515 value = iommu_read_l2(iommu, 0x47); 1516 1517 if (value & BIT(0)) 1518 return; 1519 1520 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1521 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1522 1523 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1524 } 1525 1526 /* 1527 * This function clues the initialization function for one IOMMU 1528 * together and also allocates the command buffer and programs the 1529 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1530 */ 1531 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) 1532 { 1533 int ret; 1534 1535 raw_spin_lock_init(&iommu->lock); 1536 iommu->cmd_sem_val = 0; 1537 1538 /* Add IOMMU to internal data structures */ 1539 list_add_tail(&iommu->list, &amd_iommu_list); 1540 iommu->index = amd_iommus_present++; 1541 1542 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1543 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1544 return -ENOSYS; 1545 } 1546 1547 /* Index is fine - add IOMMU to the array */ 1548 amd_iommus[iommu->index] = iommu; 1549 1550 /* 1551 * Copy data from ACPI table entry to the iommu struct 1552 */ 1553 iommu->devid = h->devid; 1554 iommu->cap_ptr = h->cap_ptr; 1555 iommu->pci_seg = h->pci_seg; 1556 iommu->mmio_phys = h->mmio_phys; 1557 1558 switch (h->type) { 1559 case 0x10: 1560 /* Check if IVHD EFR contains proper max banks/counters */ 1561 if ((h->efr_attr != 0) && 1562 ((h->efr_attr & (0xF << 13)) != 0) && 1563 ((h->efr_attr & (0x3F << 17)) != 0)) 1564 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1565 else 1566 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1567 1568 /* 1569 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1570 * GAM also requires GA mode. Therefore, we need to 1571 * check cmpxchg16b support before enabling it. 1572 */ 1573 if (!boot_cpu_has(X86_FEATURE_CX16) || 1574 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) 1575 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1576 break; 1577 case 0x11: 1578 case 0x40: 1579 if (h->efr_reg & (1 << 9)) 1580 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1581 else 1582 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1583 1584 /* 1585 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1586 * XT, GAM also requires GA mode. Therefore, we need to 1587 * check cmpxchg16b support before enabling them. 1588 */ 1589 if (!boot_cpu_has(X86_FEATURE_CX16) || 1590 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) { 1591 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1592 break; 1593 } 1594 1595 /* 1596 * Note: Since iommu_update_intcapxt() leverages 1597 * the IOMMU MMIO access to MSI capability block registers 1598 * for MSI address lo/hi/data, we need to check both 1599 * EFR[XtSup] and EFR[MsiCapMmioSup] for x2APIC support. 1600 */ 1601 if ((h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) && 1602 (h->efr_reg & BIT(IOMMU_EFR_MSICAPMMIOSUP_SHIFT))) 1603 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1604 1605 early_iommu_features_init(iommu, h); 1606 1607 break; 1608 default: 1609 return -EINVAL; 1610 } 1611 1612 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1613 iommu->mmio_phys_end); 1614 if (!iommu->mmio_base) 1615 return -ENOMEM; 1616 1617 if (alloc_cwwb_sem(iommu)) 1618 return -ENOMEM; 1619 1620 if (alloc_command_buffer(iommu)) 1621 return -ENOMEM; 1622 1623 if (alloc_event_buffer(iommu)) 1624 return -ENOMEM; 1625 1626 iommu->int_enabled = false; 1627 1628 init_translation_status(iommu); 1629 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1630 iommu_disable(iommu); 1631 clear_translation_pre_enabled(iommu); 1632 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1633 iommu->index); 1634 } 1635 if (amd_iommu_pre_enabled) 1636 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1637 1638 ret = init_iommu_from_acpi(iommu, h); 1639 if (ret) 1640 return ret; 1641 1642 ret = amd_iommu_create_irq_domain(iommu); 1643 if (ret) 1644 return ret; 1645 1646 /* 1647 * Make sure IOMMU is not considered to translate itself. The IVRS 1648 * table tells us so, but this is a lie! 1649 */ 1650 amd_iommu_rlookup_table[iommu->devid] = NULL; 1651 1652 return 0; 1653 } 1654 1655 /** 1656 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1657 * @ivrs: Pointer to the IVRS header 1658 * 1659 * This function search through all IVDB of the maximum supported IVHD 1660 */ 1661 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1662 { 1663 u8 *base = (u8 *)ivrs; 1664 struct ivhd_header *ivhd = (struct ivhd_header *) 1665 (base + IVRS_HEADER_LENGTH); 1666 u8 last_type = ivhd->type; 1667 u16 devid = ivhd->devid; 1668 1669 while (((u8 *)ivhd - base < ivrs->length) && 1670 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1671 u8 *p = (u8 *) ivhd; 1672 1673 if (ivhd->devid == devid) 1674 last_type = ivhd->type; 1675 ivhd = (struct ivhd_header *)(p + ivhd->length); 1676 } 1677 1678 return last_type; 1679 } 1680 1681 /* 1682 * Iterates over all IOMMU entries in the ACPI table, allocates the 1683 * IOMMU structure and initializes it with init_iommu_one() 1684 */ 1685 static int __init init_iommu_all(struct acpi_table_header *table) 1686 { 1687 u8 *p = (u8 *)table, *end = (u8 *)table; 1688 struct ivhd_header *h; 1689 struct amd_iommu *iommu; 1690 int ret; 1691 1692 end += table->length; 1693 p += IVRS_HEADER_LENGTH; 1694 1695 while (p < end) { 1696 h = (struct ivhd_header *)p; 1697 if (*p == amd_iommu_target_ivhd_type) { 1698 1699 DUMP_printk("device: %02x:%02x.%01x cap: %04x " 1700 "seg: %d flags: %01x info %04x\n", 1701 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid), 1702 PCI_FUNC(h->devid), h->cap_ptr, 1703 h->pci_seg, h->flags, h->info); 1704 DUMP_printk(" mmio-addr: %016llx\n", 1705 h->mmio_phys); 1706 1707 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1708 if (iommu == NULL) 1709 return -ENOMEM; 1710 1711 ret = init_iommu_one(iommu, h); 1712 if (ret) 1713 return ret; 1714 } 1715 p += h->length; 1716 1717 } 1718 WARN_ON(p != end); 1719 1720 return 0; 1721 } 1722 1723 static void __init init_iommu_perf_ctr(struct amd_iommu *iommu) 1724 { 1725 int retry; 1726 struct pci_dev *pdev = iommu->dev; 1727 u64 val = 0xabcd, val2 = 0, save_reg, save_src; 1728 1729 if (!iommu_feature(iommu, FEATURE_PC)) 1730 return; 1731 1732 amd_iommu_pc_present = true; 1733 1734 /* save the value to restore, if writable */ 1735 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false) || 1736 iommu_pc_get_set_reg(iommu, 0, 0, 8, &save_src, false)) 1737 goto pc_false; 1738 1739 /* 1740 * Disable power gating by programing the performance counter 1741 * source to 20 (i.e. counts the reads and writes from/to IOMMU 1742 * Reserved Register [MMIO Offset 1FF8h] that are ignored.), 1743 * which never get incremented during this init phase. 1744 * (Note: The event is also deprecated.) 1745 */ 1746 val = 20; 1747 if (iommu_pc_get_set_reg(iommu, 0, 0, 8, &val, true)) 1748 goto pc_false; 1749 1750 /* Check if the performance counters can be written to */ 1751 val = 0xabcd; 1752 for (retry = 5; retry; retry--) { 1753 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true) || 1754 iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false) || 1755 val2) 1756 break; 1757 1758 /* Wait about 20 msec for power gating to disable and retry. */ 1759 msleep(20); 1760 } 1761 1762 /* restore */ 1763 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true) || 1764 iommu_pc_get_set_reg(iommu, 0, 0, 8, &save_src, true)) 1765 goto pc_false; 1766 1767 if (val != val2) 1768 goto pc_false; 1769 1770 pci_info(pdev, "IOMMU performance counters supported\n"); 1771 1772 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1773 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1774 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1775 1776 return; 1777 1778 pc_false: 1779 pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n"); 1780 amd_iommu_pc_present = false; 1781 return; 1782 } 1783 1784 static ssize_t amd_iommu_show_cap(struct device *dev, 1785 struct device_attribute *attr, 1786 char *buf) 1787 { 1788 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1789 return sprintf(buf, "%x\n", iommu->cap); 1790 } 1791 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1792 1793 static ssize_t amd_iommu_show_features(struct device *dev, 1794 struct device_attribute *attr, 1795 char *buf) 1796 { 1797 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1798 return sprintf(buf, "%llx\n", iommu->features); 1799 } 1800 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1801 1802 static struct attribute *amd_iommu_attrs[] = { 1803 &dev_attr_cap.attr, 1804 &dev_attr_features.attr, 1805 NULL, 1806 }; 1807 1808 static struct attribute_group amd_iommu_group = { 1809 .name = "amd-iommu", 1810 .attrs = amd_iommu_attrs, 1811 }; 1812 1813 static const struct attribute_group *amd_iommu_groups[] = { 1814 &amd_iommu_group, 1815 NULL, 1816 }; 1817 1818 /* 1819 * Note: IVHD 0x11 and 0x40 also contains exact copy 1820 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1821 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1822 */ 1823 static void __init late_iommu_features_init(struct amd_iommu *iommu) 1824 { 1825 u64 features; 1826 1827 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 1828 return; 1829 1830 /* read extended feature bits */ 1831 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1832 1833 if (!iommu->features) { 1834 iommu->features = features; 1835 return; 1836 } 1837 1838 /* 1839 * Sanity check and warn if EFR values from 1840 * IVHD and MMIO conflict. 1841 */ 1842 if (features != iommu->features) 1843 pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx).\n", 1844 features, iommu->features); 1845 } 1846 1847 static int __init iommu_init_pci(struct amd_iommu *iommu) 1848 { 1849 int cap_ptr = iommu->cap_ptr; 1850 int ret; 1851 1852 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), 1853 iommu->devid & 0xff); 1854 if (!iommu->dev) 1855 return -ENODEV; 1856 1857 /* Prevent binding other PCI device drivers to IOMMU devices */ 1858 iommu->dev->match_driver = false; 1859 1860 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 1861 &iommu->cap); 1862 1863 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 1864 amd_iommu_iotlb_sup = false; 1865 1866 late_iommu_features_init(iommu); 1867 1868 if (iommu_feature(iommu, FEATURE_GT)) { 1869 int glxval; 1870 u32 max_pasid; 1871 u64 pasmax; 1872 1873 pasmax = iommu->features & FEATURE_PASID_MASK; 1874 pasmax >>= FEATURE_PASID_SHIFT; 1875 max_pasid = (1 << (pasmax + 1)) - 1; 1876 1877 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); 1878 1879 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); 1880 1881 glxval = iommu->features & FEATURE_GLXVAL_MASK; 1882 glxval >>= FEATURE_GLXVAL_SHIFT; 1883 1884 if (amd_iommu_max_glx_val == -1) 1885 amd_iommu_max_glx_val = glxval; 1886 else 1887 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 1888 } 1889 1890 if (iommu_feature(iommu, FEATURE_GT) && 1891 iommu_feature(iommu, FEATURE_PPR)) { 1892 iommu->is_iommu_v2 = true; 1893 amd_iommu_v2_present = true; 1894 } 1895 1896 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) 1897 return -ENOMEM; 1898 1899 ret = iommu_init_ga(iommu); 1900 if (ret) 1901 return ret; 1902 1903 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) 1904 amd_iommu_np_cache = true; 1905 1906 init_iommu_perf_ctr(iommu); 1907 1908 if (is_rd890_iommu(iommu->dev)) { 1909 int i, j; 1910 1911 iommu->root_pdev = 1912 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, 1913 PCI_DEVFN(0, 0)); 1914 1915 /* 1916 * Some rd890 systems may not be fully reconfigured by the 1917 * BIOS, so it's necessary for us to store this information so 1918 * it can be reprogrammed on resume 1919 */ 1920 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 1921 &iommu->stored_addr_lo); 1922 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 1923 &iommu->stored_addr_hi); 1924 1925 /* Low bit locks writes to configuration space */ 1926 iommu->stored_addr_lo &= ~1; 1927 1928 for (i = 0; i < 6; i++) 1929 for (j = 0; j < 0x12; j++) 1930 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 1931 1932 for (i = 0; i < 0x83; i++) 1933 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 1934 } 1935 1936 amd_iommu_erratum_746_workaround(iommu); 1937 amd_iommu_ats_write_check_workaround(iommu); 1938 1939 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 1940 amd_iommu_groups, "ivhd%d", iommu->index); 1941 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops); 1942 iommu_device_register(&iommu->iommu); 1943 1944 return pci_enable_device(iommu->dev); 1945 } 1946 1947 static void print_iommu_info(void) 1948 { 1949 static const char * const feat_str[] = { 1950 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 1951 "IA", "GA", "HE", "PC" 1952 }; 1953 struct amd_iommu *iommu; 1954 1955 for_each_iommu(iommu) { 1956 struct pci_dev *pdev = iommu->dev; 1957 int i; 1958 1959 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr); 1960 1961 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { 1962 pci_info(pdev, "Extended features (%#llx):", 1963 iommu->features); 1964 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 1965 if (iommu_feature(iommu, (1ULL << i))) 1966 pr_cont(" %s", feat_str[i]); 1967 } 1968 1969 if (iommu->features & FEATURE_GAM_VAPIC) 1970 pr_cont(" GA_vAPIC"); 1971 1972 pr_cont("\n"); 1973 } 1974 } 1975 if (irq_remapping_enabled) { 1976 pr_info("Interrupt remapping enabled\n"); 1977 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 1978 pr_info("Virtual APIC enabled\n"); 1979 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 1980 pr_info("X2APIC enabled\n"); 1981 } 1982 } 1983 1984 static int __init amd_iommu_init_pci(void) 1985 { 1986 struct amd_iommu *iommu; 1987 int ret = 0; 1988 1989 for_each_iommu(iommu) { 1990 ret = iommu_init_pci(iommu); 1991 if (ret) 1992 break; 1993 1994 /* Need to setup range after PCI init */ 1995 iommu_set_cwwb_range(iommu); 1996 } 1997 1998 /* 1999 * Order is important here to make sure any unity map requirements are 2000 * fulfilled. The unity mappings are created and written to the device 2001 * table during the amd_iommu_init_api() call. 2002 * 2003 * After that we call init_device_table_dma() to make sure any 2004 * uninitialized DTE will block DMA, and in the end we flush the caches 2005 * of all IOMMUs to make sure the changes to the device table are 2006 * active. 2007 */ 2008 ret = amd_iommu_init_api(); 2009 2010 init_device_table_dma(); 2011 2012 for_each_iommu(iommu) 2013 iommu_flush_all_caches(iommu); 2014 2015 if (!ret) 2016 print_iommu_info(); 2017 2018 return ret; 2019 } 2020 2021 /**************************************************************************** 2022 * 2023 * The following functions initialize the MSI interrupts for all IOMMUs 2024 * in the system. It's a bit challenging because there could be multiple 2025 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2026 * pci_dev. 2027 * 2028 ****************************************************************************/ 2029 2030 static int iommu_setup_msi(struct amd_iommu *iommu) 2031 { 2032 int r; 2033 2034 r = pci_enable_msi(iommu->dev); 2035 if (r) 2036 return r; 2037 2038 r = request_threaded_irq(iommu->dev->irq, 2039 amd_iommu_int_handler, 2040 amd_iommu_int_thread, 2041 0, "AMD-Vi", 2042 iommu); 2043 2044 if (r) { 2045 pci_disable_msi(iommu->dev); 2046 return r; 2047 } 2048 2049 iommu->int_enabled = true; 2050 2051 return 0; 2052 } 2053 2054 #define XT_INT_DEST_MODE(x) (((x) & 0x1ULL) << 2) 2055 #define XT_INT_DEST_LO(x) (((x) & 0xFFFFFFULL) << 8) 2056 #define XT_INT_VEC(x) (((x) & 0xFFULL) << 32) 2057 #define XT_INT_DEST_HI(x) ((((x) >> 24) & 0xFFULL) << 56) 2058 2059 /* 2060 * Setup the IntCapXT registers with interrupt routing information 2061 * based on the PCI MSI capability block registers, accessed via 2062 * MMIO MSI address low/hi and MSI data registers. 2063 */ 2064 static void iommu_update_intcapxt(struct amd_iommu *iommu) 2065 { 2066 u64 val; 2067 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET); 2068 u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET); 2069 u32 data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET); 2070 bool dm = (addr_lo >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; 2071 u32 dest = ((addr_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xFF); 2072 2073 if (x2apic_enabled()) 2074 dest |= MSI_ADDR_EXT_DEST_ID(addr_hi); 2075 2076 val = XT_INT_VEC(data & 0xFF) | 2077 XT_INT_DEST_MODE(dm) | 2078 XT_INT_DEST_LO(dest) | 2079 XT_INT_DEST_HI(dest); 2080 2081 /** 2082 * Current IOMMU implemtation uses the same IRQ for all 2083 * 3 IOMMU interrupts. 2084 */ 2085 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2086 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2087 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2088 } 2089 2090 static void _irq_notifier_notify(struct irq_affinity_notify *notify, 2091 const cpumask_t *mask) 2092 { 2093 struct amd_iommu *iommu; 2094 2095 for_each_iommu(iommu) { 2096 if (iommu->dev->irq == notify->irq) { 2097 iommu_update_intcapxt(iommu); 2098 break; 2099 } 2100 } 2101 } 2102 2103 static void _irq_notifier_release(struct kref *ref) 2104 { 2105 } 2106 2107 static int iommu_init_intcapxt(struct amd_iommu *iommu) 2108 { 2109 int ret; 2110 struct irq_affinity_notify *notify = &iommu->intcapxt_notify; 2111 2112 /** 2113 * IntCapXT requires XTSup=1 and MsiCapMmioSup=1, 2114 * which can be inferred from amd_iommu_xt_mode. 2115 */ 2116 if (amd_iommu_xt_mode != IRQ_REMAP_X2APIC_MODE) 2117 return 0; 2118 2119 /** 2120 * Also, we need to setup notifier to update the IntCapXT registers 2121 * whenever the irq affinity is changed from user-space. 2122 */ 2123 notify->irq = iommu->dev->irq; 2124 notify->notify = _irq_notifier_notify, 2125 notify->release = _irq_notifier_release, 2126 ret = irq_set_affinity_notifier(iommu->dev->irq, notify); 2127 if (ret) { 2128 pr_err("Failed to register irq affinity notifier (devid=%#x, irq %d)\n", 2129 iommu->devid, iommu->dev->irq); 2130 return ret; 2131 } 2132 2133 iommu_update_intcapxt(iommu); 2134 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2135 return ret; 2136 } 2137 2138 static int iommu_init_msi(struct amd_iommu *iommu) 2139 { 2140 int ret; 2141 2142 if (iommu->int_enabled) 2143 goto enable_faults; 2144 2145 if (iommu->dev->msi_cap) 2146 ret = iommu_setup_msi(iommu); 2147 else 2148 ret = -ENODEV; 2149 2150 if (ret) 2151 return ret; 2152 2153 enable_faults: 2154 ret = iommu_init_intcapxt(iommu); 2155 if (ret) 2156 return ret; 2157 2158 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2159 2160 if (iommu->ppr_log != NULL) 2161 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); 2162 2163 iommu_ga_log_enable(iommu); 2164 2165 return 0; 2166 } 2167 2168 /**************************************************************************** 2169 * 2170 * The next functions belong to the third pass of parsing the ACPI 2171 * table. In this last pass the memory mapping requirements are 2172 * gathered (like exclusion and unity mapping ranges). 2173 * 2174 ****************************************************************************/ 2175 2176 static void __init free_unity_maps(void) 2177 { 2178 struct unity_map_entry *entry, *next; 2179 2180 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { 2181 list_del(&entry->list); 2182 kfree(entry); 2183 } 2184 } 2185 2186 /* called for unity map ACPI definition */ 2187 static int __init init_unity_map_range(struct ivmd_header *m) 2188 { 2189 struct unity_map_entry *e = NULL; 2190 char *s; 2191 2192 e = kzalloc(sizeof(*e), GFP_KERNEL); 2193 if (e == NULL) 2194 return -ENOMEM; 2195 2196 switch (m->type) { 2197 default: 2198 kfree(e); 2199 return 0; 2200 case ACPI_IVMD_TYPE: 2201 s = "IVMD_TYPEi\t\t\t"; 2202 e->devid_start = e->devid_end = m->devid; 2203 break; 2204 case ACPI_IVMD_TYPE_ALL: 2205 s = "IVMD_TYPE_ALL\t\t"; 2206 e->devid_start = 0; 2207 e->devid_end = amd_iommu_last_bdf; 2208 break; 2209 case ACPI_IVMD_TYPE_RANGE: 2210 s = "IVMD_TYPE_RANGE\t\t"; 2211 e->devid_start = m->devid; 2212 e->devid_end = m->aux; 2213 break; 2214 } 2215 e->address_start = PAGE_ALIGN(m->range_start); 2216 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2217 e->prot = m->flags >> 1; 2218 2219 /* 2220 * Treat per-device exclusion ranges as r/w unity-mapped regions 2221 * since some buggy BIOSes might lead to the overwritten exclusion 2222 * range (exclusion_start and exclusion_length members). This 2223 * happens when there are multiple exclusion ranges (IVMD entries) 2224 * defined in ACPI table. 2225 */ 2226 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2227 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2228 2229 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" 2230 " range_start: %016llx range_end: %016llx flags: %x\n", s, 2231 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2232 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end), 2233 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2234 e->address_start, e->address_end, m->flags); 2235 2236 list_add_tail(&e->list, &amd_iommu_unity_map); 2237 2238 return 0; 2239 } 2240 2241 /* iterates over all memory definitions we find in the ACPI table */ 2242 static int __init init_memory_definitions(struct acpi_table_header *table) 2243 { 2244 u8 *p = (u8 *)table, *end = (u8 *)table; 2245 struct ivmd_header *m; 2246 2247 end += table->length; 2248 p += IVRS_HEADER_LENGTH; 2249 2250 while (p < end) { 2251 m = (struct ivmd_header *)p; 2252 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2253 init_unity_map_range(m); 2254 2255 p += m->length; 2256 } 2257 2258 return 0; 2259 } 2260 2261 /* 2262 * Init the device table to not allow DMA access for devices 2263 */ 2264 static void init_device_table_dma(void) 2265 { 2266 u32 devid; 2267 2268 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2269 set_dev_entry_bit(devid, DEV_ENTRY_VALID); 2270 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); 2271 } 2272 } 2273 2274 static void __init uninit_device_table_dma(void) 2275 { 2276 u32 devid; 2277 2278 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2279 amd_iommu_dev_table[devid].data[0] = 0ULL; 2280 amd_iommu_dev_table[devid].data[1] = 0ULL; 2281 } 2282 } 2283 2284 static void init_device_table(void) 2285 { 2286 u32 devid; 2287 2288 if (!amd_iommu_irq_remap) 2289 return; 2290 2291 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) 2292 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); 2293 } 2294 2295 static void iommu_init_flags(struct amd_iommu *iommu) 2296 { 2297 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2298 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2299 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2300 2301 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2302 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2303 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2304 2305 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2306 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2307 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2308 2309 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2310 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2311 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2312 2313 /* 2314 * make IOMMU memory accesses cache coherent 2315 */ 2316 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2317 2318 /* Set IOTLB invalidation timeout to 1s */ 2319 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); 2320 } 2321 2322 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2323 { 2324 int i, j; 2325 u32 ioc_feature_control; 2326 struct pci_dev *pdev = iommu->root_pdev; 2327 2328 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2329 if (!is_rd890_iommu(iommu->dev) || !pdev) 2330 return; 2331 2332 /* 2333 * First, we need to ensure that the iommu is enabled. This is 2334 * controlled by a register in the northbridge 2335 */ 2336 2337 /* Select Northbridge indirect register 0x75 and enable writing */ 2338 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2339 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2340 2341 /* Enable the iommu */ 2342 if (!(ioc_feature_control & 0x1)) 2343 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2344 2345 /* Restore the iommu BAR */ 2346 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2347 iommu->stored_addr_lo); 2348 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2349 iommu->stored_addr_hi); 2350 2351 /* Restore the l1 indirect regs for each of the 6 l1s */ 2352 for (i = 0; i < 6; i++) 2353 for (j = 0; j < 0x12; j++) 2354 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2355 2356 /* Restore the l2 indirect regs */ 2357 for (i = 0; i < 0x83; i++) 2358 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2359 2360 /* Lock PCI setup registers */ 2361 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2362 iommu->stored_addr_lo | 1); 2363 } 2364 2365 static void iommu_enable_ga(struct amd_iommu *iommu) 2366 { 2367 #ifdef CONFIG_IRQ_REMAP 2368 switch (amd_iommu_guest_ir) { 2369 case AMD_IOMMU_GUEST_IR_VAPIC: 2370 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2371 fallthrough; 2372 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2373 iommu_feature_enable(iommu, CONTROL_GA_EN); 2374 iommu->irte_ops = &irte_128_ops; 2375 break; 2376 default: 2377 iommu->irte_ops = &irte_32_ops; 2378 break; 2379 } 2380 #endif 2381 } 2382 2383 static void early_enable_iommu(struct amd_iommu *iommu) 2384 { 2385 iommu_disable(iommu); 2386 iommu_init_flags(iommu); 2387 iommu_set_device_table(iommu); 2388 iommu_enable_command_buffer(iommu); 2389 iommu_enable_event_buffer(iommu); 2390 iommu_set_exclusion_range(iommu); 2391 iommu_enable_ga(iommu); 2392 iommu_enable_xt(iommu); 2393 iommu_enable(iommu); 2394 iommu_flush_all_caches(iommu); 2395 } 2396 2397 /* 2398 * This function finally enables all IOMMUs found in the system after 2399 * they have been initialized. 2400 * 2401 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2402 * the old content of device table entries. Not this case or copy failed, 2403 * just continue as normal kernel does. 2404 */ 2405 static void early_enable_iommus(void) 2406 { 2407 struct amd_iommu *iommu; 2408 2409 2410 if (!copy_device_table()) { 2411 /* 2412 * If come here because of failure in copying device table from old 2413 * kernel with all IOMMUs enabled, print error message and try to 2414 * free allocated old_dev_tbl_cpy. 2415 */ 2416 if (amd_iommu_pre_enabled) 2417 pr_err("Failed to copy DEV table from previous kernel.\n"); 2418 if (old_dev_tbl_cpy != NULL) 2419 free_pages((unsigned long)old_dev_tbl_cpy, 2420 get_order(dev_table_size)); 2421 2422 for_each_iommu(iommu) { 2423 clear_translation_pre_enabled(iommu); 2424 early_enable_iommu(iommu); 2425 } 2426 } else { 2427 pr_info("Copied DEV table from previous kernel.\n"); 2428 free_pages((unsigned long)amd_iommu_dev_table, 2429 get_order(dev_table_size)); 2430 amd_iommu_dev_table = old_dev_tbl_cpy; 2431 for_each_iommu(iommu) { 2432 iommu_disable_command_buffer(iommu); 2433 iommu_disable_event_buffer(iommu); 2434 iommu_enable_command_buffer(iommu); 2435 iommu_enable_event_buffer(iommu); 2436 iommu_enable_ga(iommu); 2437 iommu_enable_xt(iommu); 2438 iommu_set_device_table(iommu); 2439 iommu_flush_all_caches(iommu); 2440 } 2441 } 2442 2443 #ifdef CONFIG_IRQ_REMAP 2444 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2445 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2446 #endif 2447 } 2448 2449 static void enable_iommus_v2(void) 2450 { 2451 struct amd_iommu *iommu; 2452 2453 for_each_iommu(iommu) { 2454 iommu_enable_ppr_log(iommu); 2455 iommu_enable_gt(iommu); 2456 } 2457 } 2458 2459 static void enable_iommus(void) 2460 { 2461 early_enable_iommus(); 2462 2463 enable_iommus_v2(); 2464 } 2465 2466 static void disable_iommus(void) 2467 { 2468 struct amd_iommu *iommu; 2469 2470 for_each_iommu(iommu) 2471 iommu_disable(iommu); 2472 2473 #ifdef CONFIG_IRQ_REMAP 2474 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2475 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2476 #endif 2477 } 2478 2479 /* 2480 * Suspend/Resume support 2481 * disable suspend until real resume implemented 2482 */ 2483 2484 static void amd_iommu_resume(void) 2485 { 2486 struct amd_iommu *iommu; 2487 2488 for_each_iommu(iommu) 2489 iommu_apply_resume_quirks(iommu); 2490 2491 /* re-load the hardware */ 2492 enable_iommus(); 2493 2494 amd_iommu_enable_interrupts(); 2495 } 2496 2497 static int amd_iommu_suspend(void) 2498 { 2499 /* disable IOMMUs to go out of the way for BIOS */ 2500 disable_iommus(); 2501 2502 return 0; 2503 } 2504 2505 static struct syscore_ops amd_iommu_syscore_ops = { 2506 .suspend = amd_iommu_suspend, 2507 .resume = amd_iommu_resume, 2508 }; 2509 2510 static void __init free_iommu_resources(void) 2511 { 2512 kmemleak_free(irq_lookup_table); 2513 free_pages((unsigned long)irq_lookup_table, 2514 get_order(rlookup_table_size)); 2515 irq_lookup_table = NULL; 2516 2517 kmem_cache_destroy(amd_iommu_irq_cache); 2518 amd_iommu_irq_cache = NULL; 2519 2520 free_pages((unsigned long)amd_iommu_rlookup_table, 2521 get_order(rlookup_table_size)); 2522 amd_iommu_rlookup_table = NULL; 2523 2524 free_pages((unsigned long)amd_iommu_alias_table, 2525 get_order(alias_table_size)); 2526 amd_iommu_alias_table = NULL; 2527 2528 free_pages((unsigned long)amd_iommu_dev_table, 2529 get_order(dev_table_size)); 2530 amd_iommu_dev_table = NULL; 2531 2532 free_iommu_all(); 2533 } 2534 2535 /* SB IOAPIC is always on this device in AMD systems */ 2536 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2537 2538 static bool __init check_ioapic_information(void) 2539 { 2540 const char *fw_bug = FW_BUG; 2541 bool ret, has_sb_ioapic; 2542 int idx; 2543 2544 has_sb_ioapic = false; 2545 ret = false; 2546 2547 /* 2548 * If we have map overrides on the kernel command line the 2549 * messages in this function might not describe firmware bugs 2550 * anymore - so be careful 2551 */ 2552 if (cmdline_maps) 2553 fw_bug = ""; 2554 2555 for (idx = 0; idx < nr_ioapics; idx++) { 2556 int devid, id = mpc_ioapic_id(idx); 2557 2558 devid = get_ioapic_devid(id); 2559 if (devid < 0) { 2560 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2561 fw_bug, id); 2562 ret = false; 2563 } else if (devid == IOAPIC_SB_DEVID) { 2564 has_sb_ioapic = true; 2565 ret = true; 2566 } 2567 } 2568 2569 if (!has_sb_ioapic) { 2570 /* 2571 * We expect the SB IOAPIC to be listed in the IVRS 2572 * table. The system timer is connected to the SB IOAPIC 2573 * and if we don't have it in the list the system will 2574 * panic at boot time. This situation usually happens 2575 * when the BIOS is buggy and provides us the wrong 2576 * device id for the IOAPIC in the system. 2577 */ 2578 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2579 } 2580 2581 if (!ret) 2582 pr_err("Disabling interrupt remapping\n"); 2583 2584 return ret; 2585 } 2586 2587 static void __init free_dma_resources(void) 2588 { 2589 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 2590 get_order(MAX_DOMAIN_ID/8)); 2591 amd_iommu_pd_alloc_bitmap = NULL; 2592 2593 free_unity_maps(); 2594 } 2595 2596 static void __init ivinfo_init(void *ivrs) 2597 { 2598 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 2599 } 2600 2601 /* 2602 * This is the hardware init function for AMD IOMMU in the system. 2603 * This function is called either from amd_iommu_init or from the interrupt 2604 * remapping setup code. 2605 * 2606 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 2607 * four times: 2608 * 2609 * 1 pass) Discover the most comprehensive IVHD type to use. 2610 * 2611 * 2 pass) Find the highest PCI device id the driver has to handle. 2612 * Upon this information the size of the data structures is 2613 * determined that needs to be allocated. 2614 * 2615 * 3 pass) Initialize the data structures just allocated with the 2616 * information in the ACPI table about available AMD IOMMUs 2617 * in the system. It also maps the PCI devices in the 2618 * system to specific IOMMUs 2619 * 2620 * 4 pass) After the basic data structures are allocated and 2621 * initialized we update them with information about memory 2622 * remapping requirements parsed out of the ACPI table in 2623 * this last pass. 2624 * 2625 * After everything is set up the IOMMUs are enabled and the necessary 2626 * hotplug and suspend notifiers are registered. 2627 */ 2628 static int __init early_amd_iommu_init(void) 2629 { 2630 struct acpi_table_header *ivrs_base; 2631 acpi_status status; 2632 int i, remap_cache_sz, ret = 0; 2633 u32 pci_id; 2634 2635 if (!amd_iommu_detected) 2636 return -ENODEV; 2637 2638 status = acpi_get_table("IVRS", 0, &ivrs_base); 2639 if (status == AE_NOT_FOUND) 2640 return -ENODEV; 2641 else if (ACPI_FAILURE(status)) { 2642 const char *err = acpi_format_exception(status); 2643 pr_err("IVRS table error: %s\n", err); 2644 return -EINVAL; 2645 } 2646 2647 /* 2648 * Validate checksum here so we don't need to do it when 2649 * we actually parse the table 2650 */ 2651 ret = check_ivrs_checksum(ivrs_base); 2652 if (ret) 2653 goto out; 2654 2655 ivinfo_init(ivrs_base); 2656 2657 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 2658 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 2659 2660 /* 2661 * First parse ACPI tables to find the largest Bus/Dev/Func 2662 * we need to handle. Upon this information the shared data 2663 * structures for the IOMMUs in the system will be allocated 2664 */ 2665 ret = find_last_devid_acpi(ivrs_base); 2666 if (ret) 2667 goto out; 2668 2669 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 2670 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 2671 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); 2672 2673 /* Device table - directly used by all IOMMUs */ 2674 ret = -ENOMEM; 2675 amd_iommu_dev_table = (void *)__get_free_pages( 2676 GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 2677 get_order(dev_table_size)); 2678 if (amd_iommu_dev_table == NULL) 2679 goto out; 2680 2681 /* 2682 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the 2683 * IOMMU see for that device 2684 */ 2685 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, 2686 get_order(alias_table_size)); 2687 if (amd_iommu_alias_table == NULL) 2688 goto out; 2689 2690 /* IOMMU rlookup table - find the IOMMU for a specific device */ 2691 amd_iommu_rlookup_table = (void *)__get_free_pages( 2692 GFP_KERNEL | __GFP_ZERO, 2693 get_order(rlookup_table_size)); 2694 if (amd_iommu_rlookup_table == NULL) 2695 goto out; 2696 2697 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( 2698 GFP_KERNEL | __GFP_ZERO, 2699 get_order(MAX_DOMAIN_ID/8)); 2700 if (amd_iommu_pd_alloc_bitmap == NULL) 2701 goto out; 2702 2703 /* 2704 * let all alias entries point to itself 2705 */ 2706 for (i = 0; i <= amd_iommu_last_bdf; ++i) 2707 amd_iommu_alias_table[i] = i; 2708 2709 /* 2710 * never allocate domain 0 because its used as the non-allocated and 2711 * error value placeholder 2712 */ 2713 __set_bit(0, amd_iommu_pd_alloc_bitmap); 2714 2715 /* 2716 * now the data structures are allocated and basically initialized 2717 * start the real acpi table scan 2718 */ 2719 ret = init_iommu_all(ivrs_base); 2720 if (ret) 2721 goto out; 2722 2723 /* Disable IOMMU if there's Stoney Ridge graphics */ 2724 for (i = 0; i < 32; i++) { 2725 pci_id = read_pci_config(0, i, 0, 0); 2726 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 2727 pr_info("Disable IOMMU on Stoney Ridge\n"); 2728 amd_iommu_disabled = true; 2729 break; 2730 } 2731 } 2732 2733 /* Disable any previously enabled IOMMUs */ 2734 if (!is_kdump_kernel() || amd_iommu_disabled) 2735 disable_iommus(); 2736 2737 if (amd_iommu_irq_remap) 2738 amd_iommu_irq_remap = check_ioapic_information(); 2739 2740 if (amd_iommu_irq_remap) { 2741 /* 2742 * Interrupt remapping enabled, create kmem_cache for the 2743 * remapping tables. 2744 */ 2745 ret = -ENOMEM; 2746 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 2747 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32); 2748 else 2749 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2); 2750 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", 2751 remap_cache_sz, 2752 IRQ_TABLE_ALIGNMENT, 2753 0, NULL); 2754 if (!amd_iommu_irq_cache) 2755 goto out; 2756 2757 irq_lookup_table = (void *)__get_free_pages( 2758 GFP_KERNEL | __GFP_ZERO, 2759 get_order(rlookup_table_size)); 2760 kmemleak_alloc(irq_lookup_table, rlookup_table_size, 2761 1, GFP_KERNEL); 2762 if (!irq_lookup_table) 2763 goto out; 2764 } 2765 2766 ret = init_memory_definitions(ivrs_base); 2767 if (ret) 2768 goto out; 2769 2770 /* init the device table */ 2771 init_device_table(); 2772 2773 out: 2774 /* Don't leak any ACPI memory */ 2775 acpi_put_table(ivrs_base); 2776 ivrs_base = NULL; 2777 2778 return ret; 2779 } 2780 2781 static int amd_iommu_enable_interrupts(void) 2782 { 2783 struct amd_iommu *iommu; 2784 int ret = 0; 2785 2786 for_each_iommu(iommu) { 2787 ret = iommu_init_msi(iommu); 2788 if (ret) 2789 goto out; 2790 } 2791 2792 out: 2793 return ret; 2794 } 2795 2796 static bool detect_ivrs(void) 2797 { 2798 struct acpi_table_header *ivrs_base; 2799 acpi_status status; 2800 2801 status = acpi_get_table("IVRS", 0, &ivrs_base); 2802 if (status == AE_NOT_FOUND) 2803 return false; 2804 else if (ACPI_FAILURE(status)) { 2805 const char *err = acpi_format_exception(status); 2806 pr_err("IVRS table error: %s\n", err); 2807 return false; 2808 } 2809 2810 acpi_put_table(ivrs_base); 2811 2812 /* Make sure ACS will be enabled during PCI probe */ 2813 pci_request_acs(); 2814 2815 return true; 2816 } 2817 2818 /**************************************************************************** 2819 * 2820 * AMD IOMMU Initialization State Machine 2821 * 2822 ****************************************************************************/ 2823 2824 static int __init state_next(void) 2825 { 2826 int ret = 0; 2827 2828 switch (init_state) { 2829 case IOMMU_START_STATE: 2830 if (!detect_ivrs()) { 2831 init_state = IOMMU_NOT_FOUND; 2832 ret = -ENODEV; 2833 } else { 2834 init_state = IOMMU_IVRS_DETECTED; 2835 } 2836 break; 2837 case IOMMU_IVRS_DETECTED: 2838 ret = early_amd_iommu_init(); 2839 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 2840 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) { 2841 pr_info("AMD IOMMU disabled\n"); 2842 init_state = IOMMU_CMDLINE_DISABLED; 2843 ret = -EINVAL; 2844 } 2845 break; 2846 case IOMMU_ACPI_FINISHED: 2847 early_enable_iommus(); 2848 x86_platform.iommu_shutdown = disable_iommus; 2849 init_state = IOMMU_ENABLED; 2850 break; 2851 case IOMMU_ENABLED: 2852 register_syscore_ops(&amd_iommu_syscore_ops); 2853 ret = amd_iommu_init_pci(); 2854 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 2855 enable_iommus_v2(); 2856 break; 2857 case IOMMU_PCI_INIT: 2858 ret = amd_iommu_enable_interrupts(); 2859 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 2860 break; 2861 case IOMMU_INTERRUPTS_EN: 2862 ret = amd_iommu_init_dma_ops(); 2863 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS; 2864 break; 2865 case IOMMU_DMA_OPS: 2866 init_state = IOMMU_INITIALIZED; 2867 break; 2868 case IOMMU_INITIALIZED: 2869 /* Nothing to do */ 2870 break; 2871 case IOMMU_NOT_FOUND: 2872 case IOMMU_INIT_ERROR: 2873 case IOMMU_CMDLINE_DISABLED: 2874 /* Error states => do nothing */ 2875 ret = -EINVAL; 2876 break; 2877 default: 2878 /* Unknown state */ 2879 BUG(); 2880 } 2881 2882 if (ret) { 2883 free_dma_resources(); 2884 if (!irq_remapping_enabled) { 2885 disable_iommus(); 2886 free_iommu_resources(); 2887 } else { 2888 struct amd_iommu *iommu; 2889 2890 uninit_device_table_dma(); 2891 for_each_iommu(iommu) 2892 iommu_flush_all_caches(iommu); 2893 } 2894 } 2895 return ret; 2896 } 2897 2898 static int __init iommu_go_to_state(enum iommu_init_state state) 2899 { 2900 int ret = -EINVAL; 2901 2902 while (init_state != state) { 2903 if (init_state == IOMMU_NOT_FOUND || 2904 init_state == IOMMU_INIT_ERROR || 2905 init_state == IOMMU_CMDLINE_DISABLED) 2906 break; 2907 ret = state_next(); 2908 } 2909 2910 return ret; 2911 } 2912 2913 #ifdef CONFIG_IRQ_REMAP 2914 int __init amd_iommu_prepare(void) 2915 { 2916 int ret; 2917 2918 amd_iommu_irq_remap = true; 2919 2920 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 2921 if (ret) 2922 return ret; 2923 return amd_iommu_irq_remap ? 0 : -ENODEV; 2924 } 2925 2926 int __init amd_iommu_enable(void) 2927 { 2928 int ret; 2929 2930 ret = iommu_go_to_state(IOMMU_ENABLED); 2931 if (ret) 2932 return ret; 2933 2934 irq_remapping_enabled = 1; 2935 return amd_iommu_xt_mode; 2936 } 2937 2938 void amd_iommu_disable(void) 2939 { 2940 amd_iommu_suspend(); 2941 } 2942 2943 int amd_iommu_reenable(int mode) 2944 { 2945 amd_iommu_resume(); 2946 2947 return 0; 2948 } 2949 2950 int __init amd_iommu_enable_faulting(void) 2951 { 2952 /* We enable MSI later when PCI is initialized */ 2953 return 0; 2954 } 2955 #endif 2956 2957 /* 2958 * This is the core init function for AMD IOMMU hardware in the system. 2959 * This function is called from the generic x86 DMA layer initialization 2960 * code. 2961 */ 2962 static int __init amd_iommu_init(void) 2963 { 2964 struct amd_iommu *iommu; 2965 int ret; 2966 2967 ret = iommu_go_to_state(IOMMU_INITIALIZED); 2968 #ifdef CONFIG_GART_IOMMU 2969 if (ret && list_empty(&amd_iommu_list)) { 2970 /* 2971 * We failed to initialize the AMD IOMMU - try fallback 2972 * to GART if possible. 2973 */ 2974 gart_iommu_init(); 2975 } 2976 #endif 2977 2978 for_each_iommu(iommu) 2979 amd_iommu_debugfs_setup(iommu); 2980 2981 return ret; 2982 } 2983 2984 static bool amd_iommu_sme_check(void) 2985 { 2986 if (!sme_active() || (boot_cpu_data.x86 != 0x17)) 2987 return true; 2988 2989 /* For Fam17h, a specific level of support is required */ 2990 if (boot_cpu_data.microcode >= 0x08001205) 2991 return true; 2992 2993 if ((boot_cpu_data.microcode >= 0x08001126) && 2994 (boot_cpu_data.microcode <= 0x080011ff)) 2995 return true; 2996 2997 pr_notice("IOMMU not currently supported when SME is active\n"); 2998 2999 return false; 3000 } 3001 3002 /**************************************************************************** 3003 * 3004 * Early detect code. This code runs at IOMMU detection time in the DMA 3005 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3006 * IOMMUs 3007 * 3008 ****************************************************************************/ 3009 int __init amd_iommu_detect(void) 3010 { 3011 int ret; 3012 3013 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3014 return -ENODEV; 3015 3016 if (!amd_iommu_sme_check()) 3017 return -ENODEV; 3018 3019 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3020 if (ret) 3021 return ret; 3022 3023 amd_iommu_detected = true; 3024 iommu_detected = 1; 3025 x86_init.iommu.iommu_init = amd_iommu_init; 3026 3027 return 1; 3028 } 3029 3030 /**************************************************************************** 3031 * 3032 * Parsing functions for the AMD IOMMU specific kernel command line 3033 * options. 3034 * 3035 ****************************************************************************/ 3036 3037 static int __init parse_amd_iommu_dump(char *str) 3038 { 3039 amd_iommu_dump = true; 3040 3041 return 1; 3042 } 3043 3044 static int __init parse_amd_iommu_intr(char *str) 3045 { 3046 for (; *str; ++str) { 3047 if (strncmp(str, "legacy", 6) == 0) { 3048 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3049 break; 3050 } 3051 if (strncmp(str, "vapic", 5) == 0) { 3052 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3053 break; 3054 } 3055 } 3056 return 1; 3057 } 3058 3059 static int __init parse_amd_iommu_options(char *str) 3060 { 3061 for (; *str; ++str) { 3062 if (strncmp(str, "fullflush", 9) == 0) 3063 amd_iommu_unmap_flush = true; 3064 if (strncmp(str, "off", 3) == 0) 3065 amd_iommu_disabled = true; 3066 if (strncmp(str, "force_isolation", 15) == 0) 3067 amd_iommu_force_isolation = true; 3068 } 3069 3070 return 1; 3071 } 3072 3073 static int __init parse_ivrs_ioapic(char *str) 3074 { 3075 unsigned int bus, dev, fn; 3076 int ret, id, i; 3077 u16 devid; 3078 3079 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3080 3081 if (ret != 4) { 3082 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3083 return 1; 3084 } 3085 3086 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3087 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3088 str); 3089 return 1; 3090 } 3091 3092 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3093 3094 cmdline_maps = true; 3095 i = early_ioapic_map_size++; 3096 early_ioapic_map[i].id = id; 3097 early_ioapic_map[i].devid = devid; 3098 early_ioapic_map[i].cmd_line = true; 3099 3100 return 1; 3101 } 3102 3103 static int __init parse_ivrs_hpet(char *str) 3104 { 3105 unsigned int bus, dev, fn; 3106 int ret, id, i; 3107 u16 devid; 3108 3109 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3110 3111 if (ret != 4) { 3112 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3113 return 1; 3114 } 3115 3116 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3117 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3118 str); 3119 return 1; 3120 } 3121 3122 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3123 3124 cmdline_maps = true; 3125 i = early_hpet_map_size++; 3126 early_hpet_map[i].id = id; 3127 early_hpet_map[i].devid = devid; 3128 early_hpet_map[i].cmd_line = true; 3129 3130 return 1; 3131 } 3132 3133 static int __init parse_ivrs_acpihid(char *str) 3134 { 3135 u32 bus, dev, fn; 3136 char *hid, *uid, *p; 3137 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0}; 3138 int ret, i; 3139 3140 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid); 3141 if (ret != 4) { 3142 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str); 3143 return 1; 3144 } 3145 3146 p = acpiid; 3147 hid = strsep(&p, ":"); 3148 uid = p; 3149 3150 if (!hid || !(*hid) || !uid) { 3151 pr_err("Invalid command line: hid or uid\n"); 3152 return 1; 3153 } 3154 3155 i = early_acpihid_map_size++; 3156 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3157 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3158 early_acpihid_map[i].devid = 3159 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3160 early_acpihid_map[i].cmd_line = true; 3161 3162 return 1; 3163 } 3164 3165 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3166 __setup("amd_iommu=", parse_amd_iommu_options); 3167 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3168 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3169 __setup("ivrs_hpet", parse_ivrs_hpet); 3170 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3171 3172 IOMMU_INIT_FINISH(amd_iommu_detect, 3173 gart_iommu_hole_init, 3174 NULL, 3175 NULL); 3176 3177 bool amd_iommu_v2_supported(void) 3178 { 3179 return amd_iommu_v2_present; 3180 } 3181 EXPORT_SYMBOL(amd_iommu_v2_supported); 3182 3183 struct amd_iommu *get_amd_iommu(unsigned int idx) 3184 { 3185 unsigned int i = 0; 3186 struct amd_iommu *iommu; 3187 3188 for_each_iommu(iommu) 3189 if (i++ == idx) 3190 return iommu; 3191 return NULL; 3192 } 3193 EXPORT_SYMBOL(get_amd_iommu); 3194 3195 /**************************************************************************** 3196 * 3197 * IOMMU EFR Performance Counter support functionality. This code allows 3198 * access to the IOMMU PC functionality. 3199 * 3200 ****************************************************************************/ 3201 3202 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3203 { 3204 struct amd_iommu *iommu = get_amd_iommu(idx); 3205 3206 if (iommu) 3207 return iommu->max_banks; 3208 3209 return 0; 3210 } 3211 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks); 3212 3213 bool amd_iommu_pc_supported(void) 3214 { 3215 return amd_iommu_pc_present; 3216 } 3217 EXPORT_SYMBOL(amd_iommu_pc_supported); 3218 3219 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3220 { 3221 struct amd_iommu *iommu = get_amd_iommu(idx); 3222 3223 if (iommu) 3224 return iommu->max_counters; 3225 3226 return 0; 3227 } 3228 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters); 3229 3230 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3231 u8 fxn, u64 *value, bool is_write) 3232 { 3233 u32 offset; 3234 u32 max_offset_lim; 3235 3236 /* Make sure the IOMMU PC resource is available */ 3237 if (!amd_iommu_pc_present) 3238 return -ENODEV; 3239 3240 /* Check for valid iommu and pc register indexing */ 3241 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3242 return -ENODEV; 3243 3244 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3245 3246 /* Limit the offset to the hw defined mmio region aperture */ 3247 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3248 (iommu->max_counters << 8) | 0x28); 3249 if ((offset < MMIO_CNTR_REG_OFFSET) || 3250 (offset > max_offset_lim)) 3251 return -EINVAL; 3252 3253 if (is_write) { 3254 u64 val = *value & GENMASK_ULL(47, 0); 3255 3256 writel((u32)val, iommu->mmio_base + offset); 3257 writel((val >> 32), iommu->mmio_base + offset + 4); 3258 } else { 3259 *value = readl(iommu->mmio_base + offset + 4); 3260 *value <<= 32; 3261 *value |= readl(iommu->mmio_base + offset); 3262 *value &= GENMASK_ULL(47, 0); 3263 } 3264 3265 return 0; 3266 } 3267 3268 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3269 { 3270 if (!iommu) 3271 return -EINVAL; 3272 3273 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3274 } 3275 EXPORT_SYMBOL(amd_iommu_pc_get_reg); 3276 3277 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3278 { 3279 if (!iommu) 3280 return -EINVAL; 3281 3282 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3283 } 3284 EXPORT_SYMBOL(amd_iommu_pc_set_reg); 3285