1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H 9 #define _ASM_X86_AMD_IOMMU_TYPES_H 10 11 #include <linux/types.h> 12 #include <linux/mutex.h> 13 #include <linux/msi.h> 14 #include <linux/list.h> 15 #include <linux/spinlock.h> 16 #include <linux/pci.h> 17 #include <linux/irqreturn.h> 18 #include <linux/io-pgtable.h> 19 20 /* 21 * Maximum number of IOMMUs supported 22 */ 23 #define MAX_IOMMUS 32 24 25 /* 26 * some size calculation constants 27 */ 28 #define DEV_TABLE_ENTRY_SIZE 32 29 #define ALIAS_TABLE_ENTRY_SIZE 2 30 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) 31 32 /* Capability offsets used by the driver */ 33 #define MMIO_CAP_HDR_OFFSET 0x00 34 #define MMIO_RANGE_OFFSET 0x0c 35 #define MMIO_MISC_OFFSET 0x10 36 37 /* Masks, shifts and macros to parse the device range capability */ 38 #define MMIO_RANGE_LD_MASK 0xff000000 39 #define MMIO_RANGE_FD_MASK 0x00ff0000 40 #define MMIO_RANGE_BUS_MASK 0x0000ff00 41 #define MMIO_RANGE_LD_SHIFT 24 42 #define MMIO_RANGE_FD_SHIFT 16 43 #define MMIO_RANGE_BUS_SHIFT 8 44 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) 45 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) 46 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) 47 #define MMIO_MSI_NUM(x) ((x) & 0x1f) 48 49 /* Flag masks for the AMD IOMMU exclusion range */ 50 #define MMIO_EXCL_ENABLE_MASK 0x01ULL 51 #define MMIO_EXCL_ALLOW_MASK 0x02ULL 52 53 /* Used offsets into the MMIO space */ 54 #define MMIO_DEV_TABLE_OFFSET 0x0000 55 #define MMIO_CMD_BUF_OFFSET 0x0008 56 #define MMIO_EVT_BUF_OFFSET 0x0010 57 #define MMIO_CONTROL_OFFSET 0x0018 58 #define MMIO_EXCL_BASE_OFFSET 0x0020 59 #define MMIO_EXCL_LIMIT_OFFSET 0x0028 60 #define MMIO_EXT_FEATURES 0x0030 61 #define MMIO_PPR_LOG_OFFSET 0x0038 62 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 63 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8 64 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C 65 #define MMIO_MSI_ADDR_HI_OFFSET 0x0160 66 #define MMIO_MSI_DATA_OFFSET 0x0164 67 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170 68 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178 69 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180 70 #define MMIO_EXT_FEATURES2 0x01A0 71 #define MMIO_CMD_HEAD_OFFSET 0x2000 72 #define MMIO_CMD_TAIL_OFFSET 0x2008 73 #define MMIO_EVT_HEAD_OFFSET 0x2010 74 #define MMIO_EVT_TAIL_OFFSET 0x2018 75 #define MMIO_STATUS_OFFSET 0x2020 76 #define MMIO_PPR_HEAD_OFFSET 0x2030 77 #define MMIO_PPR_TAIL_OFFSET 0x2038 78 #define MMIO_GA_HEAD_OFFSET 0x2040 79 #define MMIO_GA_TAIL_OFFSET 0x2048 80 #define MMIO_CNTR_CONF_OFFSET 0x4000 81 #define MMIO_CNTR_REG_OFFSET 0x40000 82 #define MMIO_REG_END_OFFSET 0x80000 83 84 85 86 /* Extended Feature Bits */ 87 #define FEATURE_PREFETCH BIT_ULL(0) 88 #define FEATURE_PPR BIT_ULL(1) 89 #define FEATURE_X2APIC BIT_ULL(2) 90 #define FEATURE_NX BIT_ULL(3) 91 #define FEATURE_GT BIT_ULL(4) 92 #define FEATURE_IA BIT_ULL(6) 93 #define FEATURE_GA BIT_ULL(7) 94 #define FEATURE_HE BIT_ULL(8) 95 #define FEATURE_PC BIT_ULL(9) 96 #define FEATURE_GATS_SHIFT (12) 97 #define FEATURE_GATS_MASK (3ULL) 98 #define FEATURE_GAM_VAPIC BIT_ULL(21) 99 #define FEATURE_GIOSUP BIT_ULL(48) 100 #define FEATURE_EPHSUP BIT_ULL(50) 101 #define FEATURE_SNP BIT_ULL(63) 102 103 #define FEATURE_PASID_SHIFT 32 104 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) 105 106 #define FEATURE_GLXVAL_SHIFT 14 107 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) 108 109 /* Extended Feature 2 Bits */ 110 #define FEATURE_SNPAVICSUP_SHIFT 5 111 #define FEATURE_SNPAVICSUP_MASK (0x07ULL << FEATURE_SNPAVICSUP_SHIFT) 112 #define FEATURE_SNPAVICSUP_GAM(x) \ 113 ((x & FEATURE_SNPAVICSUP_MASK) >> FEATURE_SNPAVICSUP_SHIFT == 0x1) 114 115 /* Note: 116 * The current driver only support 16-bit PASID. 117 * Currently, hardware only implement upto 16-bit PASID 118 * even though the spec says it could have upto 20 bits. 119 */ 120 #define PASID_MASK 0x0000ffff 121 122 /* MMIO status bits */ 123 #define MMIO_STATUS_EVT_OVERFLOW_MASK BIT(0) 124 #define MMIO_STATUS_EVT_INT_MASK BIT(1) 125 #define MMIO_STATUS_COM_WAIT_INT_MASK BIT(2) 126 #define MMIO_STATUS_EVT_RUN_MASK BIT(3) 127 #define MMIO_STATUS_PPR_OVERFLOW_MASK BIT(5) 128 #define MMIO_STATUS_PPR_INT_MASK BIT(6) 129 #define MMIO_STATUS_PPR_RUN_MASK BIT(7) 130 #define MMIO_STATUS_GALOG_RUN_MASK BIT(8) 131 #define MMIO_STATUS_GALOG_OVERFLOW_MASK BIT(9) 132 #define MMIO_STATUS_GALOG_INT_MASK BIT(10) 133 134 /* event logging constants */ 135 #define EVENT_ENTRY_SIZE 0x10 136 #define EVENT_TYPE_SHIFT 28 137 #define EVENT_TYPE_MASK 0xf 138 #define EVENT_TYPE_ILL_DEV 0x1 139 #define EVENT_TYPE_IO_FAULT 0x2 140 #define EVENT_TYPE_DEV_TAB_ERR 0x3 141 #define EVENT_TYPE_PAGE_TAB_ERR 0x4 142 #define EVENT_TYPE_ILL_CMD 0x5 143 #define EVENT_TYPE_CMD_HARD_ERR 0x6 144 #define EVENT_TYPE_IOTLB_INV_TO 0x7 145 #define EVENT_TYPE_INV_DEV_REQ 0x8 146 #define EVENT_TYPE_INV_PPR_REQ 0x9 147 #define EVENT_TYPE_RMP_FAULT 0xd 148 #define EVENT_TYPE_RMP_HW_ERR 0xe 149 #define EVENT_DEVID_MASK 0xffff 150 #define EVENT_DEVID_SHIFT 0 151 #define EVENT_DOMID_MASK_LO 0xffff 152 #define EVENT_DOMID_MASK_HI 0xf0000 153 #define EVENT_FLAGS_MASK 0xfff 154 #define EVENT_FLAGS_SHIFT 0x10 155 #define EVENT_FLAG_RW 0x020 156 #define EVENT_FLAG_I 0x008 157 158 /* feature control bits */ 159 #define CONTROL_IOMMU_EN 0 160 #define CONTROL_HT_TUN_EN 1 161 #define CONTROL_EVT_LOG_EN 2 162 #define CONTROL_EVT_INT_EN 3 163 #define CONTROL_COMWAIT_EN 4 164 #define CONTROL_INV_TIMEOUT 5 165 #define CONTROL_PASSPW_EN 8 166 #define CONTROL_RESPASSPW_EN 9 167 #define CONTROL_COHERENT_EN 10 168 #define CONTROL_ISOC_EN 11 169 #define CONTROL_CMDBUF_EN 12 170 #define CONTROL_PPRLOG_EN 13 171 #define CONTROL_PPRINT_EN 14 172 #define CONTROL_PPR_EN 15 173 #define CONTROL_GT_EN 16 174 #define CONTROL_GA_EN 17 175 #define CONTROL_GAM_EN 25 176 #define CONTROL_GALOG_EN 28 177 #define CONTROL_GAINT_EN 29 178 #define CONTROL_XT_EN 50 179 #define CONTROL_INTCAPXT_EN 51 180 #define CONTROL_IRTCACHEDIS 59 181 #define CONTROL_SNPAVIC_EN 61 182 183 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) 184 #define CTRL_INV_TO_NONE 0 185 #define CTRL_INV_TO_1MS 1 186 #define CTRL_INV_TO_10MS 2 187 #define CTRL_INV_TO_100MS 3 188 #define CTRL_INV_TO_1S 4 189 #define CTRL_INV_TO_10S 5 190 #define CTRL_INV_TO_100S 6 191 192 /* command specific defines */ 193 #define CMD_COMPL_WAIT 0x01 194 #define CMD_INV_DEV_ENTRY 0x02 195 #define CMD_INV_IOMMU_PAGES 0x03 196 #define CMD_INV_IOTLB_PAGES 0x04 197 #define CMD_INV_IRT 0x05 198 #define CMD_COMPLETE_PPR 0x07 199 #define CMD_INV_ALL 0x08 200 201 #define CMD_COMPL_WAIT_STORE_MASK 0x01 202 #define CMD_COMPL_WAIT_INT_MASK 0x02 203 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 204 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 205 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 206 207 #define PPR_STATUS_MASK 0xf 208 #define PPR_STATUS_SHIFT 12 209 210 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL 211 212 /* macros and definitions for device table entries */ 213 #define DEV_ENTRY_VALID 0x00 214 #define DEV_ENTRY_TRANSLATION 0x01 215 #define DEV_ENTRY_PPR 0x34 216 #define DEV_ENTRY_IR 0x3d 217 #define DEV_ENTRY_IW 0x3e 218 #define DEV_ENTRY_NO_PAGE_FAULT 0x62 219 #define DEV_ENTRY_EX 0x67 220 #define DEV_ENTRY_SYSMGT1 0x68 221 #define DEV_ENTRY_SYSMGT2 0x69 222 #define DEV_ENTRY_IRQ_TBL_EN 0x80 223 #define DEV_ENTRY_INIT_PASS 0xb8 224 #define DEV_ENTRY_EINT_PASS 0xb9 225 #define DEV_ENTRY_NMI_PASS 0xba 226 #define DEV_ENTRY_LINT0_PASS 0xbe 227 #define DEV_ENTRY_LINT1_PASS 0xbf 228 #define DEV_ENTRY_MODE_MASK 0x07 229 #define DEV_ENTRY_MODE_SHIFT 0x09 230 231 #define MAX_DEV_TABLE_ENTRIES 0xffff 232 233 /* constants to configure the command buffer */ 234 #define CMD_BUFFER_SIZE 8192 235 #define CMD_BUFFER_UNINITIALIZED 1 236 #define CMD_BUFFER_ENTRIES 512 237 #define MMIO_CMD_SIZE_SHIFT 56 238 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) 239 240 /* constants for event buffer handling */ 241 #define EVT_BUFFER_SIZE 8192 /* 512 entries */ 242 #define EVT_LEN_MASK (0x9ULL << 56) 243 244 /* Constants for PPR Log handling */ 245 #define PPR_LOG_ENTRIES 512 246 #define PPR_LOG_SIZE_SHIFT 56 247 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) 248 #define PPR_ENTRY_SIZE 16 249 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) 250 251 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) 252 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) 253 #define PPR_DEVID(x) ((x) & 0xffffULL) 254 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) 255 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) 256 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) 257 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) 258 259 #define PPR_REQ_FAULT 0x01 260 261 /* Constants for GA Log handling */ 262 #define GA_LOG_ENTRIES 512 263 #define GA_LOG_SIZE_SHIFT 56 264 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT) 265 #define GA_ENTRY_SIZE 8 266 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES) 267 268 #define GA_TAG(x) (u32)(x & 0xffffffffULL) 269 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL) 270 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL) 271 272 #define GA_GUEST_NR 0x1 273 274 #define IOMMU_IN_ADDR_BIT_SIZE 52 275 #define IOMMU_OUT_ADDR_BIT_SIZE 52 276 277 /* 278 * This bitmap is used to advertise the page sizes our hardware support 279 * to the IOMMU core, which will then use this information to split 280 * physically contiguous memory regions it is mapping into page sizes 281 * that we support. 282 * 283 * 512GB Pages are not supported due to a hardware bug 284 */ 285 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) 286 /* 4K, 2MB, 1G page sizes are supported */ 287 #define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30)) 288 289 /* Bit value definition for dte irq remapping fields*/ 290 #define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6) 291 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60) 292 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) 293 #define DTE_IRQ_REMAP_ENABLE 1ULL 294 295 /* 296 * AMD IOMMU hardware only support 512 IRTEs despite 297 * the architectural limitation of 2048 entries. 298 */ 299 #define DTE_INTTAB_ALIGNMENT 128 300 #define DTE_INTTABLEN_VALUE 9ULL 301 #define DTE_INTTABLEN (DTE_INTTABLEN_VALUE << 1) 302 #define DTE_INTTABLEN_MASK (0xfULL << 1) 303 #define MAX_IRQS_PER_TABLE (1 << DTE_INTTABLEN_VALUE) 304 305 #define PAGE_MODE_NONE 0x00 306 #define PAGE_MODE_1_LEVEL 0x01 307 #define PAGE_MODE_2_LEVEL 0x02 308 #define PAGE_MODE_3_LEVEL 0x03 309 #define PAGE_MODE_4_LEVEL 0x04 310 #define PAGE_MODE_5_LEVEL 0x05 311 #define PAGE_MODE_6_LEVEL 0x06 312 #define PAGE_MODE_7_LEVEL 0x07 313 314 #define GUEST_PGTABLE_4_LEVEL 0x00 315 #define GUEST_PGTABLE_5_LEVEL 0x01 316 317 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) 318 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ 319 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ 320 (0xffffffffffffffffULL)) 321 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) 322 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) 323 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ 324 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW) 325 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) 326 327 #define PM_MAP_4k 0 328 #define PM_ADDR_MASK 0x000ffffffffff000ULL 329 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ 330 (~((1ULL << (12 + ((lvl) * 9))) - 1))) 331 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) 332 333 /* 334 * Returns the page table level to use for a given page size 335 * Pagesize is expected to be a power-of-two 336 */ 337 #define PAGE_SIZE_LEVEL(pagesize) \ 338 ((__ffs(pagesize) - 12) / 9) 339 /* 340 * Returns the number of ptes to use for a given page size 341 * Pagesize is expected to be a power-of-two 342 */ 343 #define PAGE_SIZE_PTE_COUNT(pagesize) \ 344 (1ULL << ((__ffs(pagesize) - 12) % 9)) 345 346 /* 347 * Aligns a given io-virtual address to a given page size 348 * Pagesize is expected to be a power-of-two 349 */ 350 #define PAGE_SIZE_ALIGN(address, pagesize) \ 351 ((address) & ~((pagesize) - 1)) 352 /* 353 * Creates an IOMMU PTE for an address and a given pagesize 354 * The PTE has no permission bits set 355 * Pagesize is expected to be a power-of-two larger than 4096 356 */ 357 #define PAGE_SIZE_PTE(address, pagesize) \ 358 (((address) | ((pagesize) - 1)) & \ 359 (~(pagesize >> 1)) & PM_ADDR_MASK) 360 361 /* 362 * Takes a PTE value with mode=0x07 and returns the page size it maps 363 */ 364 #define PTE_PAGE_SIZE(pte) \ 365 (1ULL << (1 + ffz(((pte) | 0xfffULL)))) 366 367 /* 368 * Takes a page-table level and returns the default page-size for this level 369 */ 370 #define PTE_LEVEL_PAGE_SIZE(level) \ 371 (1ULL << (12 + (9 * (level)))) 372 373 /* 374 * Bit value definition for I/O PTE fields 375 */ 376 #define IOMMU_PTE_PR BIT_ULL(0) 377 #define IOMMU_PTE_U BIT_ULL(59) 378 #define IOMMU_PTE_FC BIT_ULL(60) 379 #define IOMMU_PTE_IR BIT_ULL(61) 380 #define IOMMU_PTE_IW BIT_ULL(62) 381 382 /* 383 * Bit value definition for DTE fields 384 */ 385 #define DTE_FLAG_V BIT_ULL(0) 386 #define DTE_FLAG_TV BIT_ULL(1) 387 #define DTE_FLAG_GIOV BIT_ULL(54) 388 #define DTE_FLAG_GV BIT_ULL(55) 389 #define DTE_GLX_SHIFT (56) 390 #define DTE_GLX_MASK (3) 391 #define DTE_FLAG_IR BIT_ULL(61) 392 #define DTE_FLAG_IW BIT_ULL(62) 393 394 #define DTE_FLAG_IOTLB BIT_ULL(32) 395 #define DTE_FLAG_MASK (0x3ffULL << 32) 396 #define DEV_DOMID_MASK 0xffffULL 397 398 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) 399 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) 400 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL) 401 402 #define DTE_GCR3_INDEX_A 0 403 #define DTE_GCR3_INDEX_B 1 404 #define DTE_GCR3_INDEX_C 1 405 406 #define DTE_GCR3_SHIFT_A 58 407 #define DTE_GCR3_SHIFT_B 16 408 #define DTE_GCR3_SHIFT_C 43 409 410 #define DTE_GPT_LEVEL_SHIFT 54 411 412 #define GCR3_VALID 0x01ULL 413 414 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) 415 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR) 416 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK)) 417 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) 418 419 #define IOMMU_PROT_MASK 0x03 420 #define IOMMU_PROT_IR 0x01 421 #define IOMMU_PROT_IW 0x02 422 423 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2) 424 425 /* IOMMU capabilities */ 426 #define IOMMU_CAP_IOTLB 24 427 #define IOMMU_CAP_NPCACHE 26 428 #define IOMMU_CAP_EFR 27 429 430 /* IOMMU IVINFO */ 431 #define IOMMU_IVINFO_OFFSET 36 432 #define IOMMU_IVINFO_EFRSUP BIT(0) 433 #define IOMMU_IVINFO_DMA_REMAP BIT(1) 434 435 /* IOMMU Feature Reporting Field (for IVHD type 10h */ 436 #define IOMMU_FEAT_GASUP_SHIFT 6 437 438 /* IOMMU Extended Feature Register (EFR) */ 439 #define IOMMU_EFR_XTSUP_SHIFT 2 440 #define IOMMU_EFR_GASUP_SHIFT 7 441 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46 442 443 #define MAX_DOMAIN_ID 65536 444 445 /* Protection domain flags */ 446 #define PD_DMA_OPS_MASK BIT(0) /* domain used for dma_ops */ 447 #define PD_DEFAULT_MASK BIT(1) /* domain is a default dma_ops 448 domain for an IOMMU */ 449 #define PD_PASSTHROUGH_MASK BIT(2) /* domain has no page 450 translation */ 451 #define PD_IOMMUV2_MASK BIT(3) /* domain has gcr3 table */ 452 #define PD_GIOV_MASK BIT(4) /* domain enable GIOV support */ 453 454 extern bool amd_iommu_dump; 455 #define DUMP_printk(format, arg...) \ 456 do { \ 457 if (amd_iommu_dump) \ 458 pr_info("AMD-Vi: " format, ## arg); \ 459 } while(0); 460 461 /* global flag if IOMMUs cache non-present entries */ 462 extern bool amd_iommu_np_cache; 463 /* Only true if all IOMMUs support device IOTLBs */ 464 extern bool amd_iommu_iotlb_sup; 465 466 struct irq_remap_table { 467 raw_spinlock_t lock; 468 unsigned min_index; 469 u32 *table; 470 }; 471 472 /* Interrupt remapping feature used? */ 473 extern bool amd_iommu_irq_remap; 474 475 extern const struct iommu_ops amd_iommu_ops; 476 477 /* IVRS indicates that pre-boot remapping was enabled */ 478 extern bool amdr_ivrs_remap_support; 479 480 /* kmem_cache to get tables with 128 byte alignement */ 481 extern struct kmem_cache *amd_iommu_irq_cache; 482 483 #define PCI_SBDF_TO_SEGID(sbdf) (((sbdf) >> 16) & 0xffff) 484 #define PCI_SBDF_TO_DEVID(sbdf) ((sbdf) & 0xffff) 485 #define PCI_SEG_DEVID_TO_SBDF(seg, devid) ((((u32)(seg) & 0xffff) << 16) | \ 486 ((devid) & 0xffff)) 487 488 /* Make iterating over all pci segment easier */ 489 #define for_each_pci_segment(pci_seg) \ 490 list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list) 491 #define for_each_pci_segment_safe(pci_seg, next) \ 492 list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list) 493 /* 494 * Make iterating over all IOMMUs easier 495 */ 496 #define for_each_iommu(iommu) \ 497 list_for_each_entry((iommu), &amd_iommu_list, list) 498 #define for_each_iommu_safe(iommu, next) \ 499 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) 500 501 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ 502 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) 503 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) 504 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ 505 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) 506 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) 507 508 /* 509 * This struct is used to pass information about 510 * incoming PPR faults around. 511 */ 512 struct amd_iommu_fault { 513 u64 address; /* IO virtual address of the fault*/ 514 u32 pasid; /* Address space identifier */ 515 u32 sbdf; /* Originating PCI device id */ 516 u16 tag; /* PPR tag */ 517 u16 flags; /* Fault flags */ 518 519 }; 520 521 522 struct amd_iommu; 523 struct iommu_domain; 524 struct irq_domain; 525 struct amd_irte_ops; 526 527 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0) 528 529 #define io_pgtable_to_data(x) \ 530 container_of((x), struct amd_io_pgtable, iop) 531 532 #define io_pgtable_ops_to_data(x) \ 533 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) 534 535 #define io_pgtable_ops_to_domain(x) \ 536 container_of(io_pgtable_ops_to_data(x), \ 537 struct protection_domain, iop) 538 539 #define io_pgtable_cfg_to_data(x) \ 540 container_of((x), struct amd_io_pgtable, pgtbl_cfg) 541 542 struct amd_io_pgtable { 543 struct io_pgtable_cfg pgtbl_cfg; 544 struct io_pgtable iop; 545 int mode; 546 u64 *root; 547 atomic64_t pt_root; /* pgtable root and pgtable mode */ 548 u64 *pgd; /* v2 pgtable pgd pointer */ 549 }; 550 551 /* 552 * This structure contains generic data for IOMMU protection domains 553 * independent of their use. 554 */ 555 struct protection_domain { 556 struct list_head dev_list; /* List of all devices in this domain */ 557 struct iommu_domain domain; /* generic domain handle used by 558 iommu core code */ 559 struct amd_io_pgtable iop; 560 spinlock_t lock; /* mostly used to lock the page table*/ 561 u16 id; /* the domain id written to the device table */ 562 int glx; /* Number of levels for GCR3 table */ 563 int nid; /* Node ID */ 564 u64 *gcr3_tbl; /* Guest CR3 table */ 565 unsigned long flags; /* flags to find out type of domain */ 566 unsigned dev_cnt; /* devices assigned to this domain */ 567 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ 568 }; 569 570 /* 571 * This structure contains information about one PCI segment in the system. 572 */ 573 struct amd_iommu_pci_seg { 574 /* List with all PCI segments in the system */ 575 struct list_head list; 576 577 /* List of all available dev_data structures */ 578 struct llist_head dev_data_list; 579 580 /* PCI segment number */ 581 u16 id; 582 583 /* Largest PCI device id we expect translation requests for */ 584 u16 last_bdf; 585 586 /* Size of the device table */ 587 u32 dev_table_size; 588 589 /* Size of the alias table */ 590 u32 alias_table_size; 591 592 /* Size of the rlookup table */ 593 u32 rlookup_table_size; 594 595 /* 596 * device table virtual address 597 * 598 * Pointer to the per PCI segment device table. 599 * It is indexed by the PCI device id or the HT unit id and contains 600 * information about the domain the device belongs to as well as the 601 * page table root pointer. 602 */ 603 struct dev_table_entry *dev_table; 604 605 /* 606 * The rlookup iommu table is used to find the IOMMU which is 607 * responsible for a specific device. It is indexed by the PCI 608 * device id. 609 */ 610 struct amd_iommu **rlookup_table; 611 612 /* 613 * This table is used to find the irq remapping table for a given 614 * device id quickly. 615 */ 616 struct irq_remap_table **irq_lookup_table; 617 618 /* 619 * Pointer to a device table which the content of old device table 620 * will be copied to. It's only be used in kdump kernel. 621 */ 622 struct dev_table_entry *old_dev_tbl_cpy; 623 624 /* 625 * The alias table is a driver specific data structure which contains the 626 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 627 * More than one device can share the same requestor id. 628 */ 629 u16 *alias_table; 630 631 /* 632 * A list of required unity mappings we find in ACPI. It is not locked 633 * because as runtime it is only read. It is created at ACPI table 634 * parsing time. 635 */ 636 struct list_head unity_map; 637 }; 638 639 /* 640 * Structure where we save information about one hardware AMD IOMMU in the 641 * system. 642 */ 643 struct amd_iommu { 644 struct list_head list; 645 646 /* Index within the IOMMU array */ 647 int index; 648 649 /* locks the accesses to the hardware */ 650 raw_spinlock_t lock; 651 652 /* Pointer to PCI device of this IOMMU */ 653 struct pci_dev *dev; 654 655 /* Cache pdev to root device for resume quirks */ 656 struct pci_dev *root_pdev; 657 658 /* physical address of MMIO space */ 659 u64 mmio_phys; 660 661 /* physical end address of MMIO space */ 662 u64 mmio_phys_end; 663 664 /* virtual address of MMIO space */ 665 u8 __iomem *mmio_base; 666 667 /* capabilities of that IOMMU read from ACPI */ 668 u32 cap; 669 670 /* flags read from acpi table */ 671 u8 acpi_flags; 672 673 /* Extended features */ 674 u64 features; 675 676 /* Extended features 2 */ 677 u64 features2; 678 679 /* IOMMUv2 */ 680 bool is_iommu_v2; 681 682 /* PCI device id of the IOMMU device */ 683 u16 devid; 684 685 /* 686 * Capability pointer. There could be more than one IOMMU per PCI 687 * device function if there are more than one AMD IOMMU capability 688 * pointers. 689 */ 690 u16 cap_ptr; 691 692 /* pci domain of this IOMMU */ 693 struct amd_iommu_pci_seg *pci_seg; 694 695 /* start of exclusion range of that IOMMU */ 696 u64 exclusion_start; 697 /* length of exclusion range of that IOMMU */ 698 u64 exclusion_length; 699 700 /* command buffer virtual address */ 701 u8 *cmd_buf; 702 u32 cmd_buf_head; 703 u32 cmd_buf_tail; 704 705 /* event buffer virtual address */ 706 u8 *evt_buf; 707 708 /* Name for event log interrupt */ 709 unsigned char evt_irq_name[16]; 710 711 /* Base of the PPR log, if present */ 712 u8 *ppr_log; 713 714 /* Name for PPR log interrupt */ 715 unsigned char ppr_irq_name[16]; 716 717 /* Base of the GA log, if present */ 718 u8 *ga_log; 719 720 /* Name for GA log interrupt */ 721 unsigned char ga_irq_name[16]; 722 723 /* Tail of the GA log, if present */ 724 u8 *ga_log_tail; 725 726 /* true if interrupts for this IOMMU are already enabled */ 727 bool int_enabled; 728 729 /* if one, we need to send a completion wait command */ 730 bool need_sync; 731 732 /* true if disable irte caching */ 733 bool irtcachedis_enabled; 734 735 /* Handle for IOMMU core code */ 736 struct iommu_device iommu; 737 738 /* 739 * We can't rely on the BIOS to restore all values on reinit, so we 740 * need to stash them 741 */ 742 743 /* The iommu BAR */ 744 u32 stored_addr_lo; 745 u32 stored_addr_hi; 746 747 /* 748 * Each iommu has 6 l1s, each of which is documented as having 0x12 749 * registers 750 */ 751 u32 stored_l1[6][0x12]; 752 753 /* The l2 indirect registers */ 754 u32 stored_l2[0x83]; 755 756 /* The maximum PC banks and counters/bank (PCSup=1) */ 757 u8 max_banks; 758 u8 max_counters; 759 #ifdef CONFIG_IRQ_REMAP 760 struct irq_domain *ir_domain; 761 762 struct amd_irte_ops *irte_ops; 763 #endif 764 765 u32 flags; 766 volatile u64 *cmd_sem; 767 atomic64_t cmd_sem_val; 768 769 #ifdef CONFIG_AMD_IOMMU_DEBUGFS 770 /* DebugFS Info */ 771 struct dentry *debugfs; 772 #endif 773 }; 774 775 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) 776 { 777 struct iommu_device *iommu = dev_to_iommu_device(dev); 778 779 return container_of(iommu, struct amd_iommu, iommu); 780 } 781 782 #define ACPIHID_UID_LEN 256 783 #define ACPIHID_HID_LEN 9 784 785 struct acpihid_map_entry { 786 struct list_head list; 787 u8 uid[ACPIHID_UID_LEN]; 788 u8 hid[ACPIHID_HID_LEN]; 789 u32 devid; 790 u32 root_devid; 791 bool cmd_line; 792 struct iommu_group *group; 793 }; 794 795 struct devid_map { 796 struct list_head list; 797 u8 id; 798 u32 devid; 799 bool cmd_line; 800 }; 801 802 /* 803 * This struct contains device specific data for the IOMMU 804 */ 805 struct iommu_dev_data { 806 /*Protect against attach/detach races */ 807 spinlock_t lock; 808 809 struct list_head list; /* For domain->dev_list */ 810 struct llist_node dev_data_list; /* For global dev_data_list */ 811 struct protection_domain *domain; /* Domain the device is bound to */ 812 struct device *dev; 813 u16 devid; /* PCI Device ID */ 814 bool iommu_v2; /* Device can make use of IOMMUv2 */ 815 struct { 816 bool enabled; 817 int qdep; 818 } ats; /* ATS state */ 819 bool pri_tlp; /* PASID TLB required for 820 PPR completions */ 821 bool use_vapic; /* Enable device to use vapic mode */ 822 bool defer_attach; 823 824 struct ratelimit_state rs; /* Ratelimit IOPF messages */ 825 }; 826 827 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ 828 extern struct list_head ioapic_map; 829 extern struct list_head hpet_map; 830 extern struct list_head acpihid_map; 831 832 /* 833 * List with all PCI segments in the system. This list is not locked because 834 * it is only written at driver initialization time 835 */ 836 extern struct list_head amd_iommu_pci_seg_list; 837 838 /* 839 * List with all IOMMUs in the system. This list is not locked because it is 840 * only written and read at driver initialization or suspend time 841 */ 842 extern struct list_head amd_iommu_list; 843 844 /* 845 * Array with pointers to each IOMMU struct 846 * The indices are referenced in the protection domains 847 */ 848 extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; 849 850 /* 851 * Structure defining one entry in the device table 852 */ 853 struct dev_table_entry { 854 u64 data[4]; 855 }; 856 857 /* 858 * One entry for unity mappings parsed out of the ACPI table. 859 */ 860 struct unity_map_entry { 861 struct list_head list; 862 863 /* starting device id this entry is used for (including) */ 864 u16 devid_start; 865 /* end device id this entry is used for (including) */ 866 u16 devid_end; 867 868 /* start address to unity map (including) */ 869 u64 address_start; 870 /* end address to unity map (including) */ 871 u64 address_end; 872 873 /* required protection */ 874 int prot; 875 }; 876 877 /* 878 * Data structures for device handling 879 */ 880 881 /* size of the dma_ops aperture as power of 2 */ 882 extern unsigned amd_iommu_aperture_order; 883 884 /* allocation bitmap for domain ids */ 885 extern unsigned long *amd_iommu_pd_alloc_bitmap; 886 887 /* Smallest max PASID supported by any IOMMU in the system */ 888 extern u32 amd_iommu_max_pasid; 889 890 extern bool amd_iommu_v2_present; 891 892 extern bool amd_iommu_force_isolation; 893 894 /* Max levels of glxval supported */ 895 extern int amd_iommu_max_glx_val; 896 897 /* 898 * This function flushes all internal caches of 899 * the IOMMU used by this driver. 900 */ 901 void iommu_flush_all_caches(struct amd_iommu *iommu); 902 903 static inline int get_ioapic_devid(int id) 904 { 905 struct devid_map *entry; 906 907 list_for_each_entry(entry, &ioapic_map, list) { 908 if (entry->id == id) 909 return entry->devid; 910 } 911 912 return -EINVAL; 913 } 914 915 static inline int get_hpet_devid(int id) 916 { 917 struct devid_map *entry; 918 919 list_for_each_entry(entry, &hpet_map, list) { 920 if (entry->id == id) 921 return entry->devid; 922 } 923 924 return -EINVAL; 925 } 926 927 enum amd_iommu_intr_mode_type { 928 AMD_IOMMU_GUEST_IR_LEGACY, 929 930 /* This mode is not visible to users. It is used when 931 * we cannot fully enable vAPIC and fallback to only support 932 * legacy interrupt remapping via 128-bit IRTE. 933 */ 934 AMD_IOMMU_GUEST_IR_LEGACY_GA, 935 AMD_IOMMU_GUEST_IR_VAPIC, 936 }; 937 938 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \ 939 x == AMD_IOMMU_GUEST_IR_LEGACY_GA) 940 941 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) 942 943 union irte { 944 u32 val; 945 struct { 946 u32 valid : 1, 947 no_fault : 1, 948 int_type : 3, 949 rq_eoi : 1, 950 dm : 1, 951 rsvd_1 : 1, 952 destination : 8, 953 vector : 8, 954 rsvd_2 : 8; 955 } fields; 956 }; 957 958 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff) 959 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff) 960 961 union irte_ga_lo { 962 u64 val; 963 964 /* For int remapping */ 965 struct { 966 u64 valid : 1, 967 no_fault : 1, 968 /* ------ */ 969 int_type : 3, 970 rq_eoi : 1, 971 dm : 1, 972 /* ------ */ 973 guest_mode : 1, 974 destination : 24, 975 ga_tag : 32; 976 } fields_remap; 977 978 /* For guest vAPIC */ 979 struct { 980 u64 valid : 1, 981 no_fault : 1, 982 /* ------ */ 983 ga_log_intr : 1, 984 rsvd1 : 3, 985 is_run : 1, 986 /* ------ */ 987 guest_mode : 1, 988 destination : 24, 989 ga_tag : 32; 990 } fields_vapic; 991 }; 992 993 union irte_ga_hi { 994 u64 val; 995 struct { 996 u64 vector : 8, 997 rsvd_1 : 4, 998 ga_root_ptr : 40, 999 rsvd_2 : 4, 1000 destination : 8; 1001 } fields; 1002 }; 1003 1004 struct irte_ga { 1005 union { 1006 struct { 1007 union irte_ga_lo lo; 1008 union irte_ga_hi hi; 1009 }; 1010 u128 irte; 1011 }; 1012 }; 1013 1014 struct irq_2_irte { 1015 u16 devid; /* Device ID for IRTE table */ 1016 u16 index; /* Index into IRTE table*/ 1017 }; 1018 1019 struct amd_ir_data { 1020 u32 cached_ga_tag; 1021 struct amd_iommu *iommu; 1022 struct irq_2_irte irq_2_irte; 1023 struct msi_msg msi_entry; 1024 void *entry; /* Pointer to union irte or struct irte_ga */ 1025 1026 /** 1027 * Store information for activate/de-activate 1028 * Guest virtual APIC mode during runtime. 1029 */ 1030 struct irq_cfg *cfg; 1031 int ga_vector; 1032 u64 ga_root_ptr; 1033 u32 ga_tag; 1034 }; 1035 1036 struct amd_irte_ops { 1037 void (*prepare)(void *, u32, bool, u8, u32, int); 1038 void (*activate)(struct amd_iommu *iommu, void *, u16, u16); 1039 void (*deactivate)(struct amd_iommu *iommu, void *, u16, u16); 1040 void (*set_affinity)(struct amd_iommu *iommu, void *, u16, u16, u8, u32); 1041 void *(*get)(struct irq_remap_table *, int); 1042 void (*set_allocated)(struct irq_remap_table *, int); 1043 bool (*is_allocated)(struct irq_remap_table *, int); 1044 void (*clear_allocated)(struct irq_remap_table *, int); 1045 }; 1046 1047 #ifdef CONFIG_IRQ_REMAP 1048 extern struct amd_irte_ops irte_32_ops; 1049 extern struct amd_irte_ops irte_128_ops; 1050 #endif 1051 1052 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ 1053