1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H 9 #define _ASM_X86_AMD_IOMMU_TYPES_H 10 11 #include <linux/types.h> 12 #include <linux/mutex.h> 13 #include <linux/msi.h> 14 #include <linux/list.h> 15 #include <linux/spinlock.h> 16 #include <linux/pci.h> 17 #include <linux/irqreturn.h> 18 #include <linux/io-pgtable.h> 19 20 /* 21 * Maximum number of IOMMUs supported 22 */ 23 #define MAX_IOMMUS 32 24 25 /* 26 * some size calculation constants 27 */ 28 #define DEV_TABLE_ENTRY_SIZE 32 29 #define ALIAS_TABLE_ENTRY_SIZE 2 30 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) 31 32 /* Capability offsets used by the driver */ 33 #define MMIO_CAP_HDR_OFFSET 0x00 34 #define MMIO_RANGE_OFFSET 0x0c 35 #define MMIO_MISC_OFFSET 0x10 36 37 /* Masks, shifts and macros to parse the device range capability */ 38 #define MMIO_RANGE_LD_MASK 0xff000000 39 #define MMIO_RANGE_FD_MASK 0x00ff0000 40 #define MMIO_RANGE_BUS_MASK 0x0000ff00 41 #define MMIO_RANGE_LD_SHIFT 24 42 #define MMIO_RANGE_FD_SHIFT 16 43 #define MMIO_RANGE_BUS_SHIFT 8 44 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) 45 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) 46 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) 47 #define MMIO_MSI_NUM(x) ((x) & 0x1f) 48 49 /* Flag masks for the AMD IOMMU exclusion range */ 50 #define MMIO_EXCL_ENABLE_MASK 0x01ULL 51 #define MMIO_EXCL_ALLOW_MASK 0x02ULL 52 53 /* Used offsets into the MMIO space */ 54 #define MMIO_DEV_TABLE_OFFSET 0x0000 55 #define MMIO_CMD_BUF_OFFSET 0x0008 56 #define MMIO_EVT_BUF_OFFSET 0x0010 57 #define MMIO_CONTROL_OFFSET 0x0018 58 #define MMIO_EXCL_BASE_OFFSET 0x0020 59 #define MMIO_EXCL_LIMIT_OFFSET 0x0028 60 #define MMIO_EXT_FEATURES 0x0030 61 #define MMIO_PPR_LOG_OFFSET 0x0038 62 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 63 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8 64 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C 65 #define MMIO_MSI_ADDR_HI_OFFSET 0x0160 66 #define MMIO_MSI_DATA_OFFSET 0x0164 67 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170 68 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178 69 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180 70 #define MMIO_EXT_FEATURES2 0x01A0 71 #define MMIO_CMD_HEAD_OFFSET 0x2000 72 #define MMIO_CMD_TAIL_OFFSET 0x2008 73 #define MMIO_EVT_HEAD_OFFSET 0x2010 74 #define MMIO_EVT_TAIL_OFFSET 0x2018 75 #define MMIO_STATUS_OFFSET 0x2020 76 #define MMIO_PPR_HEAD_OFFSET 0x2030 77 #define MMIO_PPR_TAIL_OFFSET 0x2038 78 #define MMIO_GA_HEAD_OFFSET 0x2040 79 #define MMIO_GA_TAIL_OFFSET 0x2048 80 #define MMIO_CNTR_CONF_OFFSET 0x4000 81 #define MMIO_CNTR_REG_OFFSET 0x40000 82 #define MMIO_REG_END_OFFSET 0x80000 83 84 85 86 /* Extended Feature Bits */ 87 #define FEATURE_PREFETCH (1ULL<<0) 88 #define FEATURE_PPR (1ULL<<1) 89 #define FEATURE_X2APIC (1ULL<<2) 90 #define FEATURE_NX (1ULL<<3) 91 #define FEATURE_GT (1ULL<<4) 92 #define FEATURE_IA (1ULL<<6) 93 #define FEATURE_GA (1ULL<<7) 94 #define FEATURE_HE (1ULL<<8) 95 #define FEATURE_PC (1ULL<<9) 96 #define FEATURE_GAM_VAPIC (1ULL<<21) 97 #define FEATURE_EPHSUP (1ULL<<50) 98 #define FEATURE_SNP (1ULL<<63) 99 100 #define FEATURE_PASID_SHIFT 32 101 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) 102 103 #define FEATURE_GLXVAL_SHIFT 14 104 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) 105 106 /* Extended Feature 2 Bits */ 107 #define FEATURE_SNPAVICSUP_SHIFT 5 108 #define FEATURE_SNPAVICSUP_MASK (0x07ULL << FEATURE_SNPAVICSUP_SHIFT) 109 #define FEATURE_SNPAVICSUP_GAM(x) \ 110 ((x & FEATURE_SNPAVICSUP_MASK) >> FEATURE_SNPAVICSUP_SHIFT == 0x1) 111 112 /* Note: 113 * The current driver only support 16-bit PASID. 114 * Currently, hardware only implement upto 16-bit PASID 115 * even though the spec says it could have upto 20 bits. 116 */ 117 #define PASID_MASK 0x0000ffff 118 119 /* MMIO status bits */ 120 #define MMIO_STATUS_EVT_OVERFLOW_INT_MASK (1 << 0) 121 #define MMIO_STATUS_EVT_INT_MASK (1 << 1) 122 #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) 123 #define MMIO_STATUS_PPR_INT_MASK (1 << 6) 124 #define MMIO_STATUS_GALOG_RUN_MASK (1 << 8) 125 #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9) 126 #define MMIO_STATUS_GALOG_INT_MASK (1 << 10) 127 128 /* event logging constants */ 129 #define EVENT_ENTRY_SIZE 0x10 130 #define EVENT_TYPE_SHIFT 28 131 #define EVENT_TYPE_MASK 0xf 132 #define EVENT_TYPE_ILL_DEV 0x1 133 #define EVENT_TYPE_IO_FAULT 0x2 134 #define EVENT_TYPE_DEV_TAB_ERR 0x3 135 #define EVENT_TYPE_PAGE_TAB_ERR 0x4 136 #define EVENT_TYPE_ILL_CMD 0x5 137 #define EVENT_TYPE_CMD_HARD_ERR 0x6 138 #define EVENT_TYPE_IOTLB_INV_TO 0x7 139 #define EVENT_TYPE_INV_DEV_REQ 0x8 140 #define EVENT_TYPE_INV_PPR_REQ 0x9 141 #define EVENT_TYPE_RMP_FAULT 0xd 142 #define EVENT_TYPE_RMP_HW_ERR 0xe 143 #define EVENT_DEVID_MASK 0xffff 144 #define EVENT_DEVID_SHIFT 0 145 #define EVENT_DOMID_MASK_LO 0xffff 146 #define EVENT_DOMID_MASK_HI 0xf0000 147 #define EVENT_FLAGS_MASK 0xfff 148 #define EVENT_FLAGS_SHIFT 0x10 149 #define EVENT_FLAG_RW 0x020 150 #define EVENT_FLAG_I 0x008 151 152 /* feature control bits */ 153 #define CONTROL_IOMMU_EN 0 154 #define CONTROL_HT_TUN_EN 1 155 #define CONTROL_EVT_LOG_EN 2 156 #define CONTROL_EVT_INT_EN 3 157 #define CONTROL_COMWAIT_EN 4 158 #define CONTROL_INV_TIMEOUT 5 159 #define CONTROL_PASSPW_EN 8 160 #define CONTROL_RESPASSPW_EN 9 161 #define CONTROL_COHERENT_EN 10 162 #define CONTROL_ISOC_EN 11 163 #define CONTROL_CMDBUF_EN 12 164 #define CONTROL_PPRLOG_EN 13 165 #define CONTROL_PPRINT_EN 14 166 #define CONTROL_PPR_EN 15 167 #define CONTROL_GT_EN 16 168 #define CONTROL_GA_EN 17 169 #define CONTROL_GAM_EN 25 170 #define CONTROL_GALOG_EN 28 171 #define CONTROL_GAINT_EN 29 172 #define CONTROL_XT_EN 50 173 #define CONTROL_INTCAPXT_EN 51 174 #define CONTROL_SNPAVIC_EN 61 175 176 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) 177 #define CTRL_INV_TO_NONE 0 178 #define CTRL_INV_TO_1MS 1 179 #define CTRL_INV_TO_10MS 2 180 #define CTRL_INV_TO_100MS 3 181 #define CTRL_INV_TO_1S 4 182 #define CTRL_INV_TO_10S 5 183 #define CTRL_INV_TO_100S 6 184 185 /* command specific defines */ 186 #define CMD_COMPL_WAIT 0x01 187 #define CMD_INV_DEV_ENTRY 0x02 188 #define CMD_INV_IOMMU_PAGES 0x03 189 #define CMD_INV_IOTLB_PAGES 0x04 190 #define CMD_INV_IRT 0x05 191 #define CMD_COMPLETE_PPR 0x07 192 #define CMD_INV_ALL 0x08 193 194 #define CMD_COMPL_WAIT_STORE_MASK 0x01 195 #define CMD_COMPL_WAIT_INT_MASK 0x02 196 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 197 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 198 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 199 200 #define PPR_STATUS_MASK 0xf 201 #define PPR_STATUS_SHIFT 12 202 203 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL 204 205 /* macros and definitions for device table entries */ 206 #define DEV_ENTRY_VALID 0x00 207 #define DEV_ENTRY_TRANSLATION 0x01 208 #define DEV_ENTRY_PPR 0x34 209 #define DEV_ENTRY_IR 0x3d 210 #define DEV_ENTRY_IW 0x3e 211 #define DEV_ENTRY_NO_PAGE_FAULT 0x62 212 #define DEV_ENTRY_EX 0x67 213 #define DEV_ENTRY_SYSMGT1 0x68 214 #define DEV_ENTRY_SYSMGT2 0x69 215 #define DEV_ENTRY_IRQ_TBL_EN 0x80 216 #define DEV_ENTRY_INIT_PASS 0xb8 217 #define DEV_ENTRY_EINT_PASS 0xb9 218 #define DEV_ENTRY_NMI_PASS 0xba 219 #define DEV_ENTRY_LINT0_PASS 0xbe 220 #define DEV_ENTRY_LINT1_PASS 0xbf 221 #define DEV_ENTRY_MODE_MASK 0x07 222 #define DEV_ENTRY_MODE_SHIFT 0x09 223 224 #define MAX_DEV_TABLE_ENTRIES 0xffff 225 226 /* constants to configure the command buffer */ 227 #define CMD_BUFFER_SIZE 8192 228 #define CMD_BUFFER_UNINITIALIZED 1 229 #define CMD_BUFFER_ENTRIES 512 230 #define MMIO_CMD_SIZE_SHIFT 56 231 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) 232 233 /* constants for event buffer handling */ 234 #define EVT_BUFFER_SIZE 8192 /* 512 entries */ 235 #define EVT_LEN_MASK (0x9ULL << 56) 236 237 /* Constants for PPR Log handling */ 238 #define PPR_LOG_ENTRIES 512 239 #define PPR_LOG_SIZE_SHIFT 56 240 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) 241 #define PPR_ENTRY_SIZE 16 242 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) 243 244 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) 245 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) 246 #define PPR_DEVID(x) ((x) & 0xffffULL) 247 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) 248 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) 249 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) 250 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) 251 252 #define PPR_REQ_FAULT 0x01 253 254 /* Constants for GA Log handling */ 255 #define GA_LOG_ENTRIES 512 256 #define GA_LOG_SIZE_SHIFT 56 257 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT) 258 #define GA_ENTRY_SIZE 8 259 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES) 260 261 #define GA_TAG(x) (u32)(x & 0xffffffffULL) 262 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL) 263 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL) 264 265 #define GA_GUEST_NR 0x1 266 267 #define IOMMU_IN_ADDR_BIT_SIZE 52 268 #define IOMMU_OUT_ADDR_BIT_SIZE 52 269 270 /* 271 * This bitmap is used to advertise the page sizes our hardware support 272 * to the IOMMU core, which will then use this information to split 273 * physically contiguous memory regions it is mapping into page sizes 274 * that we support. 275 * 276 * 512GB Pages are not supported due to a hardware bug 277 */ 278 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) 279 280 /* Bit value definition for dte irq remapping fields*/ 281 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) 282 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60) 283 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) 284 #define DTE_IRQ_REMAP_ENABLE 1ULL 285 286 /* 287 * AMD IOMMU hardware only support 512 IRTEs despite 288 * the architectural limitation of 2048 entries. 289 */ 290 #define DTE_INTTAB_ALIGNMENT 128 291 #define DTE_INTTABLEN_VALUE 9ULL 292 #define DTE_INTTABLEN (DTE_INTTABLEN_VALUE << 1) 293 #define DTE_INTTABLEN_MASK (0xfULL << 1) 294 #define MAX_IRQS_PER_TABLE (1 << DTE_INTTABLEN_VALUE) 295 296 #define PAGE_MODE_NONE 0x00 297 #define PAGE_MODE_1_LEVEL 0x01 298 #define PAGE_MODE_2_LEVEL 0x02 299 #define PAGE_MODE_3_LEVEL 0x03 300 #define PAGE_MODE_4_LEVEL 0x04 301 #define PAGE_MODE_5_LEVEL 0x05 302 #define PAGE_MODE_6_LEVEL 0x06 303 #define PAGE_MODE_7_LEVEL 0x07 304 305 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) 306 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ 307 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ 308 (0xffffffffffffffffULL)) 309 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) 310 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) 311 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ 312 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW) 313 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) 314 315 #define PM_MAP_4k 0 316 #define PM_ADDR_MASK 0x000ffffffffff000ULL 317 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ 318 (~((1ULL << (12 + ((lvl) * 9))) - 1))) 319 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) 320 321 /* 322 * Returns the page table level to use for a given page size 323 * Pagesize is expected to be a power-of-two 324 */ 325 #define PAGE_SIZE_LEVEL(pagesize) \ 326 ((__ffs(pagesize) - 12) / 9) 327 /* 328 * Returns the number of ptes to use for a given page size 329 * Pagesize is expected to be a power-of-two 330 */ 331 #define PAGE_SIZE_PTE_COUNT(pagesize) \ 332 (1ULL << ((__ffs(pagesize) - 12) % 9)) 333 334 /* 335 * Aligns a given io-virtual address to a given page size 336 * Pagesize is expected to be a power-of-two 337 */ 338 #define PAGE_SIZE_ALIGN(address, pagesize) \ 339 ((address) & ~((pagesize) - 1)) 340 /* 341 * Creates an IOMMU PTE for an address and a given pagesize 342 * The PTE has no permission bits set 343 * Pagesize is expected to be a power-of-two larger than 4096 344 */ 345 #define PAGE_SIZE_PTE(address, pagesize) \ 346 (((address) | ((pagesize) - 1)) & \ 347 (~(pagesize >> 1)) & PM_ADDR_MASK) 348 349 /* 350 * Takes a PTE value with mode=0x07 and returns the page size it maps 351 */ 352 #define PTE_PAGE_SIZE(pte) \ 353 (1ULL << (1 + ffz(((pte) | 0xfffULL)))) 354 355 /* 356 * Takes a page-table level and returns the default page-size for this level 357 */ 358 #define PTE_LEVEL_PAGE_SIZE(level) \ 359 (1ULL << (12 + (9 * (level)))) 360 361 /* 362 * Bit value definition for I/O PTE fields 363 */ 364 #define IOMMU_PTE_PR (1ULL << 0) 365 #define IOMMU_PTE_U (1ULL << 59) 366 #define IOMMU_PTE_FC (1ULL << 60) 367 #define IOMMU_PTE_IR (1ULL << 61) 368 #define IOMMU_PTE_IW (1ULL << 62) 369 370 /* 371 * Bit value definition for DTE fields 372 */ 373 #define DTE_FLAG_V (1ULL << 0) 374 #define DTE_FLAG_TV (1ULL << 1) 375 #define DTE_FLAG_IR (1ULL << 61) 376 #define DTE_FLAG_IW (1ULL << 62) 377 378 #define DTE_FLAG_IOTLB (1ULL << 32) 379 #define DTE_FLAG_GV (1ULL << 55) 380 #define DTE_FLAG_MASK (0x3ffULL << 32) 381 #define DTE_GLX_SHIFT (56) 382 #define DTE_GLX_MASK (3) 383 #define DEV_DOMID_MASK 0xffffULL 384 385 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) 386 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) 387 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL) 388 389 #define DTE_GCR3_INDEX_A 0 390 #define DTE_GCR3_INDEX_B 1 391 #define DTE_GCR3_INDEX_C 1 392 393 #define DTE_GCR3_SHIFT_A 58 394 #define DTE_GCR3_SHIFT_B 16 395 #define DTE_GCR3_SHIFT_C 43 396 397 #define GCR3_VALID 0x01ULL 398 399 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) 400 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR) 401 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK)) 402 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) 403 404 #define IOMMU_PROT_MASK 0x03 405 #define IOMMU_PROT_IR 0x01 406 #define IOMMU_PROT_IW 0x02 407 408 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2) 409 410 /* IOMMU capabilities */ 411 #define IOMMU_CAP_IOTLB 24 412 #define IOMMU_CAP_NPCACHE 26 413 #define IOMMU_CAP_EFR 27 414 415 /* IOMMU IVINFO */ 416 #define IOMMU_IVINFO_OFFSET 36 417 #define IOMMU_IVINFO_EFRSUP BIT(0) 418 #define IOMMU_IVINFO_DMA_REMAP BIT(1) 419 420 /* IOMMU Feature Reporting Field (for IVHD type 10h */ 421 #define IOMMU_FEAT_GASUP_SHIFT 6 422 423 /* IOMMU Extended Feature Register (EFR) */ 424 #define IOMMU_EFR_XTSUP_SHIFT 2 425 #define IOMMU_EFR_GASUP_SHIFT 7 426 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46 427 428 #define MAX_DOMAIN_ID 65536 429 430 /* Protection domain flags */ 431 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ 432 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops 433 domain for an IOMMU */ 434 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page 435 translation */ 436 #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ 437 438 extern bool amd_iommu_dump; 439 #define DUMP_printk(format, arg...) \ 440 do { \ 441 if (amd_iommu_dump) \ 442 pr_info("AMD-Vi: " format, ## arg); \ 443 } while(0); 444 445 /* global flag if IOMMUs cache non-present entries */ 446 extern bool amd_iommu_np_cache; 447 /* Only true if all IOMMUs support device IOTLBs */ 448 extern bool amd_iommu_iotlb_sup; 449 450 struct irq_remap_table { 451 raw_spinlock_t lock; 452 unsigned min_index; 453 u32 *table; 454 }; 455 456 /* Interrupt remapping feature used? */ 457 extern bool amd_iommu_irq_remap; 458 459 /* IVRS indicates that pre-boot remapping was enabled */ 460 extern bool amdr_ivrs_remap_support; 461 462 /* kmem_cache to get tables with 128 byte alignement */ 463 extern struct kmem_cache *amd_iommu_irq_cache; 464 465 #define PCI_SBDF_TO_SEGID(sbdf) (((sbdf) >> 16) & 0xffff) 466 #define PCI_SBDF_TO_DEVID(sbdf) ((sbdf) & 0xffff) 467 #define PCI_SEG_DEVID_TO_SBDF(seg, devid) ((((u32)(seg) & 0xffff) << 16) | \ 468 ((devid) & 0xffff)) 469 470 /* Make iterating over all pci segment easier */ 471 #define for_each_pci_segment(pci_seg) \ 472 list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list) 473 #define for_each_pci_segment_safe(pci_seg, next) \ 474 list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list) 475 /* 476 * Make iterating over all IOMMUs easier 477 */ 478 #define for_each_iommu(iommu) \ 479 list_for_each_entry((iommu), &amd_iommu_list, list) 480 #define for_each_iommu_safe(iommu, next) \ 481 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) 482 483 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ 484 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) 485 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) 486 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ 487 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) 488 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) 489 490 /* 491 * This struct is used to pass information about 492 * incoming PPR faults around. 493 */ 494 struct amd_iommu_fault { 495 u64 address; /* IO virtual address of the fault*/ 496 u32 pasid; /* Address space identifier */ 497 u32 sbdf; /* Originating PCI device id */ 498 u16 tag; /* PPR tag */ 499 u16 flags; /* Fault flags */ 500 501 }; 502 503 504 struct amd_iommu; 505 struct iommu_domain; 506 struct irq_domain; 507 struct amd_irte_ops; 508 509 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0) 510 511 #define io_pgtable_to_data(x) \ 512 container_of((x), struct amd_io_pgtable, iop) 513 514 #define io_pgtable_ops_to_data(x) \ 515 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) 516 517 #define io_pgtable_ops_to_domain(x) \ 518 container_of(io_pgtable_ops_to_data(x), \ 519 struct protection_domain, iop) 520 521 #define io_pgtable_cfg_to_data(x) \ 522 container_of((x), struct amd_io_pgtable, pgtbl_cfg) 523 524 struct amd_io_pgtable { 525 struct io_pgtable_cfg pgtbl_cfg; 526 struct io_pgtable iop; 527 int mode; 528 u64 *root; 529 atomic64_t pt_root; /* pgtable root and pgtable mode */ 530 }; 531 532 /* 533 * This structure contains generic data for IOMMU protection domains 534 * independent of their use. 535 */ 536 struct protection_domain { 537 struct list_head dev_list; /* List of all devices in this domain */ 538 struct iommu_domain domain; /* generic domain handle used by 539 iommu core code */ 540 struct amd_io_pgtable iop; 541 spinlock_t lock; /* mostly used to lock the page table*/ 542 u16 id; /* the domain id written to the device table */ 543 int glx; /* Number of levels for GCR3 table */ 544 u64 *gcr3_tbl; /* Guest CR3 table */ 545 unsigned long flags; /* flags to find out type of domain */ 546 unsigned dev_cnt; /* devices assigned to this domain */ 547 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ 548 }; 549 550 /* 551 * This structure contains information about one PCI segment in the system. 552 */ 553 struct amd_iommu_pci_seg { 554 /* List with all PCI segments in the system */ 555 struct list_head list; 556 557 /* List of all available dev_data structures */ 558 struct llist_head dev_data_list; 559 560 /* PCI segment number */ 561 u16 id; 562 563 /* Largest PCI device id we expect translation requests for */ 564 u16 last_bdf; 565 566 /* Size of the device table */ 567 u32 dev_table_size; 568 569 /* Size of the alias table */ 570 u32 alias_table_size; 571 572 /* Size of the rlookup table */ 573 u32 rlookup_table_size; 574 575 /* 576 * device table virtual address 577 * 578 * Pointer to the per PCI segment device table. 579 * It is indexed by the PCI device id or the HT unit id and contains 580 * information about the domain the device belongs to as well as the 581 * page table root pointer. 582 */ 583 struct dev_table_entry *dev_table; 584 585 /* 586 * The rlookup iommu table is used to find the IOMMU which is 587 * responsible for a specific device. It is indexed by the PCI 588 * device id. 589 */ 590 struct amd_iommu **rlookup_table; 591 592 /* 593 * This table is used to find the irq remapping table for a given 594 * device id quickly. 595 */ 596 struct irq_remap_table **irq_lookup_table; 597 598 /* 599 * Pointer to a device table which the content of old device table 600 * will be copied to. It's only be used in kdump kernel. 601 */ 602 struct dev_table_entry *old_dev_tbl_cpy; 603 604 /* 605 * The alias table is a driver specific data structure which contains the 606 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 607 * More than one device can share the same requestor id. 608 */ 609 u16 *alias_table; 610 611 /* 612 * A list of required unity mappings we find in ACPI. It is not locked 613 * because as runtime it is only read. It is created at ACPI table 614 * parsing time. 615 */ 616 struct list_head unity_map; 617 }; 618 619 /* 620 * Structure where we save information about one hardware AMD IOMMU in the 621 * system. 622 */ 623 struct amd_iommu { 624 struct list_head list; 625 626 /* Index within the IOMMU array */ 627 int index; 628 629 /* locks the accesses to the hardware */ 630 raw_spinlock_t lock; 631 632 /* Pointer to PCI device of this IOMMU */ 633 struct pci_dev *dev; 634 635 /* Cache pdev to root device for resume quirks */ 636 struct pci_dev *root_pdev; 637 638 /* physical address of MMIO space */ 639 u64 mmio_phys; 640 641 /* physical end address of MMIO space */ 642 u64 mmio_phys_end; 643 644 /* virtual address of MMIO space */ 645 u8 __iomem *mmio_base; 646 647 /* capabilities of that IOMMU read from ACPI */ 648 u32 cap; 649 650 /* flags read from acpi table */ 651 u8 acpi_flags; 652 653 /* Extended features */ 654 u64 features; 655 656 /* Extended features 2 */ 657 u64 features2; 658 659 /* IOMMUv2 */ 660 bool is_iommu_v2; 661 662 /* PCI device id of the IOMMU device */ 663 u16 devid; 664 665 /* 666 * Capability pointer. There could be more than one IOMMU per PCI 667 * device function if there are more than one AMD IOMMU capability 668 * pointers. 669 */ 670 u16 cap_ptr; 671 672 /* pci domain of this IOMMU */ 673 struct amd_iommu_pci_seg *pci_seg; 674 675 /* start of exclusion range of that IOMMU */ 676 u64 exclusion_start; 677 /* length of exclusion range of that IOMMU */ 678 u64 exclusion_length; 679 680 /* command buffer virtual address */ 681 u8 *cmd_buf; 682 u32 cmd_buf_head; 683 u32 cmd_buf_tail; 684 685 /* event buffer virtual address */ 686 u8 *evt_buf; 687 688 /* Base of the PPR log, if present */ 689 u8 *ppr_log; 690 691 /* Base of the GA log, if present */ 692 u8 *ga_log; 693 694 /* Tail of the GA log, if present */ 695 u8 *ga_log_tail; 696 697 /* true if interrupts for this IOMMU are already enabled */ 698 bool int_enabled; 699 700 /* if one, we need to send a completion wait command */ 701 bool need_sync; 702 703 /* Handle for IOMMU core code */ 704 struct iommu_device iommu; 705 706 /* 707 * We can't rely on the BIOS to restore all values on reinit, so we 708 * need to stash them 709 */ 710 711 /* The iommu BAR */ 712 u32 stored_addr_lo; 713 u32 stored_addr_hi; 714 715 /* 716 * Each iommu has 6 l1s, each of which is documented as having 0x12 717 * registers 718 */ 719 u32 stored_l1[6][0x12]; 720 721 /* The l2 indirect registers */ 722 u32 stored_l2[0x83]; 723 724 /* The maximum PC banks and counters/bank (PCSup=1) */ 725 u8 max_banks; 726 u8 max_counters; 727 #ifdef CONFIG_IRQ_REMAP 728 struct irq_domain *ir_domain; 729 struct irq_domain *msi_domain; 730 731 struct amd_irte_ops *irte_ops; 732 #endif 733 734 u32 flags; 735 volatile u64 *cmd_sem; 736 u64 cmd_sem_val; 737 738 #ifdef CONFIG_AMD_IOMMU_DEBUGFS 739 /* DebugFS Info */ 740 struct dentry *debugfs; 741 #endif 742 }; 743 744 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) 745 { 746 struct iommu_device *iommu = dev_to_iommu_device(dev); 747 748 return container_of(iommu, struct amd_iommu, iommu); 749 } 750 751 #define ACPIHID_UID_LEN 256 752 #define ACPIHID_HID_LEN 9 753 754 struct acpihid_map_entry { 755 struct list_head list; 756 u8 uid[ACPIHID_UID_LEN]; 757 u8 hid[ACPIHID_HID_LEN]; 758 u32 devid; 759 u32 root_devid; 760 bool cmd_line; 761 struct iommu_group *group; 762 }; 763 764 struct devid_map { 765 struct list_head list; 766 u8 id; 767 u32 devid; 768 bool cmd_line; 769 }; 770 771 /* 772 * This struct contains device specific data for the IOMMU 773 */ 774 struct iommu_dev_data { 775 /*Protect against attach/detach races */ 776 spinlock_t lock; 777 778 struct list_head list; /* For domain->dev_list */ 779 struct llist_node dev_data_list; /* For global dev_data_list */ 780 struct protection_domain *domain; /* Domain the device is bound to */ 781 struct device *dev; 782 u16 devid; /* PCI Device ID */ 783 bool iommu_v2; /* Device can make use of IOMMUv2 */ 784 struct { 785 bool enabled; 786 int qdep; 787 } ats; /* ATS state */ 788 bool pri_tlp; /* PASID TLB required for 789 PPR completions */ 790 bool use_vapic; /* Enable device to use vapic mode */ 791 bool defer_attach; 792 793 struct ratelimit_state rs; /* Ratelimit IOPF messages */ 794 }; 795 796 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ 797 extern struct list_head ioapic_map; 798 extern struct list_head hpet_map; 799 extern struct list_head acpihid_map; 800 801 /* 802 * List with all PCI segments in the system. This list is not locked because 803 * it is only written at driver initialization time 804 */ 805 extern struct list_head amd_iommu_pci_seg_list; 806 807 /* 808 * List with all IOMMUs in the system. This list is not locked because it is 809 * only written and read at driver initialization or suspend time 810 */ 811 extern struct list_head amd_iommu_list; 812 813 /* 814 * Array with pointers to each IOMMU struct 815 * The indices are referenced in the protection domains 816 */ 817 extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; 818 819 /* 820 * Structure defining one entry in the device table 821 */ 822 struct dev_table_entry { 823 u64 data[4]; 824 }; 825 826 /* 827 * One entry for unity mappings parsed out of the ACPI table. 828 */ 829 struct unity_map_entry { 830 struct list_head list; 831 832 /* starting device id this entry is used for (including) */ 833 u16 devid_start; 834 /* end device id this entry is used for (including) */ 835 u16 devid_end; 836 837 /* start address to unity map (including) */ 838 u64 address_start; 839 /* end address to unity map (including) */ 840 u64 address_end; 841 842 /* required protection */ 843 int prot; 844 }; 845 846 /* 847 * Data structures for device handling 848 */ 849 850 /* size of the dma_ops aperture as power of 2 */ 851 extern unsigned amd_iommu_aperture_order; 852 853 /* allocation bitmap for domain ids */ 854 extern unsigned long *amd_iommu_pd_alloc_bitmap; 855 856 /* Smallest max PASID supported by any IOMMU in the system */ 857 extern u32 amd_iommu_max_pasid; 858 859 extern bool amd_iommu_v2_present; 860 861 extern bool amd_iommu_force_isolation; 862 863 /* Max levels of glxval supported */ 864 extern int amd_iommu_max_glx_val; 865 866 /* 867 * This function flushes all internal caches of 868 * the IOMMU used by this driver. 869 */ 870 extern void iommu_flush_all_caches(struct amd_iommu *iommu); 871 872 static inline int get_ioapic_devid(int id) 873 { 874 struct devid_map *entry; 875 876 list_for_each_entry(entry, &ioapic_map, list) { 877 if (entry->id == id) 878 return entry->devid; 879 } 880 881 return -EINVAL; 882 } 883 884 static inline int get_hpet_devid(int id) 885 { 886 struct devid_map *entry; 887 888 list_for_each_entry(entry, &hpet_map, list) { 889 if (entry->id == id) 890 return entry->devid; 891 } 892 893 return -EINVAL; 894 } 895 896 enum amd_iommu_intr_mode_type { 897 AMD_IOMMU_GUEST_IR_LEGACY, 898 899 /* This mode is not visible to users. It is used when 900 * we cannot fully enable vAPIC and fallback to only support 901 * legacy interrupt remapping via 128-bit IRTE. 902 */ 903 AMD_IOMMU_GUEST_IR_LEGACY_GA, 904 AMD_IOMMU_GUEST_IR_VAPIC, 905 }; 906 907 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \ 908 x == AMD_IOMMU_GUEST_IR_LEGACY_GA) 909 910 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) 911 912 union irte { 913 u32 val; 914 struct { 915 u32 valid : 1, 916 no_fault : 1, 917 int_type : 3, 918 rq_eoi : 1, 919 dm : 1, 920 rsvd_1 : 1, 921 destination : 8, 922 vector : 8, 923 rsvd_2 : 8; 924 } fields; 925 }; 926 927 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff) 928 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff) 929 930 union irte_ga_lo { 931 u64 val; 932 933 /* For int remapping */ 934 struct { 935 u64 valid : 1, 936 no_fault : 1, 937 /* ------ */ 938 int_type : 3, 939 rq_eoi : 1, 940 dm : 1, 941 /* ------ */ 942 guest_mode : 1, 943 destination : 24, 944 ga_tag : 32; 945 } fields_remap; 946 947 /* For guest vAPIC */ 948 struct { 949 u64 valid : 1, 950 no_fault : 1, 951 /* ------ */ 952 ga_log_intr : 1, 953 rsvd1 : 3, 954 is_run : 1, 955 /* ------ */ 956 guest_mode : 1, 957 destination : 24, 958 ga_tag : 32; 959 } fields_vapic; 960 }; 961 962 union irte_ga_hi { 963 u64 val; 964 struct { 965 u64 vector : 8, 966 rsvd_1 : 4, 967 ga_root_ptr : 40, 968 rsvd_2 : 4, 969 destination : 8; 970 } fields; 971 }; 972 973 struct irte_ga { 974 union irte_ga_lo lo; 975 union irte_ga_hi hi; 976 }; 977 978 struct irq_2_irte { 979 u16 devid; /* Device ID for IRTE table */ 980 u16 index; /* Index into IRTE table*/ 981 }; 982 983 struct amd_ir_data { 984 u32 cached_ga_tag; 985 struct amd_iommu *iommu; 986 struct irq_2_irte irq_2_irte; 987 struct msi_msg msi_entry; 988 void *entry; /* Pointer to union irte or struct irte_ga */ 989 void *ref; /* Pointer to the actual irte */ 990 991 /** 992 * Store information for activate/de-activate 993 * Guest virtual APIC mode during runtime. 994 */ 995 struct irq_cfg *cfg; 996 int ga_vector; 997 int ga_root_ptr; 998 int ga_tag; 999 }; 1000 1001 struct amd_irte_ops { 1002 void (*prepare)(void *, u32, bool, u8, u32, int); 1003 void (*activate)(struct amd_iommu *iommu, void *, u16, u16); 1004 void (*deactivate)(struct amd_iommu *iommu, void *, u16, u16); 1005 void (*set_affinity)(struct amd_iommu *iommu, void *, u16, u16, u8, u32); 1006 void *(*get)(struct irq_remap_table *, int); 1007 void (*set_allocated)(struct irq_remap_table *, int); 1008 bool (*is_allocated)(struct irq_remap_table *, int); 1009 void (*clear_allocated)(struct irq_remap_table *, int); 1010 }; 1011 1012 #ifdef CONFIG_IRQ_REMAP 1013 extern struct amd_irte_ops irte_32_ops; 1014 extern struct amd_irte_ops irte_128_ops; 1015 #endif 1016 1017 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ 1018