1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 */ 6 7 #ifndef AMD_IOMMU_H 8 #define AMD_IOMMU_H 9 10 #include <linux/iommu.h> 11 12 #include "amd_iommu_types.h" 13 14 extern int amd_iommu_init_dma_ops(void); 15 extern int amd_iommu_init_passthrough(void); 16 extern irqreturn_t amd_iommu_int_thread(int irq, void *data); 17 extern irqreturn_t amd_iommu_int_handler(int irq, void *data); 18 extern void amd_iommu_apply_erratum_63(u16 devid); 19 extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu); 20 extern int amd_iommu_init_devices(void); 21 extern void amd_iommu_uninit_devices(void); 22 extern void amd_iommu_init_notifier(void); 23 extern int amd_iommu_init_api(void); 24 25 #ifdef CONFIG_AMD_IOMMU_DEBUGFS 26 void amd_iommu_debugfs_setup(struct amd_iommu *iommu); 27 #else 28 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} 29 #endif 30 31 /* Needed for interrupt remapping */ 32 extern int amd_iommu_prepare(void); 33 extern int amd_iommu_enable(void); 34 extern void amd_iommu_disable(void); 35 extern int amd_iommu_reenable(int); 36 extern int amd_iommu_enable_faulting(void); 37 extern int amd_iommu_guest_ir; 38 extern enum io_pgtable_fmt amd_iommu_pgtable; 39 40 /* IOMMUv2 specific functions */ 41 struct iommu_domain; 42 43 extern bool amd_iommu_v2_supported(void); 44 extern struct amd_iommu *get_amd_iommu(unsigned int idx); 45 extern u8 amd_iommu_pc_get_max_banks(unsigned int idx); 46 extern bool amd_iommu_pc_supported(void); 47 extern u8 amd_iommu_pc_get_max_counters(unsigned int idx); 48 extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 49 u8 fxn, u64 *value); 50 extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 51 u8 fxn, u64 *value); 52 53 extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb); 54 extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb); 55 extern void amd_iommu_domain_direct_map(struct iommu_domain *dom); 56 extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids); 57 extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, 58 u64 address); 59 extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain); 60 extern void amd_iommu_domain_update(struct protection_domain *domain); 61 extern void amd_iommu_domain_flush_complete(struct protection_domain *domain); 62 extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain); 63 extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid); 64 extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, 65 unsigned long cr3); 66 extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid); 67 68 #ifdef CONFIG_IRQ_REMAP 69 extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu); 70 #else 71 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu) 72 { 73 return 0; 74 } 75 #endif 76 77 #define PPR_SUCCESS 0x0 78 #define PPR_INVALID 0x1 79 #define PPR_FAILURE 0xf 80 81 extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid, 82 int status, int tag); 83 84 static inline bool is_rd890_iommu(struct pci_dev *pdev) 85 { 86 return (pdev->vendor == PCI_VENDOR_ID_ATI) && 87 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU); 88 } 89 90 static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask) 91 { 92 return !!(iommu->features & mask); 93 } 94 95 static inline u64 iommu_virt_to_phys(void *vaddr) 96 { 97 return (u64)__sme_set(virt_to_phys(vaddr)); 98 } 99 100 static inline void *iommu_phys_to_virt(unsigned long paddr) 101 { 102 return phys_to_virt(__sme_clr(paddr)); 103 } 104 105 static inline 106 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root) 107 { 108 atomic64_set(&domain->iop.pt_root, root); 109 domain->iop.root = (u64 *)(root & PAGE_MASK); 110 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */ 111 } 112 113 static inline 114 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain) 115 { 116 amd_iommu_domain_set_pt_root(domain, 0); 117 } 118 119 120 extern bool translation_pre_enabled(struct amd_iommu *iommu); 121 extern bool amd_iommu_is_attach_deferred(struct iommu_domain *domain, 122 struct device *dev); 123 extern int __init add_special_device(u8 type, u8 id, u16 *devid, 124 bool cmd_line); 125 126 #ifdef CONFIG_DMI 127 void amd_iommu_apply_ivrs_quirks(void); 128 #else 129 static inline void amd_iommu_apply_ivrs_quirks(void) { } 130 #endif 131 132 extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain, 133 u64 *root, int mode); 134 #endif 135