1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 */ 6 7 #ifndef AMD_IOMMU_H 8 #define AMD_IOMMU_H 9 10 #include <linux/iommu.h> 11 12 #include "amd_iommu_types.h" 13 14 extern irqreturn_t amd_iommu_int_thread(int irq, void *data); 15 extern irqreturn_t amd_iommu_int_handler(int irq, void *data); 16 extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid); 17 extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu); 18 extern void amd_iommu_restart_ga_log(struct amd_iommu *iommu); 19 extern void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid); 20 21 #ifdef CONFIG_AMD_IOMMU_DEBUGFS 22 void amd_iommu_debugfs_setup(struct amd_iommu *iommu); 23 #else 24 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} 25 #endif 26 27 /* Needed for interrupt remapping */ 28 extern int amd_iommu_prepare(void); 29 extern int amd_iommu_enable(void); 30 extern void amd_iommu_disable(void); 31 extern int amd_iommu_reenable(int); 32 extern int amd_iommu_enable_faulting(void); 33 extern int amd_iommu_guest_ir; 34 extern enum io_pgtable_fmt amd_iommu_pgtable; 35 extern int amd_iommu_gpt_level; 36 37 /* IOMMUv2 specific functions */ 38 struct iommu_domain; 39 40 extern bool amd_iommu_v2_supported(void); 41 extern struct amd_iommu *get_amd_iommu(unsigned int idx); 42 extern u8 amd_iommu_pc_get_max_banks(unsigned int idx); 43 extern bool amd_iommu_pc_supported(void); 44 extern u8 amd_iommu_pc_get_max_counters(unsigned int idx); 45 extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 46 u8 fxn, u64 *value); 47 extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 48 u8 fxn, u64 *value); 49 50 extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb); 51 extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb); 52 extern void amd_iommu_domain_direct_map(struct iommu_domain *dom); 53 extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids); 54 extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, 55 u64 address); 56 extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain); 57 extern void amd_iommu_domain_update(struct protection_domain *domain); 58 extern void amd_iommu_domain_flush_complete(struct protection_domain *domain); 59 extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain); 60 extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid); 61 extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, 62 unsigned long cr3); 63 extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid); 64 65 #ifdef CONFIG_IRQ_REMAP 66 extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu); 67 #else 68 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu) 69 { 70 return 0; 71 } 72 #endif 73 74 #define PPR_SUCCESS 0x0 75 #define PPR_INVALID 0x1 76 #define PPR_FAILURE 0xf 77 78 extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid, 79 int status, int tag); 80 81 static inline bool is_rd890_iommu(struct pci_dev *pdev) 82 { 83 return (pdev->vendor == PCI_VENDOR_ID_ATI) && 84 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU); 85 } 86 87 static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask) 88 { 89 return !!(iommu->features & mask); 90 } 91 92 static inline u64 iommu_virt_to_phys(void *vaddr) 93 { 94 return (u64)__sme_set(virt_to_phys(vaddr)); 95 } 96 97 static inline void *iommu_phys_to_virt(unsigned long paddr) 98 { 99 return phys_to_virt(__sme_clr(paddr)); 100 } 101 102 static inline 103 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root) 104 { 105 atomic64_set(&domain->iop.pt_root, root); 106 domain->iop.root = (u64 *)(root & PAGE_MASK); 107 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */ 108 } 109 110 static inline 111 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain) 112 { 113 amd_iommu_domain_set_pt_root(domain, 0); 114 } 115 116 static inline int get_pci_sbdf_id(struct pci_dev *pdev) 117 { 118 int seg = pci_domain_nr(pdev->bus); 119 u16 devid = pci_dev_id(pdev); 120 121 return PCI_SEG_DEVID_TO_SBDF(seg, devid); 122 } 123 124 static inline void *alloc_pgtable_page(int nid, gfp_t gfp) 125 { 126 struct page *page; 127 128 page = alloc_pages_node(nid, gfp | __GFP_ZERO, 0); 129 return page ? page_address(page) : NULL; 130 } 131 132 extern bool translation_pre_enabled(struct amd_iommu *iommu); 133 extern bool amd_iommu_is_attach_deferred(struct device *dev); 134 extern int __init add_special_device(u8 type, u8 id, u32 *devid, 135 bool cmd_line); 136 137 #ifdef CONFIG_DMI 138 void amd_iommu_apply_ivrs_quirks(void); 139 #else 140 static inline void amd_iommu_apply_ivrs_quirks(void) { } 141 #endif 142 143 extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain, 144 u64 *root, int mode); 145 extern struct dev_table_entry *get_dev_table(struct amd_iommu *iommu); 146 147 extern u64 amd_iommu_efr; 148 extern u64 amd_iommu_efr2; 149 150 extern bool amd_iommu_snp_en; 151 #endif 152