1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 */ 6 7 #ifndef AMD_IOMMU_H 8 #define AMD_IOMMU_H 9 10 #include <linux/iommu.h> 11 12 #include "amd_iommu_types.h" 13 14 extern int amd_iommu_get_num_iommus(void); 15 extern int amd_iommu_init_dma_ops(void); 16 extern int amd_iommu_init_passthrough(void); 17 extern irqreturn_t amd_iommu_int_thread(int irq, void *data); 18 extern irqreturn_t amd_iommu_int_handler(int irq, void *data); 19 extern void amd_iommu_apply_erratum_63(u16 devid); 20 extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu); 21 extern int amd_iommu_init_devices(void); 22 extern void amd_iommu_uninit_devices(void); 23 extern void amd_iommu_init_notifier(void); 24 extern int amd_iommu_init_api(void); 25 26 #ifdef CONFIG_AMD_IOMMU_DEBUGFS 27 void amd_iommu_debugfs_setup(struct amd_iommu *iommu); 28 #else 29 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} 30 #endif 31 32 /* Needed for interrupt remapping */ 33 extern int amd_iommu_prepare(void); 34 extern int amd_iommu_enable(void); 35 extern void amd_iommu_disable(void); 36 extern int amd_iommu_reenable(int); 37 extern int amd_iommu_enable_faulting(void); 38 extern int amd_iommu_guest_ir; 39 extern enum io_pgtable_fmt amd_iommu_pgtable; 40 41 /* IOMMUv2 specific functions */ 42 struct iommu_domain; 43 44 extern bool amd_iommu_v2_supported(void); 45 extern struct amd_iommu *get_amd_iommu(unsigned int idx); 46 extern u8 amd_iommu_pc_get_max_banks(unsigned int idx); 47 extern bool amd_iommu_pc_supported(void); 48 extern u8 amd_iommu_pc_get_max_counters(unsigned int idx); 49 extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 50 u8 fxn, u64 *value); 51 extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 52 u8 fxn, u64 *value); 53 54 extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb); 55 extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb); 56 extern void amd_iommu_domain_direct_map(struct iommu_domain *dom); 57 extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids); 58 extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, 59 u64 address); 60 extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain); 61 extern void amd_iommu_domain_update(struct protection_domain *domain); 62 extern void amd_iommu_domain_flush_complete(struct protection_domain *domain); 63 extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain); 64 extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid); 65 extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, 66 unsigned long cr3); 67 extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid); 68 extern struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev); 69 70 #ifdef CONFIG_IRQ_REMAP 71 extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu); 72 #else 73 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu) 74 { 75 return 0; 76 } 77 #endif 78 79 #define PPR_SUCCESS 0x0 80 #define PPR_INVALID 0x1 81 #define PPR_FAILURE 0xf 82 83 extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid, 84 int status, int tag); 85 86 static inline bool is_rd890_iommu(struct pci_dev *pdev) 87 { 88 return (pdev->vendor == PCI_VENDOR_ID_ATI) && 89 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU); 90 } 91 92 static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask) 93 { 94 return !!(iommu->features & mask); 95 } 96 97 static inline u64 iommu_virt_to_phys(void *vaddr) 98 { 99 return (u64)__sme_set(virt_to_phys(vaddr)); 100 } 101 102 static inline void *iommu_phys_to_virt(unsigned long paddr) 103 { 104 return phys_to_virt(__sme_clr(paddr)); 105 } 106 107 static inline 108 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root) 109 { 110 atomic64_set(&domain->iop.pt_root, root); 111 domain->iop.root = (u64 *)(root & PAGE_MASK); 112 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */ 113 } 114 115 static inline 116 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain) 117 { 118 amd_iommu_domain_set_pt_root(domain, 0); 119 } 120 121 122 extern bool translation_pre_enabled(struct amd_iommu *iommu); 123 extern bool amd_iommu_is_attach_deferred(struct iommu_domain *domain, 124 struct device *dev); 125 extern int __init add_special_device(u8 type, u8 id, u16 *devid, 126 bool cmd_line); 127 128 #ifdef CONFIG_DMI 129 void amd_iommu_apply_ivrs_quirks(void); 130 #else 131 static inline void amd_iommu_apply_ivrs_quirks(void) { } 132 #endif 133 134 extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain, 135 u64 *root, int mode); 136 #endif 137