xref: /openbmc/linux/drivers/iommu/Kconfig (revision 20911ce6)
1ab493a0fSOhad Ben-Cohen# IOMMU_API always gets selected by whoever wants it.
2ab493a0fSOhad Ben-Cohenconfig IOMMU_API
3ab493a0fSOhad Ben-Cohen	bool
4b10f127eSOhad Ben-Cohen
568255b62SJoerg Roedelmenuconfig IOMMU_SUPPORT
668255b62SJoerg Roedel	bool "IOMMU Hardware Support"
768255b62SJoerg Roedel	default y
868255b62SJoerg Roedel	---help---
968255b62SJoerg Roedel	  Say Y here if you want to compile device drivers for IO Memory
1068255b62SJoerg Roedel	  Management Units into the kernel. These devices usually allow to
1168255b62SJoerg Roedel	  remap DMA requests and/or remap interrupts from other devices on the
1268255b62SJoerg Roedel	  system.
1368255b62SJoerg Roedel
1468255b62SJoerg Roedelif IOMMU_SUPPORT
1568255b62SJoerg Roedel
164e0ee78fSHiroshi Doyuconfig OF_IOMMU
174e0ee78fSHiroshi Doyu       def_bool y
184e0ee78fSHiroshi Doyu       depends on OF
194e0ee78fSHiroshi Doyu
20695093e3SVarun Sethiconfig FSL_PAMU
21695093e3SVarun Sethi	bool "Freescale IOMMU support"
22695093e3SVarun Sethi	depends on PPC_E500MC
23695093e3SVarun Sethi	select IOMMU_API
24695093e3SVarun Sethi	select GENERIC_ALLOCATOR
25695093e3SVarun Sethi	help
26695093e3SVarun Sethi	  Freescale PAMU support. PAMU is the IOMMU present on Freescale QorIQ platforms.
27695093e3SVarun Sethi	  PAMU can authorize memory access, remap the memory address, and remap I/O
28695093e3SVarun Sethi	  transaction types.
29695093e3SVarun Sethi
30b10f127eSOhad Ben-Cohen# MSM IOMMU support
31b10f127eSOhad Ben-Cohenconfig MSM_IOMMU
32b10f127eSOhad Ben-Cohen	bool "MSM IOMMU Support"
33b10f127eSOhad Ben-Cohen	depends on ARCH_MSM8X60 || ARCH_MSM8960
34b10f127eSOhad Ben-Cohen	select IOMMU_API
35b10f127eSOhad Ben-Cohen	help
36b10f127eSOhad Ben-Cohen	  Support for the IOMMUs found on certain Qualcomm SOCs.
37b10f127eSOhad Ben-Cohen	  These IOMMUs allow virtualization of the address space used by most
38b10f127eSOhad Ben-Cohen	  cores within the multimedia subsystem.
39b10f127eSOhad Ben-Cohen
40b10f127eSOhad Ben-Cohen	  If unsure, say N here.
41b10f127eSOhad Ben-Cohen
42b10f127eSOhad Ben-Cohenconfig IOMMU_PGTABLES_L2
43b10f127eSOhad Ben-Cohen	def_bool y
44b10f127eSOhad Ben-Cohen	depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n
4529b68415SOhad Ben-Cohen
4629b68415SOhad Ben-Cohen# AMD IOMMU support
4729b68415SOhad Ben-Cohenconfig AMD_IOMMU
4829b68415SOhad Ben-Cohen	bool "AMD IOMMU support"
4929b68415SOhad Ben-Cohen	select SWIOTLB
5029b68415SOhad Ben-Cohen	select PCI_MSI
5152815b75SJoerg Roedel	select PCI_ATS
5252815b75SJoerg Roedel	select PCI_PRI
5352815b75SJoerg Roedel	select PCI_PASID
5429b68415SOhad Ben-Cohen	select IOMMU_API
550dbc6078SThomas Petazzoni	depends on X86_64 && PCI && ACPI
5629b68415SOhad Ben-Cohen	---help---
5729b68415SOhad Ben-Cohen	  With this option you can enable support for AMD IOMMU hardware in
5829b68415SOhad Ben-Cohen	  your system. An IOMMU is a hardware component which provides
5929b68415SOhad Ben-Cohen	  remapping of DMA memory accesses from devices. With an AMD IOMMU you
6059bf8964SMasanari Iida	  can isolate the DMA memory of different devices and protect the
6129b68415SOhad Ben-Cohen	  system from misbehaving device drivers or hardware.
6229b68415SOhad Ben-Cohen
6329b68415SOhad Ben-Cohen	  You can find out if your system has an AMD IOMMU if you look into
6429b68415SOhad Ben-Cohen	  your BIOS for an option to enable it or if you have an IVRS ACPI
6529b68415SOhad Ben-Cohen	  table.
6629b68415SOhad Ben-Cohen
6729b68415SOhad Ben-Cohenconfig AMD_IOMMU_STATS
6829b68415SOhad Ben-Cohen	bool "Export AMD IOMMU statistics to debugfs"
6929b68415SOhad Ben-Cohen	depends on AMD_IOMMU
7029b68415SOhad Ben-Cohen	select DEBUG_FS
7129b68415SOhad Ben-Cohen	---help---
7229b68415SOhad Ben-Cohen	  This option enables code in the AMD IOMMU driver to collect various
7329b68415SOhad Ben-Cohen	  statistics about whats happening in the driver and exports that
7429b68415SOhad Ben-Cohen	  information to userspace via debugfs.
7529b68415SOhad Ben-Cohen	  If unsure, say N.
76166e9278SOhad Ben-Cohen
77e3c495c7SJoerg Roedelconfig AMD_IOMMU_V2
78a446e219SKees Cook	tristate "AMD IOMMU Version 2 driver"
79e5cac32cSBorislav Petkov	depends on AMD_IOMMU
808736b2c3SJoerg Roedel	select MMU_NOTIFIER
81e3c495c7SJoerg Roedel	---help---
82e3c495c7SJoerg Roedel	  This option enables support for the AMD IOMMUv2 features of the IOMMU
83e3c495c7SJoerg Roedel	  hardware. Select this option if you want to use devices that support
8459bf8964SMasanari Iida	  the PCI PRI and PASID interface.
85e3c495c7SJoerg Roedel
86166e9278SOhad Ben-Cohen# Intel IOMMU support
87d3f13810SSuresh Siddhaconfig DMAR_TABLE
88d3f13810SSuresh Siddha	bool
89d3f13810SSuresh Siddha
90d3f13810SSuresh Siddhaconfig INTEL_IOMMU
91d3f13810SSuresh Siddha	bool "Support for Intel IOMMU using DMA Remapping Devices"
92166e9278SOhad Ben-Cohen	depends on PCI_MSI && ACPI && (X86 || IA64_GENERIC)
93166e9278SOhad Ben-Cohen	select IOMMU_API
94d3f13810SSuresh Siddha	select DMAR_TABLE
95166e9278SOhad Ben-Cohen	help
96166e9278SOhad Ben-Cohen	  DMA remapping (DMAR) devices support enables independent address
97166e9278SOhad Ben-Cohen	  translations for Direct Memory Access (DMA) from devices.
98166e9278SOhad Ben-Cohen	  These DMA remapping devices are reported via ACPI tables
99166e9278SOhad Ben-Cohen	  and include PCI device scope covered by these DMA
100166e9278SOhad Ben-Cohen	  remapping devices.
101166e9278SOhad Ben-Cohen
102d3f13810SSuresh Siddhaconfig INTEL_IOMMU_DEFAULT_ON
103166e9278SOhad Ben-Cohen	def_bool y
104d3f13810SSuresh Siddha	prompt "Enable Intel DMA Remapping Devices by default"
105d3f13810SSuresh Siddha	depends on INTEL_IOMMU
106166e9278SOhad Ben-Cohen	help
107166e9278SOhad Ben-Cohen	  Selecting this option will enable a DMAR device at boot time if
108166e9278SOhad Ben-Cohen	  one is found. If this option is not selected, DMAR support can
109166e9278SOhad Ben-Cohen	  be enabled by passing intel_iommu=on to the kernel.
110166e9278SOhad Ben-Cohen
111d3f13810SSuresh Siddhaconfig INTEL_IOMMU_BROKEN_GFX_WA
112166e9278SOhad Ben-Cohen	bool "Workaround broken graphics drivers (going away soon)"
113d3f13810SSuresh Siddha	depends on INTEL_IOMMU && BROKEN && X86
114166e9278SOhad Ben-Cohen	---help---
115166e9278SOhad Ben-Cohen	  Current Graphics drivers tend to use physical address
116166e9278SOhad Ben-Cohen	  for DMA and avoid using DMA APIs. Setting this config
117166e9278SOhad Ben-Cohen	  option permits the IOMMU driver to set a unity map for
118166e9278SOhad Ben-Cohen	  all the OS-visible memory. Hence the driver can continue
119166e9278SOhad Ben-Cohen	  to use physical addresses for DMA, at least until this
120166e9278SOhad Ben-Cohen	  option is removed in the 2.6.32 kernel.
121166e9278SOhad Ben-Cohen
122d3f13810SSuresh Siddhaconfig INTEL_IOMMU_FLOPPY_WA
123166e9278SOhad Ben-Cohen	def_bool y
124d3f13810SSuresh Siddha	depends on INTEL_IOMMU && X86
125166e9278SOhad Ben-Cohen	---help---
126166e9278SOhad Ben-Cohen	  Floppy disk drivers are known to bypass DMA API calls
127166e9278SOhad Ben-Cohen	  thereby failing to work when IOMMU is enabled. This
128166e9278SOhad Ben-Cohen	  workaround will setup a 1:1 mapping for the first
129166e9278SOhad Ben-Cohen	  16MiB to make floppy (an ISA device) work.
130166e9278SOhad Ben-Cohen
131d3f13810SSuresh Siddhaconfig IRQ_REMAP
132a446e219SKees Cook	bool "Support for Interrupt Remapping"
133a446e219SKees Cook	depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI
134d3f13810SSuresh Siddha	select DMAR_TABLE
135166e9278SOhad Ben-Cohen	---help---
136166e9278SOhad Ben-Cohen	  Supports Interrupt remapping for IO-APIC and MSI devices.
137166e9278SOhad Ben-Cohen	  To use x2apic mode in the CPU's which support x2APIC enhancements or
138166e9278SOhad Ben-Cohen	  to support platforms with CPU's having > 8 bit APIC ID, say Y.
13968255b62SJoerg Roedel
140fcf3a6efSOhad Ben-Cohen# OMAP IOMMU support
141fcf3a6efSOhad Ben-Cohenconfig OMAP_IOMMU
142fcf3a6efSOhad Ben-Cohen	bool "OMAP IOMMU Support"
143ae191589SArnd Bergmann	depends on ARCH_OMAP2PLUS
144fcf3a6efSOhad Ben-Cohen	select IOMMU_API
145fcf3a6efSOhad Ben-Cohen
146fcf3a6efSOhad Ben-Cohenconfig OMAP_IOMMU_DEBUG
147baaa7b5dSLaurent Pinchart       tristate "Export OMAP IOMMU internals in DebugFS"
148baaa7b5dSLaurent Pinchart       depends on OMAP_IOMMU && DEBUG_FS
149fcf3a6efSOhad Ben-Cohen       help
150fcf3a6efSOhad Ben-Cohen         Select this to see extensive information about
151baaa7b5dSLaurent Pinchart         the internal state of OMAP IOMMU in debugfs.
152fcf3a6efSOhad Ben-Cohen
153fcf3a6efSOhad Ben-Cohen         Say N unless you know you need this.
154fcf3a6efSOhad Ben-Cohen
155d53e54b4SHiroshi DOYUconfig TEGRA_IOMMU_GART
156d53e54b4SHiroshi DOYU	bool "Tegra GART IOMMU Support"
157d53e54b4SHiroshi DOYU	depends on ARCH_TEGRA_2x_SOC
158d53e54b4SHiroshi DOYU	select IOMMU_API
159d53e54b4SHiroshi DOYU	help
160d53e54b4SHiroshi DOYU	  Enables support for remapping discontiguous physical memory
161d53e54b4SHiroshi DOYU	  shared with the operating system into contiguous I/O virtual
162d53e54b4SHiroshi DOYU	  space through the GART (Graphics Address Relocation Table)
163d53e54b4SHiroshi DOYU	  hardware included on Tegra SoCs.
164d53e54b4SHiroshi DOYU
1657a31f6f4SHiroshi DOYUconfig TEGRA_IOMMU_SMMU
16689184651SThierry Reding	bool "NVIDIA Tegra SMMU Support"
16789184651SThierry Reding	depends on ARCH_TEGRA
16889184651SThierry Reding	depends on TEGRA_AHB
16989184651SThierry Reding	depends on TEGRA_MC
1707a31f6f4SHiroshi DOYU	select IOMMU_API
1717a31f6f4SHiroshi DOYU	help
17289184651SThierry Reding	  This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
17389184651SThierry Reding	  SoCs (Tegra30 up to Tegra124).
1747a31f6f4SHiroshi DOYU
1752a96536eSKyongHo Choconfig EXYNOS_IOMMU
1762a96536eSKyongHo Cho	bool "Exynos IOMMU Support"
17720911ce6SMark Brown	depends on ARCH_EXYNOS && ARM
1782a96536eSKyongHo Cho	select IOMMU_API
1794802c1d0STushar Behera	select ARM_DMA_USE_IOMMU
1802a96536eSKyongHo Cho	help
1812a96536eSKyongHo Cho	  Support for the IOMMU (System MMU) of Samsung Exynos application
1825455d700SSachin Kamat	  processor family. This enables H/W multimedia accelerators to see
1835455d700SSachin Kamat	  non-linear physical memory chunks as linear memory in their
1845455d700SSachin Kamat	  address space.
1852a96536eSKyongHo Cho
1862a96536eSKyongHo Cho	  If unsure, say N here.
1872a96536eSKyongHo Cho
1882a96536eSKyongHo Choconfig EXYNOS_IOMMU_DEBUG
1892a96536eSKyongHo Cho	bool "Debugging log for Exynos IOMMU"
1902a96536eSKyongHo Cho	depends on EXYNOS_IOMMU
1912a96536eSKyongHo Cho	help
1922a96536eSKyongHo Cho	  Select this to see the detailed log message that shows what
1935455d700SSachin Kamat	  happens in the IOMMU driver.
1942a96536eSKyongHo Cho
1955455d700SSachin Kamat	  Say N unless you need kernel log message for IOMMU debugging.
1962a96536eSKyongHo Cho
197c2c460f7SHideki EIRAKUconfig SHMOBILE_IPMMU
198c2c460f7SHideki EIRAKU	bool
199c2c460f7SHideki EIRAKU
200c2c460f7SHideki EIRAKUconfig SHMOBILE_IPMMU_TLB
201c2c460f7SHideki EIRAKU	bool
202c2c460f7SHideki EIRAKU
203c2c460f7SHideki EIRAKUconfig SHMOBILE_IOMMU
204c2c460f7SHideki EIRAKU	bool "IOMMU for Renesas IPMMU/IPMMUI"
205c2c460f7SHideki EIRAKU	default n
206f63c4824SLinus Torvalds	depends on ARM
207b8354439SPaul Bolle	depends on ARCH_SHMOBILE || COMPILE_TEST
208c2c460f7SHideki EIRAKU	select IOMMU_API
209c2c460f7SHideki EIRAKU	select ARM_DMA_USE_IOMMU
210c2c460f7SHideki EIRAKU	select SHMOBILE_IPMMU
211c2c460f7SHideki EIRAKU	select SHMOBILE_IPMMU_TLB
212c2c460f7SHideki EIRAKU	help
213c2c460f7SHideki EIRAKU	  Support for Renesas IPMMU/IPMMUI. This option enables
214c2c460f7SHideki EIRAKU	  remapping of DMA memory accesses from all of the IP blocks
215c2c460f7SHideki EIRAKU	  on the ICB.
216c2c460f7SHideki EIRAKU
217c2c460f7SHideki EIRAKU	  Warning: Drivers (including userspace drivers of UIO
218c2c460f7SHideki EIRAKU	  devices) of the IP blocks on the ICB *must* use addresses
219c2c460f7SHideki EIRAKU	  allocated from the IPMMU (iova) for DMA with this option
220c2c460f7SHideki EIRAKU	  enabled.
221c2c460f7SHideki EIRAKU
222c2c460f7SHideki EIRAKU	  If unsure, say N.
223c2c460f7SHideki EIRAKU
224c2c460f7SHideki EIRAKUchoice
225c2c460f7SHideki EIRAKU	prompt "IPMMU/IPMMUI address space size"
226c2c460f7SHideki EIRAKU	default SHMOBILE_IOMMU_ADDRSIZE_2048MB
227c2c460f7SHideki EIRAKU	depends on SHMOBILE_IOMMU
228c2c460f7SHideki EIRAKU	help
229c2c460f7SHideki EIRAKU	  This option sets IPMMU/IPMMUI address space size by
230c2c460f7SHideki EIRAKU	  adjusting the 1st level page table size. The page table size
231c2c460f7SHideki EIRAKU	  is calculated as follows:
232c2c460f7SHideki EIRAKU
233c2c460f7SHideki EIRAKU	      page table size = number of page table entries * 4 bytes
234c2c460f7SHideki EIRAKU	      number of page table entries = address space size / 1 MiB
235c2c460f7SHideki EIRAKU
236c2c460f7SHideki EIRAKU	  For example, when the address space size is 2048 MiB, the
237c2c460f7SHideki EIRAKU	  1st level page table size is 8192 bytes.
238c2c460f7SHideki EIRAKU
239c2c460f7SHideki EIRAKU	config SHMOBILE_IOMMU_ADDRSIZE_2048MB
240c2c460f7SHideki EIRAKU		bool "2 GiB"
241c2c460f7SHideki EIRAKU
242c2c460f7SHideki EIRAKU	config SHMOBILE_IOMMU_ADDRSIZE_1024MB
243c2c460f7SHideki EIRAKU		bool "1 GiB"
244c2c460f7SHideki EIRAKU
245c2c460f7SHideki EIRAKU	config SHMOBILE_IOMMU_ADDRSIZE_512MB
246c2c460f7SHideki EIRAKU		bool "512 MiB"
247c2c460f7SHideki EIRAKU
248c2c460f7SHideki EIRAKU	config SHMOBILE_IOMMU_ADDRSIZE_256MB
249c2c460f7SHideki EIRAKU		bool "256 MiB"
250c2c460f7SHideki EIRAKU
251c2c460f7SHideki EIRAKU	config SHMOBILE_IOMMU_ADDRSIZE_128MB
252c2c460f7SHideki EIRAKU		bool "128 MiB"
253c2c460f7SHideki EIRAKU
254c2c460f7SHideki EIRAKU	config SHMOBILE_IOMMU_ADDRSIZE_64MB
255c2c460f7SHideki EIRAKU		bool "64 MiB"
256c2c460f7SHideki EIRAKU
257c2c460f7SHideki EIRAKU	config SHMOBILE_IOMMU_ADDRSIZE_32MB
258c2c460f7SHideki EIRAKU		bool "32 MiB"
259c2c460f7SHideki EIRAKU
260c2c460f7SHideki EIRAKUendchoice
261c2c460f7SHideki EIRAKU
262c2c460f7SHideki EIRAKUconfig SHMOBILE_IOMMU_L1SIZE
263c2c460f7SHideki EIRAKU	int
264c2c460f7SHideki EIRAKU	default 8192 if SHMOBILE_IOMMU_ADDRSIZE_2048MB
265c2c460f7SHideki EIRAKU	default 4096 if SHMOBILE_IOMMU_ADDRSIZE_1024MB
266c2c460f7SHideki EIRAKU	default 2048 if SHMOBILE_IOMMU_ADDRSIZE_512MB
267c2c460f7SHideki EIRAKU	default 1024 if SHMOBILE_IOMMU_ADDRSIZE_256MB
268c2c460f7SHideki EIRAKU	default 512 if SHMOBILE_IOMMU_ADDRSIZE_128MB
269c2c460f7SHideki EIRAKU	default 256 if SHMOBILE_IOMMU_ADDRSIZE_64MB
270c2c460f7SHideki EIRAKU	default 128 if SHMOBILE_IOMMU_ADDRSIZE_32MB
271c2c460f7SHideki EIRAKU
272d25a2a16SLaurent Pinchartconfig IPMMU_VMSA
273d25a2a16SLaurent Pinchart	bool "Renesas VMSA-compatible IPMMU"
274d25a2a16SLaurent Pinchart	depends on ARM_LPAE
275d25a2a16SLaurent Pinchart	depends on ARCH_SHMOBILE || COMPILE_TEST
276d25a2a16SLaurent Pinchart	select IOMMU_API
277d25a2a16SLaurent Pinchart	select ARM_DMA_USE_IOMMU
278d25a2a16SLaurent Pinchart	help
279d25a2a16SLaurent Pinchart	  Support for the Renesas VMSA-compatible IPMMU Renesas found in the
280d25a2a16SLaurent Pinchart	  R-Mobile APE6 and R-Car H2/M2 SoCs.
281d25a2a16SLaurent Pinchart
282d25a2a16SLaurent Pinchart	  If unsure, say N.
283d25a2a16SLaurent Pinchart
2844e13c1acSAlexey Kardashevskiyconfig SPAPR_TCE_IOMMU
2854e13c1acSAlexey Kardashevskiy	bool "sPAPR TCE IOMMU Support"
2865b25199eSAlexey Kardashevskiy	depends on PPC_POWERNV || PPC_PSERIES
2874e13c1acSAlexey Kardashevskiy	select IOMMU_API
2884e13c1acSAlexey Kardashevskiy	help
2894e13c1acSAlexey Kardashevskiy	  Enables bits of IOMMU API required by VFIO. The iommu_ops
2904e13c1acSAlexey Kardashevskiy	  is not implemented as it is not necessary for VFIO.
2914e13c1acSAlexey Kardashevskiy
29245ae7cffSWill Deaconconfig ARM_SMMU
29345ae7cffSWill Deacon	bool "ARM Ltd. System MMU (SMMU) Support"
29445ae7cffSWill Deacon	depends on ARM64 || (ARM_LPAE && OF)
29545ae7cffSWill Deacon	select IOMMU_API
29645ae7cffSWill Deacon	select ARM_DMA_USE_IOMMU if ARM
29745ae7cffSWill Deacon	help
29845ae7cffSWill Deacon	  Support for implementations of the ARM System MMU architecture
29945ae7cffSWill Deacon	  versions 1 and 2. The driver supports both v7l and v8l table
30045ae7cffSWill Deacon	  formats with 4k and 64k page sizes.
30145ae7cffSWill Deacon
30245ae7cffSWill Deacon	  Say Y here if your SoC includes an IOMMU device implementing
30345ae7cffSWill Deacon	  the ARM SMMU architecture.
30445ae7cffSWill Deacon
30568255b62SJoerg Roedelendif # IOMMU_SUPPORT
306