1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
5  * Copyright (c) 2022, Linaro Limited
6  *
7  */
8 
9 #include <linux/device.h>
10 #include <linux/interconnect.h>
11 #include <linux/interconnect-provider.h>
12 #include <linux/module.h>
13 #include <linux/of_platform.h>
14 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
15 
16 #include "bcm-voter.h"
17 #include "icc-common.h"
18 #include "icc-rpmh.h"
19 #include "sm8550.h"
20 
21 static struct qcom_icc_node qhm_qspi = {
22 	.name = "qhm_qspi",
23 	.id = SM8550_MASTER_QSPI_0,
24 	.channels = 1,
25 	.buswidth = 4,
26 	.num_links = 1,
27 	.links = { SM8550_SLAVE_A1NOC_SNOC },
28 };
29 
30 static struct qcom_icc_node qhm_qup1 = {
31 	.name = "qhm_qup1",
32 	.id = SM8550_MASTER_QUP_1,
33 	.channels = 1,
34 	.buswidth = 4,
35 	.num_links = 1,
36 	.links = { SM8550_SLAVE_A1NOC_SNOC },
37 };
38 
39 static struct qcom_icc_node xm_sdc4 = {
40 	.name = "xm_sdc4",
41 	.id = SM8550_MASTER_SDCC_4,
42 	.channels = 1,
43 	.buswidth = 8,
44 	.num_links = 1,
45 	.links = { SM8550_SLAVE_A1NOC_SNOC },
46 };
47 
48 static struct qcom_icc_node xm_ufs_mem = {
49 	.name = "xm_ufs_mem",
50 	.id = SM8550_MASTER_UFS_MEM,
51 	.channels = 1,
52 	.buswidth = 16,
53 	.num_links = 1,
54 	.links = { SM8550_SLAVE_A1NOC_SNOC },
55 };
56 
57 static struct qcom_icc_node xm_usb3_0 = {
58 	.name = "xm_usb3_0",
59 	.id = SM8550_MASTER_USB3_0,
60 	.channels = 1,
61 	.buswidth = 8,
62 	.num_links = 1,
63 	.links = { SM8550_SLAVE_A1NOC_SNOC },
64 };
65 
66 static struct qcom_icc_node qhm_qdss_bam = {
67 	.name = "qhm_qdss_bam",
68 	.id = SM8550_MASTER_QDSS_BAM,
69 	.channels = 1,
70 	.buswidth = 4,
71 	.num_links = 1,
72 	.links = { SM8550_SLAVE_A2NOC_SNOC },
73 };
74 
75 static struct qcom_icc_node qhm_qup2 = {
76 	.name = "qhm_qup2",
77 	.id = SM8550_MASTER_QUP_2,
78 	.channels = 1,
79 	.buswidth = 4,
80 	.num_links = 1,
81 	.links = { SM8550_SLAVE_A2NOC_SNOC },
82 };
83 
84 static struct qcom_icc_node qxm_crypto = {
85 	.name = "qxm_crypto",
86 	.id = SM8550_MASTER_CRYPTO,
87 	.channels = 1,
88 	.buswidth = 8,
89 	.num_links = 1,
90 	.links = { SM8550_SLAVE_A2NOC_SNOC },
91 };
92 
93 static struct qcom_icc_node qxm_ipa = {
94 	.name = "qxm_ipa",
95 	.id = SM8550_MASTER_IPA,
96 	.channels = 1,
97 	.buswidth = 8,
98 	.num_links = 1,
99 	.links = { SM8550_SLAVE_A2NOC_SNOC },
100 };
101 
102 static struct qcom_icc_node qxm_sp = {
103 	.name = "qxm_sp",
104 	.id = SM8550_MASTER_SP,
105 	.channels = 1,
106 	.buswidth = 8,
107 	.num_links = 1,
108 	.links = { SM8550_SLAVE_A2NOC_SNOC },
109 };
110 
111 static struct qcom_icc_node xm_qdss_etr_0 = {
112 	.name = "xm_qdss_etr_0",
113 	.id = SM8550_MASTER_QDSS_ETR,
114 	.channels = 1,
115 	.buswidth = 8,
116 	.num_links = 1,
117 	.links = { SM8550_SLAVE_A2NOC_SNOC },
118 };
119 
120 static struct qcom_icc_node xm_qdss_etr_1 = {
121 	.name = "xm_qdss_etr_1",
122 	.id = SM8550_MASTER_QDSS_ETR_1,
123 	.channels = 1,
124 	.buswidth = 8,
125 	.num_links = 1,
126 	.links = { SM8550_SLAVE_A2NOC_SNOC },
127 };
128 
129 static struct qcom_icc_node xm_sdc2 = {
130 	.name = "xm_sdc2",
131 	.id = SM8550_MASTER_SDCC_2,
132 	.channels = 1,
133 	.buswidth = 8,
134 	.num_links = 1,
135 	.links = { SM8550_SLAVE_A2NOC_SNOC },
136 };
137 
138 static struct qcom_icc_node qup0_core_master = {
139 	.name = "qup0_core_master",
140 	.id = SM8550_MASTER_QUP_CORE_0,
141 	.channels = 1,
142 	.buswidth = 4,
143 	.num_links = 1,
144 	.links = { SM8550_SLAVE_QUP_CORE_0 },
145 };
146 
147 static struct qcom_icc_node qup1_core_master = {
148 	.name = "qup1_core_master",
149 	.id = SM8550_MASTER_QUP_CORE_1,
150 	.channels = 1,
151 	.buswidth = 4,
152 	.num_links = 1,
153 	.links = { SM8550_SLAVE_QUP_CORE_1 },
154 };
155 
156 static struct qcom_icc_node qup2_core_master = {
157 	.name = "qup2_core_master",
158 	.id = SM8550_MASTER_QUP_CORE_2,
159 	.channels = 1,
160 	.buswidth = 4,
161 	.num_links = 1,
162 	.links = { SM8550_SLAVE_QUP_CORE_2 },
163 };
164 
165 static struct qcom_icc_node qsm_cfg = {
166 	.name = "qsm_cfg",
167 	.id = SM8550_MASTER_CNOC_CFG,
168 	.channels = 1,
169 	.buswidth = 4,
170 	.num_links = 44,
171 	.links = { SM8550_SLAVE_AHB2PHY_SOUTH, SM8550_SLAVE_AHB2PHY_NORTH,
172 		   SM8550_SLAVE_APPSS, SM8550_SLAVE_CAMERA_CFG,
173 		   SM8550_SLAVE_CLK_CTL, SM8550_SLAVE_RBCPR_CX_CFG,
174 		   SM8550_SLAVE_RBCPR_MMCX_CFG, SM8550_SLAVE_RBCPR_MXA_CFG,
175 		   SM8550_SLAVE_RBCPR_MXC_CFG, SM8550_SLAVE_CPR_NSPCX,
176 		   SM8550_SLAVE_CRYPTO_0_CFG, SM8550_SLAVE_CX_RDPM,
177 		   SM8550_SLAVE_DISPLAY_CFG, SM8550_SLAVE_GFX3D_CFG,
178 		   SM8550_SLAVE_I2C, SM8550_SLAVE_IMEM_CFG,
179 		   SM8550_SLAVE_IPA_CFG, SM8550_SLAVE_IPC_ROUTER_CFG,
180 		   SM8550_SLAVE_CNOC_MSS, SM8550_SLAVE_MX_RDPM,
181 		   SM8550_SLAVE_PCIE_0_CFG, SM8550_SLAVE_PCIE_1_CFG,
182 		   SM8550_SLAVE_PDM, SM8550_SLAVE_PIMEM_CFG,
183 		   SM8550_SLAVE_PRNG, SM8550_SLAVE_QDSS_CFG,
184 		   SM8550_SLAVE_QSPI_0, SM8550_SLAVE_QUP_1,
185 		   SM8550_SLAVE_QUP_2, SM8550_SLAVE_SDCC_2,
186 		   SM8550_SLAVE_SDCC_4, SM8550_SLAVE_SPSS_CFG,
187 		   SM8550_SLAVE_TCSR, SM8550_SLAVE_TLMM,
188 		   SM8550_SLAVE_UFS_MEM_CFG, SM8550_SLAVE_USB3_0,
189 		   SM8550_SLAVE_VENUS_CFG, SM8550_SLAVE_VSENSE_CTRL_CFG,
190 		   SM8550_SLAVE_LPASS_QTB_CFG, SM8550_SLAVE_CNOC_MNOC_CFG,
191 		   SM8550_SLAVE_NSP_QTB_CFG, SM8550_SLAVE_PCIE_ANOC_CFG,
192 		   SM8550_SLAVE_QDSS_STM, SM8550_SLAVE_TCU },
193 };
194 
195 static struct qcom_icc_node qnm_gemnoc_cnoc = {
196 	.name = "qnm_gemnoc_cnoc",
197 	.id = SM8550_MASTER_GEM_NOC_CNOC,
198 	.channels = 1,
199 	.buswidth = 16,
200 	.num_links = 6,
201 	.links = { SM8550_SLAVE_AOSS, SM8550_SLAVE_TME_CFG,
202 		   SM8550_SLAVE_CNOC_CFG, SM8550_SLAVE_DDRSS_CFG,
203 		   SM8550_SLAVE_BOOT_IMEM, SM8550_SLAVE_IMEM },
204 };
205 
206 static struct qcom_icc_node qnm_gemnoc_pcie = {
207 	.name = "qnm_gemnoc_pcie",
208 	.id = SM8550_MASTER_GEM_NOC_PCIE_SNOC,
209 	.channels = 1,
210 	.buswidth = 8,
211 	.num_links = 2,
212 	.links = { SM8550_SLAVE_PCIE_0, SM8550_SLAVE_PCIE_1 },
213 };
214 
215 static struct qcom_icc_node alm_gpu_tcu = {
216 	.name = "alm_gpu_tcu",
217 	.id = SM8550_MASTER_GPU_TCU,
218 	.channels = 1,
219 	.buswidth = 8,
220 	.num_links = 2,
221 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
222 };
223 
224 static struct qcom_icc_node alm_sys_tcu = {
225 	.name = "alm_sys_tcu",
226 	.id = SM8550_MASTER_SYS_TCU,
227 	.channels = 1,
228 	.buswidth = 8,
229 	.num_links = 2,
230 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
231 };
232 
233 static struct qcom_icc_node chm_apps = {
234 	.name = "chm_apps",
235 	.id = SM8550_MASTER_APPSS_PROC,
236 	.channels = 3,
237 	.buswidth = 32,
238 	.num_links = 3,
239 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
240 		   SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
241 };
242 
243 static struct qcom_icc_node qnm_gpu = {
244 	.name = "qnm_gpu",
245 	.id = SM8550_MASTER_GFX3D,
246 	.channels = 2,
247 	.buswidth = 32,
248 	.num_links = 2,
249 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
250 };
251 
252 static struct qcom_icc_node qnm_lpass_gemnoc = {
253 	.name = "qnm_lpass_gemnoc",
254 	.id = SM8550_MASTER_LPASS_GEM_NOC,
255 	.channels = 1,
256 	.buswidth = 16,
257 	.num_links = 3,
258 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
259 		   SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
260 };
261 
262 static struct qcom_icc_node qnm_mdsp = {
263 	.name = "qnm_mdsp",
264 	.id = SM8550_MASTER_MSS_PROC,
265 	.channels = 1,
266 	.buswidth = 16,
267 	.num_links = 3,
268 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
269 		   SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
270 };
271 
272 static struct qcom_icc_node qnm_mnoc_hf = {
273 	.name = "qnm_mnoc_hf",
274 	.id = SM8550_MASTER_MNOC_HF_MEM_NOC,
275 	.channels = 2,
276 	.buswidth = 32,
277 	.num_links = 2,
278 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
279 };
280 
281 static struct qcom_icc_node qnm_mnoc_sf = {
282 	.name = "qnm_mnoc_sf",
283 	.id = SM8550_MASTER_MNOC_SF_MEM_NOC,
284 	.channels = 2,
285 	.buswidth = 32,
286 	.num_links = 2,
287 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
288 };
289 
290 static struct qcom_icc_node qnm_nsp_gemnoc = {
291 	.name = "qnm_nsp_gemnoc",
292 	.id = SM8550_MASTER_COMPUTE_NOC,
293 	.channels = 2,
294 	.buswidth = 32,
295 	.num_links = 2,
296 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
297 };
298 
299 static struct qcom_icc_node qnm_pcie = {
300 	.name = "qnm_pcie",
301 	.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC,
302 	.channels = 1,
303 	.buswidth = 16,
304 	.num_links = 2,
305 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
306 };
307 
308 static struct qcom_icc_node qnm_snoc_gc = {
309 	.name = "qnm_snoc_gc",
310 	.id = SM8550_MASTER_SNOC_GC_MEM_NOC,
311 	.channels = 1,
312 	.buswidth = 8,
313 	.num_links = 1,
314 	.links = { SM8550_SLAVE_LLCC },
315 };
316 
317 static struct qcom_icc_node qnm_snoc_sf = {
318 	.name = "qnm_snoc_sf",
319 	.id = SM8550_MASTER_SNOC_SF_MEM_NOC,
320 	.channels = 1,
321 	.buswidth = 16,
322 	.num_links = 3,
323 	.links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
324 		   SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
325 };
326 
327 static struct qcom_icc_node qnm_lpiaon_noc = {
328 	.name = "qnm_lpiaon_noc",
329 	.id = SM8550_MASTER_LPIAON_NOC,
330 	.channels = 1,
331 	.buswidth = 16,
332 	.num_links = 1,
333 	.links = { SM8550_SLAVE_LPASS_GEM_NOC },
334 };
335 
336 static struct qcom_icc_node qnm_lpass_lpinoc = {
337 	.name = "qnm_lpass_lpinoc",
338 	.id = SM8550_MASTER_LPASS_LPINOC,
339 	.channels = 1,
340 	.buswidth = 16,
341 	.num_links = 1,
342 	.links = { SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
343 };
344 
345 static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
346 	.name = "qxm_lpinoc_dsp_axim",
347 	.id = SM8550_MASTER_LPASS_PROC,
348 	.channels = 1,
349 	.buswidth = 16,
350 	.num_links = 1,
351 	.links = { SM8550_SLAVE_LPICX_NOC_LPIAON_NOC },
352 };
353 
354 static struct qcom_icc_node llcc_mc = {
355 	.name = "llcc_mc",
356 	.id = SM8550_MASTER_LLCC,
357 	.channels = 4,
358 	.buswidth = 4,
359 	.num_links = 1,
360 	.links = { SM8550_SLAVE_EBI1 },
361 };
362 
363 static struct qcom_icc_node qnm_camnoc_hf = {
364 	.name = "qnm_camnoc_hf",
365 	.id = SM8550_MASTER_CAMNOC_HF,
366 	.channels = 2,
367 	.buswidth = 32,
368 	.num_links = 1,
369 	.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
370 };
371 
372 static struct qcom_icc_node qnm_camnoc_icp = {
373 	.name = "qnm_camnoc_icp",
374 	.id = SM8550_MASTER_CAMNOC_ICP,
375 	.channels = 1,
376 	.buswidth = 8,
377 	.num_links = 1,
378 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
379 };
380 
381 static struct qcom_icc_node qnm_camnoc_sf = {
382 	.name = "qnm_camnoc_sf",
383 	.id = SM8550_MASTER_CAMNOC_SF,
384 	.channels = 2,
385 	.buswidth = 32,
386 	.num_links = 1,
387 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
388 };
389 
390 static struct qcom_icc_node qnm_mdp = {
391 	.name = "qnm_mdp",
392 	.id = SM8550_MASTER_MDP,
393 	.channels = 2,
394 	.buswidth = 32,
395 	.num_links = 1,
396 	.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
397 };
398 
399 static struct qcom_icc_node qnm_vapss_hcp = {
400 	.name = "qnm_vapss_hcp",
401 	.id = SM8550_MASTER_CDSP_HCP,
402 	.channels = 1,
403 	.buswidth = 32,
404 	.num_links = 1,
405 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
406 };
407 
408 static struct qcom_icc_node qnm_video = {
409 	.name = "qnm_video",
410 	.id = SM8550_MASTER_VIDEO,
411 	.channels = 2,
412 	.buswidth = 32,
413 	.num_links = 1,
414 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
415 };
416 
417 static struct qcom_icc_node qnm_video_cv_cpu = {
418 	.name = "qnm_video_cv_cpu",
419 	.id = SM8550_MASTER_VIDEO_CV_PROC,
420 	.channels = 1,
421 	.buswidth = 8,
422 	.num_links = 1,
423 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
424 };
425 
426 static struct qcom_icc_node qnm_video_cvp = {
427 	.name = "qnm_video_cvp",
428 	.id = SM8550_MASTER_VIDEO_PROC,
429 	.channels = 1,
430 	.buswidth = 32,
431 	.num_links = 1,
432 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
433 };
434 
435 static struct qcom_icc_node qnm_video_v_cpu = {
436 	.name = "qnm_video_v_cpu",
437 	.id = SM8550_MASTER_VIDEO_V_PROC,
438 	.channels = 1,
439 	.buswidth = 8,
440 	.num_links = 1,
441 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
442 };
443 
444 static struct qcom_icc_node qsm_mnoc_cfg = {
445 	.name = "qsm_mnoc_cfg",
446 	.id = SM8550_MASTER_CNOC_MNOC_CFG,
447 	.channels = 1,
448 	.buswidth = 4,
449 	.num_links = 1,
450 	.links = { SM8550_SLAVE_SERVICE_MNOC },
451 };
452 
453 static struct qcom_icc_node qxm_nsp = {
454 	.name = "qxm_nsp",
455 	.id = SM8550_MASTER_CDSP_PROC,
456 	.channels = 2,
457 	.buswidth = 32,
458 	.num_links = 1,
459 	.links = { SM8550_SLAVE_CDSP_MEM_NOC },
460 };
461 
462 static struct qcom_icc_node qsm_pcie_anoc_cfg = {
463 	.name = "qsm_pcie_anoc_cfg",
464 	.id = SM8550_MASTER_PCIE_ANOC_CFG,
465 	.channels = 1,
466 	.buswidth = 4,
467 	.num_links = 1,
468 	.links = { SM8550_SLAVE_SERVICE_PCIE_ANOC },
469 };
470 
471 static struct qcom_icc_node xm_pcie3_0 = {
472 	.name = "xm_pcie3_0",
473 	.id = SM8550_MASTER_PCIE_0,
474 	.channels = 1,
475 	.buswidth = 8,
476 	.num_links = 1,
477 	.links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
478 };
479 
480 static struct qcom_icc_node xm_pcie3_1 = {
481 	.name = "xm_pcie3_1",
482 	.id = SM8550_MASTER_PCIE_1,
483 	.channels = 1,
484 	.buswidth = 16,
485 	.num_links = 1,
486 	.links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
487 };
488 
489 static struct qcom_icc_node qhm_gic = {
490 	.name = "qhm_gic",
491 	.id = SM8550_MASTER_GIC_AHB,
492 	.channels = 1,
493 	.buswidth = 4,
494 	.num_links = 1,
495 	.links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
496 };
497 
498 static struct qcom_icc_node qnm_aggre1_noc = {
499 	.name = "qnm_aggre1_noc",
500 	.id = SM8550_MASTER_A1NOC_SNOC,
501 	.channels = 1,
502 	.buswidth = 16,
503 	.num_links = 1,
504 	.links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
505 };
506 
507 static struct qcom_icc_node qnm_aggre2_noc = {
508 	.name = "qnm_aggre2_noc",
509 	.id = SM8550_MASTER_A2NOC_SNOC,
510 	.channels = 1,
511 	.buswidth = 16,
512 	.num_links = 1,
513 	.links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
514 };
515 
516 static struct qcom_icc_node xm_gic = {
517 	.name = "xm_gic",
518 	.id = SM8550_MASTER_GIC,
519 	.channels = 1,
520 	.buswidth = 8,
521 	.num_links = 1,
522 	.links = { SM8550_SLAVE_SNOC_GEM_NOC_GC },
523 };
524 
525 static struct qcom_icc_node qnm_mnoc_hf_disp = {
526 	.name = "qnm_mnoc_hf_disp",
527 	.id = SM8550_MASTER_MNOC_HF_MEM_NOC_DISP,
528 	.channels = 2,
529 	.buswidth = 32,
530 	.num_links = 1,
531 	.links = { SM8550_SLAVE_LLCC_DISP },
532 };
533 
534 static struct qcom_icc_node qnm_pcie_disp = {
535 	.name = "qnm_pcie_disp",
536 	.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP,
537 	.channels = 1,
538 	.buswidth = 16,
539 	.num_links = 1,
540 	.links = { SM8550_SLAVE_LLCC_DISP },
541 };
542 
543 static struct qcom_icc_node llcc_mc_disp = {
544 	.name = "llcc_mc_disp",
545 	.id = SM8550_MASTER_LLCC_DISP,
546 	.channels = 4,
547 	.buswidth = 4,
548 	.num_links = 1,
549 	.links = { SM8550_SLAVE_EBI1_DISP },
550 };
551 
552 static struct qcom_icc_node qnm_mdp_disp = {
553 	.name = "qnm_mdp_disp",
554 	.id = SM8550_MASTER_MDP_DISP,
555 	.channels = 2,
556 	.buswidth = 32,
557 	.num_links = 1,
558 	.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP },
559 };
560 
561 static struct qcom_icc_node qnm_mnoc_hf_cam_ife_0 = {
562 	.name = "qnm_mnoc_hf_cam_ife_0",
563 	.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0,
564 	.channels = 2,
565 	.buswidth = 32,
566 	.num_links = 1,
567 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
568 };
569 
570 static struct qcom_icc_node qnm_mnoc_sf_cam_ife_0 = {
571 	.name = "qnm_mnoc_sf_cam_ife_0",
572 	.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0,
573 	.channels = 2,
574 	.buswidth = 32,
575 	.num_links = 1,
576 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
577 };
578 
579 static struct qcom_icc_node qnm_pcie_cam_ife_0 = {
580 	.name = "qnm_pcie_cam_ife_0",
581 	.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0,
582 	.channels = 1,
583 	.buswidth = 16,
584 	.num_links = 1,
585 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
586 };
587 
588 static struct qcom_icc_node llcc_mc_cam_ife_0 = {
589 	.name = "llcc_mc_cam_ife_0",
590 	.id = SM8550_MASTER_LLCC_CAM_IFE_0,
591 	.channels = 4,
592 	.buswidth = 4,
593 	.num_links = 1,
594 	.links = { SM8550_SLAVE_EBI1_CAM_IFE_0 },
595 };
596 
597 static struct qcom_icc_node qnm_camnoc_hf_cam_ife_0 = {
598 	.name = "qnm_camnoc_hf_cam_ife_0",
599 	.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_0,
600 	.channels = 2,
601 	.buswidth = 32,
602 	.num_links = 1,
603 	.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 },
604 };
605 
606 static struct qcom_icc_node qnm_camnoc_icp_cam_ife_0 = {
607 	.name = "qnm_camnoc_icp_cam_ife_0",
608 	.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0,
609 	.channels = 1,
610 	.buswidth = 8,
611 	.num_links = 1,
612 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
613 };
614 
615 static struct qcom_icc_node qnm_camnoc_sf_cam_ife_0 = {
616 	.name = "qnm_camnoc_sf_cam_ife_0",
617 	.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_0,
618 	.channels = 2,
619 	.buswidth = 32,
620 	.num_links = 1,
621 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
622 };
623 
624 static struct qcom_icc_node qnm_mnoc_hf_cam_ife_1 = {
625 	.name = "qnm_mnoc_hf_cam_ife_1",
626 	.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1,
627 	.channels = 2,
628 	.buswidth = 32,
629 	.num_links = 1,
630 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
631 };
632 
633 static struct qcom_icc_node qnm_mnoc_sf_cam_ife_1 = {
634 	.name = "qnm_mnoc_sf_cam_ife_1",
635 	.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1,
636 	.channels = 2,
637 	.buswidth = 32,
638 	.num_links = 1,
639 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
640 };
641 
642 static struct qcom_icc_node qnm_pcie_cam_ife_1 = {
643 	.name = "qnm_pcie_cam_ife_1",
644 	.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1,
645 	.channels = 1,
646 	.buswidth = 16,
647 	.num_links = 1,
648 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
649 };
650 
651 static struct qcom_icc_node llcc_mc_cam_ife_1 = {
652 	.name = "llcc_mc_cam_ife_1",
653 	.id = SM8550_MASTER_LLCC_CAM_IFE_1,
654 	.channels = 4,
655 	.buswidth = 4,
656 	.num_links = 1,
657 	.links = { SM8550_SLAVE_EBI1_CAM_IFE_1 },
658 };
659 
660 static struct qcom_icc_node qnm_camnoc_hf_cam_ife_1 = {
661 	.name = "qnm_camnoc_hf_cam_ife_1",
662 	.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_1,
663 	.channels = 2,
664 	.buswidth = 32,
665 	.num_links = 1,
666 	.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 },
667 };
668 
669 static struct qcom_icc_node qnm_camnoc_icp_cam_ife_1 = {
670 	.name = "qnm_camnoc_icp_cam_ife_1",
671 	.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1,
672 	.channels = 1,
673 	.buswidth = 8,
674 	.num_links = 1,
675 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
676 };
677 
678 static struct qcom_icc_node qnm_camnoc_sf_cam_ife_1 = {
679 	.name = "qnm_camnoc_sf_cam_ife_1",
680 	.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_1,
681 	.channels = 2,
682 	.buswidth = 32,
683 	.num_links = 1,
684 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
685 };
686 
687 static struct qcom_icc_node qnm_mnoc_hf_cam_ife_2 = {
688 	.name = "qnm_mnoc_hf_cam_ife_2",
689 	.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2,
690 	.channels = 2,
691 	.buswidth = 32,
692 	.num_links = 1,
693 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
694 };
695 
696 static struct qcom_icc_node qnm_mnoc_sf_cam_ife_2 = {
697 	.name = "qnm_mnoc_sf_cam_ife_2",
698 	.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2,
699 	.channels = 2,
700 	.buswidth = 32,
701 	.num_links = 1,
702 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
703 };
704 
705 static struct qcom_icc_node qnm_pcie_cam_ife_2 = {
706 	.name = "qnm_pcie_cam_ife_2",
707 	.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2,
708 	.channels = 1,
709 	.buswidth = 16,
710 	.num_links = 1,
711 	.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
712 };
713 
714 static struct qcom_icc_node llcc_mc_cam_ife_2 = {
715 	.name = "llcc_mc_cam_ife_2",
716 	.id = SM8550_MASTER_LLCC_CAM_IFE_2,
717 	.channels = 4,
718 	.buswidth = 4,
719 	.num_links = 1,
720 	.links = { SM8550_SLAVE_EBI1_CAM_IFE_2 },
721 };
722 
723 static struct qcom_icc_node qnm_camnoc_hf_cam_ife_2 = {
724 	.name = "qnm_camnoc_hf_cam_ife_2",
725 	.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_2,
726 	.channels = 2,
727 	.buswidth = 32,
728 	.num_links = 1,
729 	.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 },
730 };
731 
732 static struct qcom_icc_node qnm_camnoc_icp_cam_ife_2 = {
733 	.name = "qnm_camnoc_icp_cam_ife_2",
734 	.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2,
735 	.channels = 1,
736 	.buswidth = 8,
737 	.num_links = 1,
738 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
739 };
740 
741 static struct qcom_icc_node qnm_camnoc_sf_cam_ife_2 = {
742 	.name = "qnm_camnoc_sf_cam_ife_2",
743 	.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_2,
744 	.channels = 2,
745 	.buswidth = 32,
746 	.num_links = 1,
747 	.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
748 };
749 
750 static struct qcom_icc_node qns_a1noc_snoc = {
751 	.name = "qns_a1noc_snoc",
752 	.id = SM8550_SLAVE_A1NOC_SNOC,
753 	.channels = 1,
754 	.buswidth = 16,
755 	.num_links = 1,
756 	.links = { SM8550_MASTER_A1NOC_SNOC },
757 };
758 
759 static struct qcom_icc_node qns_a2noc_snoc = {
760 	.name = "qns_a2noc_snoc",
761 	.id = SM8550_SLAVE_A2NOC_SNOC,
762 	.channels = 1,
763 	.buswidth = 16,
764 	.num_links = 1,
765 	.links = { SM8550_MASTER_A2NOC_SNOC },
766 };
767 
768 static struct qcom_icc_node qup0_core_slave = {
769 	.name = "qup0_core_slave",
770 	.id = SM8550_SLAVE_QUP_CORE_0,
771 	.channels = 1,
772 	.buswidth = 4,
773 	.num_links = 0,
774 };
775 
776 static struct qcom_icc_node qup1_core_slave = {
777 	.name = "qup1_core_slave",
778 	.id = SM8550_SLAVE_QUP_CORE_1,
779 	.channels = 1,
780 	.buswidth = 4,
781 	.num_links = 0,
782 };
783 
784 static struct qcom_icc_node qup2_core_slave = {
785 	.name = "qup2_core_slave",
786 	.id = SM8550_SLAVE_QUP_CORE_2,
787 	.channels = 1,
788 	.buswidth = 4,
789 	.num_links = 0,
790 };
791 
792 static struct qcom_icc_node qhs_ahb2phy0 = {
793 	.name = "qhs_ahb2phy0",
794 	.id = SM8550_SLAVE_AHB2PHY_SOUTH,
795 	.channels = 1,
796 	.buswidth = 4,
797 	.num_links = 0,
798 };
799 
800 static struct qcom_icc_node qhs_ahb2phy1 = {
801 	.name = "qhs_ahb2phy1",
802 	.id = SM8550_SLAVE_AHB2PHY_NORTH,
803 	.channels = 1,
804 	.buswidth = 4,
805 	.num_links = 0,
806 };
807 
808 static struct qcom_icc_node qhs_apss = {
809 	.name = "qhs_apss",
810 	.id = SM8550_SLAVE_APPSS,
811 	.channels = 1,
812 	.buswidth = 8,
813 	.num_links = 0,
814 };
815 
816 static struct qcom_icc_node qhs_camera_cfg = {
817 	.name = "qhs_camera_cfg",
818 	.id = SM8550_SLAVE_CAMERA_CFG,
819 	.channels = 1,
820 	.buswidth = 4,
821 	.num_links = 0,
822 };
823 
824 static struct qcom_icc_node qhs_clk_ctl = {
825 	.name = "qhs_clk_ctl",
826 	.id = SM8550_SLAVE_CLK_CTL,
827 	.channels = 1,
828 	.buswidth = 4,
829 	.num_links = 0,
830 };
831 
832 static struct qcom_icc_node qhs_cpr_cx = {
833 	.name = "qhs_cpr_cx",
834 	.id = SM8550_SLAVE_RBCPR_CX_CFG,
835 	.channels = 1,
836 	.buswidth = 4,
837 	.num_links = 0,
838 };
839 
840 static struct qcom_icc_node qhs_cpr_mmcx = {
841 	.name = "qhs_cpr_mmcx",
842 	.id = SM8550_SLAVE_RBCPR_MMCX_CFG,
843 	.channels = 1,
844 	.buswidth = 4,
845 	.num_links = 0,
846 };
847 
848 static struct qcom_icc_node qhs_cpr_mxa = {
849 	.name = "qhs_cpr_mxa",
850 	.id = SM8550_SLAVE_RBCPR_MXA_CFG,
851 	.channels = 1,
852 	.buswidth = 4,
853 	.num_links = 0,
854 };
855 
856 static struct qcom_icc_node qhs_cpr_mxc = {
857 	.name = "qhs_cpr_mxc",
858 	.id = SM8550_SLAVE_RBCPR_MXC_CFG,
859 	.channels = 1,
860 	.buswidth = 4,
861 	.num_links = 0,
862 };
863 
864 static struct qcom_icc_node qhs_cpr_nspcx = {
865 	.name = "qhs_cpr_nspcx",
866 	.id = SM8550_SLAVE_CPR_NSPCX,
867 	.channels = 1,
868 	.buswidth = 4,
869 	.num_links = 0,
870 };
871 
872 static struct qcom_icc_node qhs_crypto0_cfg = {
873 	.name = "qhs_crypto0_cfg",
874 	.id = SM8550_SLAVE_CRYPTO_0_CFG,
875 	.channels = 1,
876 	.buswidth = 4,
877 	.num_links = 0,
878 };
879 
880 static struct qcom_icc_node qhs_cx_rdpm = {
881 	.name = "qhs_cx_rdpm",
882 	.id = SM8550_SLAVE_CX_RDPM,
883 	.channels = 1,
884 	.buswidth = 4,
885 	.num_links = 0,
886 };
887 
888 static struct qcom_icc_node qhs_display_cfg = {
889 	.name = "qhs_display_cfg",
890 	.id = SM8550_SLAVE_DISPLAY_CFG,
891 	.channels = 1,
892 	.buswidth = 4,
893 	.num_links = 0,
894 };
895 
896 static struct qcom_icc_node qhs_gpuss_cfg = {
897 	.name = "qhs_gpuss_cfg",
898 	.id = SM8550_SLAVE_GFX3D_CFG,
899 	.channels = 1,
900 	.buswidth = 8,
901 	.num_links = 0,
902 };
903 
904 static struct qcom_icc_node qhs_i2c = {
905 	.name = "qhs_i2c",
906 	.id = SM8550_SLAVE_I2C,
907 	.channels = 1,
908 	.buswidth = 4,
909 	.num_links = 0,
910 };
911 
912 static struct qcom_icc_node qhs_imem_cfg = {
913 	.name = "qhs_imem_cfg",
914 	.id = SM8550_SLAVE_IMEM_CFG,
915 	.channels = 1,
916 	.buswidth = 4,
917 	.num_links = 0,
918 };
919 
920 static struct qcom_icc_node qhs_ipa = {
921 	.name = "qhs_ipa",
922 	.id = SM8550_SLAVE_IPA_CFG,
923 	.channels = 1,
924 	.buswidth = 4,
925 	.num_links = 0,
926 };
927 
928 static struct qcom_icc_node qhs_ipc_router = {
929 	.name = "qhs_ipc_router",
930 	.id = SM8550_SLAVE_IPC_ROUTER_CFG,
931 	.channels = 1,
932 	.buswidth = 4,
933 	.num_links = 0,
934 };
935 
936 static struct qcom_icc_node qhs_mss_cfg = {
937 	.name = "qhs_mss_cfg",
938 	.id = SM8550_SLAVE_CNOC_MSS,
939 	.channels = 1,
940 	.buswidth = 4,
941 	.num_links = 0,
942 };
943 
944 static struct qcom_icc_node qhs_mx_rdpm = {
945 	.name = "qhs_mx_rdpm",
946 	.id = SM8550_SLAVE_MX_RDPM,
947 	.channels = 1,
948 	.buswidth = 4,
949 	.num_links = 0,
950 };
951 
952 static struct qcom_icc_node qhs_pcie0_cfg = {
953 	.name = "qhs_pcie0_cfg",
954 	.id = SM8550_SLAVE_PCIE_0_CFG,
955 	.channels = 1,
956 	.buswidth = 4,
957 	.num_links = 0,
958 };
959 
960 static struct qcom_icc_node qhs_pcie1_cfg = {
961 	.name = "qhs_pcie1_cfg",
962 	.id = SM8550_SLAVE_PCIE_1_CFG,
963 	.channels = 1,
964 	.buswidth = 4,
965 	.num_links = 0,
966 };
967 
968 static struct qcom_icc_node qhs_pdm = {
969 	.name = "qhs_pdm",
970 	.id = SM8550_SLAVE_PDM,
971 	.channels = 1,
972 	.buswidth = 4,
973 	.num_links = 0,
974 };
975 
976 static struct qcom_icc_node qhs_pimem_cfg = {
977 	.name = "qhs_pimem_cfg",
978 	.id = SM8550_SLAVE_PIMEM_CFG,
979 	.channels = 1,
980 	.buswidth = 4,
981 	.num_links = 0,
982 };
983 
984 static struct qcom_icc_node qhs_prng = {
985 	.name = "qhs_prng",
986 	.id = SM8550_SLAVE_PRNG,
987 	.channels = 1,
988 	.buswidth = 4,
989 	.num_links = 0,
990 };
991 
992 static struct qcom_icc_node qhs_qdss_cfg = {
993 	.name = "qhs_qdss_cfg",
994 	.id = SM8550_SLAVE_QDSS_CFG,
995 	.channels = 1,
996 	.buswidth = 4,
997 	.num_links = 0,
998 };
999 
1000 static struct qcom_icc_node qhs_qspi = {
1001 	.name = "qhs_qspi",
1002 	.id = SM8550_SLAVE_QSPI_0,
1003 	.channels = 1,
1004 	.buswidth = 4,
1005 	.num_links = 0,
1006 };
1007 
1008 static struct qcom_icc_node qhs_qup1 = {
1009 	.name = "qhs_qup1",
1010 	.id = SM8550_SLAVE_QUP_1,
1011 	.channels = 1,
1012 	.buswidth = 4,
1013 	.num_links = 0,
1014 };
1015 
1016 static struct qcom_icc_node qhs_qup2 = {
1017 	.name = "qhs_qup2",
1018 	.id = SM8550_SLAVE_QUP_2,
1019 	.channels = 1,
1020 	.buswidth = 4,
1021 	.num_links = 0,
1022 };
1023 
1024 static struct qcom_icc_node qhs_sdc2 = {
1025 	.name = "qhs_sdc2",
1026 	.id = SM8550_SLAVE_SDCC_2,
1027 	.channels = 1,
1028 	.buswidth = 4,
1029 	.num_links = 0,
1030 };
1031 
1032 static struct qcom_icc_node qhs_sdc4 = {
1033 	.name = "qhs_sdc4",
1034 	.id = SM8550_SLAVE_SDCC_4,
1035 	.channels = 1,
1036 	.buswidth = 4,
1037 	.num_links = 0,
1038 };
1039 
1040 static struct qcom_icc_node qhs_spss_cfg = {
1041 	.name = "qhs_spss_cfg",
1042 	.id = SM8550_SLAVE_SPSS_CFG,
1043 	.channels = 1,
1044 	.buswidth = 4,
1045 	.num_links = 0,
1046 };
1047 
1048 static struct qcom_icc_node qhs_tcsr = {
1049 	.name = "qhs_tcsr",
1050 	.id = SM8550_SLAVE_TCSR,
1051 	.channels = 1,
1052 	.buswidth = 4,
1053 	.num_links = 0,
1054 };
1055 
1056 static struct qcom_icc_node qhs_tlmm = {
1057 	.name = "qhs_tlmm",
1058 	.id = SM8550_SLAVE_TLMM,
1059 	.channels = 1,
1060 	.buswidth = 4,
1061 	.num_links = 0,
1062 };
1063 
1064 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1065 	.name = "qhs_ufs_mem_cfg",
1066 	.id = SM8550_SLAVE_UFS_MEM_CFG,
1067 	.channels = 1,
1068 	.buswidth = 4,
1069 	.num_links = 0,
1070 };
1071 
1072 static struct qcom_icc_node qhs_usb3_0 = {
1073 	.name = "qhs_usb3_0",
1074 	.id = SM8550_SLAVE_USB3_0,
1075 	.channels = 1,
1076 	.buswidth = 4,
1077 	.num_links = 0,
1078 };
1079 
1080 static struct qcom_icc_node qhs_venus_cfg = {
1081 	.name = "qhs_venus_cfg",
1082 	.id = SM8550_SLAVE_VENUS_CFG,
1083 	.channels = 1,
1084 	.buswidth = 4,
1085 	.num_links = 0,
1086 };
1087 
1088 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1089 	.name = "qhs_vsense_ctrl_cfg",
1090 	.id = SM8550_SLAVE_VSENSE_CTRL_CFG,
1091 	.channels = 1,
1092 	.buswidth = 4,
1093 	.num_links = 0,
1094 };
1095 
1096 static struct qcom_icc_node qss_lpass_qtb_cfg = {
1097 	.name = "qss_lpass_qtb_cfg",
1098 	.id = SM8550_SLAVE_LPASS_QTB_CFG,
1099 	.channels = 1,
1100 	.buswidth = 4,
1101 	.num_links = 0,
1102 };
1103 
1104 static struct qcom_icc_node qss_mnoc_cfg = {
1105 	.name = "qss_mnoc_cfg",
1106 	.id = SM8550_SLAVE_CNOC_MNOC_CFG,
1107 	.channels = 1,
1108 	.buswidth = 4,
1109 	.num_links = 1,
1110 	.links = { SM8550_MASTER_CNOC_MNOC_CFG },
1111 };
1112 
1113 static struct qcom_icc_node qss_nsp_qtb_cfg = {
1114 	.name = "qss_nsp_qtb_cfg",
1115 	.id = SM8550_SLAVE_NSP_QTB_CFG,
1116 	.channels = 1,
1117 	.buswidth = 4,
1118 	.num_links = 0,
1119 };
1120 
1121 static struct qcom_icc_node qss_pcie_anoc_cfg = {
1122 	.name = "qss_pcie_anoc_cfg",
1123 	.id = SM8550_SLAVE_PCIE_ANOC_CFG,
1124 	.channels = 1,
1125 	.buswidth = 4,
1126 	.num_links = 1,
1127 	.links = { SM8550_MASTER_PCIE_ANOC_CFG },
1128 };
1129 
1130 static struct qcom_icc_node xs_qdss_stm = {
1131 	.name = "xs_qdss_stm",
1132 	.id = SM8550_SLAVE_QDSS_STM,
1133 	.channels = 1,
1134 	.buswidth = 4,
1135 	.num_links = 0,
1136 };
1137 
1138 static struct qcom_icc_node xs_sys_tcu_cfg = {
1139 	.name = "xs_sys_tcu_cfg",
1140 	.id = SM8550_SLAVE_TCU,
1141 	.channels = 1,
1142 	.buswidth = 8,
1143 	.num_links = 0,
1144 };
1145 
1146 static struct qcom_icc_node qhs_aoss = {
1147 	.name = "qhs_aoss",
1148 	.id = SM8550_SLAVE_AOSS,
1149 	.channels = 1,
1150 	.buswidth = 4,
1151 	.num_links = 0,
1152 };
1153 
1154 static struct qcom_icc_node qhs_tme_cfg = {
1155 	.name = "qhs_tme_cfg",
1156 	.id = SM8550_SLAVE_TME_CFG,
1157 	.channels = 1,
1158 	.buswidth = 4,
1159 	.num_links = 0,
1160 };
1161 
1162 static struct qcom_icc_node qss_cfg = {
1163 	.name = "qss_cfg",
1164 	.id = SM8550_SLAVE_CNOC_CFG,
1165 	.channels = 1,
1166 	.buswidth = 4,
1167 	.num_links = 1,
1168 	.links = { SM8550_MASTER_CNOC_CFG },
1169 };
1170 
1171 static struct qcom_icc_node qss_ddrss_cfg = {
1172 	.name = "qss_ddrss_cfg",
1173 	.id = SM8550_SLAVE_DDRSS_CFG,
1174 	.channels = 1,
1175 	.buswidth = 4,
1176 	.num_links = 0,
1177 };
1178 
1179 static struct qcom_icc_node qxs_boot_imem = {
1180 	.name = "qxs_boot_imem",
1181 	.id = SM8550_SLAVE_BOOT_IMEM,
1182 	.channels = 1,
1183 	.buswidth = 8,
1184 	.num_links = 0,
1185 };
1186 
1187 static struct qcom_icc_node qxs_imem = {
1188 	.name = "qxs_imem",
1189 	.id = SM8550_SLAVE_IMEM,
1190 	.channels = 1,
1191 	.buswidth = 8,
1192 	.num_links = 0,
1193 };
1194 
1195 static struct qcom_icc_node xs_pcie_0 = {
1196 	.name = "xs_pcie_0",
1197 	.id = SM8550_SLAVE_PCIE_0,
1198 	.channels = 1,
1199 	.buswidth = 8,
1200 	.num_links = 0,
1201 };
1202 
1203 static struct qcom_icc_node xs_pcie_1 = {
1204 	.name = "xs_pcie_1",
1205 	.id = SM8550_SLAVE_PCIE_1,
1206 	.channels = 1,
1207 	.buswidth = 16,
1208 	.num_links = 0,
1209 };
1210 
1211 static struct qcom_icc_node qns_gem_noc_cnoc = {
1212 	.name = "qns_gem_noc_cnoc",
1213 	.id = SM8550_SLAVE_GEM_NOC_CNOC,
1214 	.channels = 1,
1215 	.buswidth = 16,
1216 	.num_links = 1,
1217 	.links = { SM8550_MASTER_GEM_NOC_CNOC },
1218 };
1219 
1220 static struct qcom_icc_node qns_llcc = {
1221 	.name = "qns_llcc",
1222 	.id = SM8550_SLAVE_LLCC,
1223 	.channels = 4,
1224 	.buswidth = 16,
1225 	.num_links = 1,
1226 	.links = { SM8550_MASTER_LLCC },
1227 };
1228 
1229 static struct qcom_icc_node qns_pcie = {
1230 	.name = "qns_pcie",
1231 	.id = SM8550_SLAVE_MEM_NOC_PCIE_SNOC,
1232 	.channels = 1,
1233 	.buswidth = 8,
1234 	.num_links = 1,
1235 	.links = { SM8550_MASTER_GEM_NOC_PCIE_SNOC },
1236 };
1237 
1238 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
1239 	.name = "qns_lpass_ag_noc_gemnoc",
1240 	.id = SM8550_SLAVE_LPASS_GEM_NOC,
1241 	.channels = 1,
1242 	.buswidth = 16,
1243 	.num_links = 1,
1244 	.links = { SM8550_MASTER_LPASS_GEM_NOC },
1245 };
1246 
1247 static struct qcom_icc_node qns_lpass_aggnoc = {
1248 	.name = "qns_lpass_aggnoc",
1249 	.id = SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
1250 	.channels = 1,
1251 	.buswidth = 16,
1252 	.num_links = 1,
1253 	.links = { SM8550_MASTER_LPIAON_NOC },
1254 };
1255 
1256 static struct qcom_icc_node qns_lpi_aon_noc = {
1257 	.name = "qns_lpi_aon_noc",
1258 	.id = SM8550_SLAVE_LPICX_NOC_LPIAON_NOC,
1259 	.channels = 1,
1260 	.buswidth = 16,
1261 	.num_links = 1,
1262 	.links = { SM8550_MASTER_LPASS_LPINOC },
1263 };
1264 
1265 static struct qcom_icc_node ebi = {
1266 	.name = "ebi",
1267 	.id = SM8550_SLAVE_EBI1,
1268 	.channels = 4,
1269 	.buswidth = 4,
1270 	.num_links = 0,
1271 };
1272 
1273 static struct qcom_icc_node qns_mem_noc_hf = {
1274 	.name = "qns_mem_noc_hf",
1275 	.id = SM8550_SLAVE_MNOC_HF_MEM_NOC,
1276 	.channels = 2,
1277 	.buswidth = 32,
1278 	.num_links = 1,
1279 	.links = { SM8550_MASTER_MNOC_HF_MEM_NOC },
1280 };
1281 
1282 static struct qcom_icc_node qns_mem_noc_sf = {
1283 	.name = "qns_mem_noc_sf",
1284 	.id = SM8550_SLAVE_MNOC_SF_MEM_NOC,
1285 	.channels = 2,
1286 	.buswidth = 32,
1287 	.num_links = 1,
1288 	.links = { SM8550_MASTER_MNOC_SF_MEM_NOC },
1289 };
1290 
1291 static struct qcom_icc_node srvc_mnoc = {
1292 	.name = "srvc_mnoc",
1293 	.id = SM8550_SLAVE_SERVICE_MNOC,
1294 	.channels = 1,
1295 	.buswidth = 4,
1296 	.num_links = 0,
1297 };
1298 
1299 static struct qcom_icc_node qns_nsp_gemnoc = {
1300 	.name = "qns_nsp_gemnoc",
1301 	.id = SM8550_SLAVE_CDSP_MEM_NOC,
1302 	.channels = 2,
1303 	.buswidth = 32,
1304 	.num_links = 1,
1305 	.links = { SM8550_MASTER_COMPUTE_NOC },
1306 };
1307 
1308 static struct qcom_icc_node qns_pcie_mem_noc = {
1309 	.name = "qns_pcie_mem_noc",
1310 	.id = SM8550_SLAVE_ANOC_PCIE_GEM_NOC,
1311 	.channels = 1,
1312 	.buswidth = 16,
1313 	.num_links = 1,
1314 	.links = { SM8550_MASTER_ANOC_PCIE_GEM_NOC },
1315 };
1316 
1317 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1318 	.name = "srvc_pcie_aggre_noc",
1319 	.id = SM8550_SLAVE_SERVICE_PCIE_ANOC,
1320 	.channels = 1,
1321 	.buswidth = 4,
1322 	.num_links = 0,
1323 };
1324 
1325 static struct qcom_icc_node qns_gemnoc_gc = {
1326 	.name = "qns_gemnoc_gc",
1327 	.id = SM8550_SLAVE_SNOC_GEM_NOC_GC,
1328 	.channels = 1,
1329 	.buswidth = 8,
1330 	.num_links = 1,
1331 	.links = { SM8550_MASTER_SNOC_GC_MEM_NOC },
1332 };
1333 
1334 static struct qcom_icc_node qns_gemnoc_sf = {
1335 	.name = "qns_gemnoc_sf",
1336 	.id = SM8550_SLAVE_SNOC_GEM_NOC_SF,
1337 	.channels = 1,
1338 	.buswidth = 16,
1339 	.num_links = 1,
1340 	.links = { SM8550_MASTER_SNOC_SF_MEM_NOC },
1341 };
1342 
1343 static struct qcom_icc_node qns_llcc_disp = {
1344 	.name = "qns_llcc_disp",
1345 	.id = SM8550_SLAVE_LLCC_DISP,
1346 	.channels = 4,
1347 	.buswidth = 16,
1348 	.num_links = 1,
1349 	.links = { SM8550_MASTER_LLCC_DISP },
1350 };
1351 
1352 static struct qcom_icc_node ebi_disp = {
1353 	.name = "ebi_disp",
1354 	.id = SM8550_SLAVE_EBI1_DISP,
1355 	.channels = 4,
1356 	.buswidth = 4,
1357 	.num_links = 0,
1358 };
1359 
1360 static struct qcom_icc_node qns_mem_noc_hf_disp = {
1361 	.name = "qns_mem_noc_hf_disp",
1362 	.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP,
1363 	.channels = 2,
1364 	.buswidth = 32,
1365 	.num_links = 1,
1366 	.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_DISP },
1367 };
1368 
1369 static struct qcom_icc_node qns_llcc_cam_ife_0 = {
1370 	.name = "qns_llcc_cam_ife_0",
1371 	.id = SM8550_SLAVE_LLCC_CAM_IFE_0,
1372 	.channels = 4,
1373 	.buswidth = 16,
1374 	.num_links = 1,
1375 	.links = { SM8550_MASTER_LLCC_CAM_IFE_0 },
1376 };
1377 
1378 static struct qcom_icc_node ebi_cam_ife_0 = {
1379 	.name = "ebi_cam_ife_0",
1380 	.id = SM8550_SLAVE_EBI1_CAM_IFE_0,
1381 	.channels = 4,
1382 	.buswidth = 4,
1383 	.num_links = 0,
1384 };
1385 
1386 static struct qcom_icc_node qns_mem_noc_hf_cam_ife_0 = {
1387 	.name = "qns_mem_noc_hf_cam_ife_0",
1388 	.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0,
1389 	.channels = 2,
1390 	.buswidth = 32,
1391 	.num_links = 1,
1392 	.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 },
1393 };
1394 
1395 static struct qcom_icc_node qns_mem_noc_sf_cam_ife_0 = {
1396 	.name = "qns_mem_noc_sf_cam_ife_0",
1397 	.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0,
1398 	.channels = 2,
1399 	.buswidth = 32,
1400 	.num_links = 1,
1401 	.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 },
1402 };
1403 
1404 static struct qcom_icc_node qns_llcc_cam_ife_1 = {
1405 	.name = "qns_llcc_cam_ife_1",
1406 	.id = SM8550_SLAVE_LLCC_CAM_IFE_1,
1407 	.channels = 4,
1408 	.buswidth = 16,
1409 	.num_links = 1,
1410 	.links = { SM8550_MASTER_LLCC_CAM_IFE_1 },
1411 };
1412 
1413 static struct qcom_icc_node ebi_cam_ife_1 = {
1414 	.name = "ebi_cam_ife_1",
1415 	.id = SM8550_SLAVE_EBI1_CAM_IFE_1,
1416 	.channels = 4,
1417 	.buswidth = 4,
1418 	.num_links = 0,
1419 };
1420 
1421 static struct qcom_icc_node qns_mem_noc_hf_cam_ife_1 = {
1422 	.name = "qns_mem_noc_hf_cam_ife_1",
1423 	.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1,
1424 	.channels = 2,
1425 	.buswidth = 32,
1426 	.num_links = 1,
1427 	.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 },
1428 };
1429 
1430 static struct qcom_icc_node qns_mem_noc_sf_cam_ife_1 = {
1431 	.name = "qns_mem_noc_sf_cam_ife_1",
1432 	.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1,
1433 	.channels = 2,
1434 	.buswidth = 32,
1435 	.num_links = 1,
1436 	.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 },
1437 };
1438 
1439 static struct qcom_icc_node qns_llcc_cam_ife_2 = {
1440 	.name = "qns_llcc_cam_ife_2",
1441 	.id = SM8550_SLAVE_LLCC_CAM_IFE_2,
1442 	.channels = 4,
1443 	.buswidth = 16,
1444 	.num_links = 1,
1445 	.links = { SM8550_MASTER_LLCC_CAM_IFE_2 },
1446 };
1447 
1448 static struct qcom_icc_node ebi_cam_ife_2 = {
1449 	.name = "ebi_cam_ife_2",
1450 	.id = SM8550_SLAVE_EBI1_CAM_IFE_2,
1451 	.channels = 4,
1452 	.buswidth = 4,
1453 	.num_links = 0,
1454 };
1455 
1456 static struct qcom_icc_node qns_mem_noc_hf_cam_ife_2 = {
1457 	.name = "qns_mem_noc_hf_cam_ife_2",
1458 	.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2,
1459 	.channels = 2,
1460 	.buswidth = 32,
1461 	.num_links = 1,
1462 	.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 },
1463 };
1464 
1465 static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
1466 	.name = "qns_mem_noc_sf_cam_ife_2",
1467 	.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2,
1468 	.channels = 2,
1469 	.buswidth = 32,
1470 	.num_links = 1,
1471 	.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 },
1472 };
1473 
1474 static struct qcom_icc_bcm bcm_acv = {
1475 	.name = "ACV",
1476 	.num_nodes = 1,
1477 	.nodes = { &ebi },
1478 };
1479 
1480 static struct qcom_icc_bcm bcm_ce0 = {
1481 	.name = "CE0",
1482 	.num_nodes = 1,
1483 	.nodes = { &qxm_crypto },
1484 };
1485 
1486 static struct qcom_icc_bcm bcm_cn0 = {
1487 	.name = "CN0",
1488 	.keepalive = true,
1489 	.num_nodes = 54,
1490 	.nodes = { &qsm_cfg, &qhs_ahb2phy0,
1491 		   &qhs_ahb2phy1, &qhs_apss,
1492 		   &qhs_camera_cfg, &qhs_clk_ctl,
1493 		   &qhs_cpr_cx, &qhs_cpr_mmcx,
1494 		   &qhs_cpr_mxa, &qhs_cpr_mxc,
1495 		   &qhs_cpr_nspcx, &qhs_crypto0_cfg,
1496 		   &qhs_cx_rdpm, &qhs_gpuss_cfg,
1497 		   &qhs_i2c, &qhs_imem_cfg,
1498 		   &qhs_ipa, &qhs_ipc_router,
1499 		   &qhs_mss_cfg, &qhs_mx_rdpm,
1500 		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1501 		   &qhs_pdm, &qhs_pimem_cfg,
1502 		   &qhs_prng, &qhs_qdss_cfg,
1503 		   &qhs_qspi, &qhs_qup1,
1504 		   &qhs_qup2, &qhs_sdc2,
1505 		   &qhs_sdc4, &qhs_spss_cfg,
1506 		   &qhs_tcsr, &qhs_tlmm,
1507 		   &qhs_ufs_mem_cfg, &qhs_usb3_0,
1508 		   &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1509 		   &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
1510 		   &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
1511 		   &xs_qdss_stm, &xs_sys_tcu_cfg,
1512 		   &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1513 		   &qhs_aoss, &qhs_tme_cfg,
1514 		   &qss_cfg, &qss_ddrss_cfg,
1515 		   &qxs_boot_imem, &qxs_imem,
1516 		   &xs_pcie_0, &xs_pcie_1 },
1517 };
1518 
1519 static struct qcom_icc_bcm bcm_cn1 = {
1520 	.name = "CN1",
1521 	.num_nodes = 1,
1522 	.nodes = { &qhs_display_cfg },
1523 };
1524 
1525 static struct qcom_icc_bcm bcm_co0 = {
1526 	.name = "CO0",
1527 	.num_nodes = 2,
1528 	.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1529 };
1530 
1531 static struct qcom_icc_bcm bcm_lp0 = {
1532 	.name = "LP0",
1533 	.num_nodes = 2,
1534 	.nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1535 };
1536 
1537 static struct qcom_icc_bcm bcm_mc0 = {
1538 	.name = "MC0",
1539 	.keepalive = true,
1540 	.num_nodes = 1,
1541 	.nodes = { &ebi },
1542 };
1543 
1544 static struct qcom_icc_bcm bcm_mm0 = {
1545 	.name = "MM0",
1546 	.num_nodes = 1,
1547 	.nodes = { &qns_mem_noc_hf },
1548 };
1549 
1550 static struct qcom_icc_bcm bcm_mm1 = {
1551 	.name = "MM1",
1552 	.num_nodes = 8,
1553 	.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1554 		   &qnm_camnoc_sf, &qnm_vapss_hcp,
1555 		   &qnm_video_cv_cpu, &qnm_video_cvp,
1556 		   &qnm_video_v_cpu, &qns_mem_noc_sf },
1557 };
1558 
1559 static struct qcom_icc_bcm bcm_qup0 = {
1560 	.name = "QUP0",
1561 	.keepalive = true,
1562 	.vote_scale = 1,
1563 	.num_nodes = 1,
1564 	.nodes = { &qup0_core_slave },
1565 };
1566 
1567 static struct qcom_icc_bcm bcm_qup1 = {
1568 	.name = "QUP1",
1569 	.keepalive = true,
1570 	.vote_scale = 1,
1571 	.num_nodes = 1,
1572 	.nodes = { &qup1_core_slave },
1573 };
1574 
1575 static struct qcom_icc_bcm bcm_qup2 = {
1576 	.name = "QUP2",
1577 	.keepalive = true,
1578 	.vote_scale = 1,
1579 	.num_nodes = 1,
1580 	.nodes = { &qup2_core_slave },
1581 };
1582 
1583 static struct qcom_icc_bcm bcm_sh0 = {
1584 	.name = "SH0",
1585 	.keepalive = true,
1586 	.num_nodes = 1,
1587 	.nodes = { &qns_llcc },
1588 };
1589 
1590 static struct qcom_icc_bcm bcm_sh1 = {
1591 	.name = "SH1",
1592 	.num_nodes = 13,
1593 	.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1594 		   &chm_apps, &qnm_gpu,
1595 		   &qnm_mdsp, &qnm_mnoc_hf,
1596 		   &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1597 		   &qnm_pcie, &qnm_snoc_gc,
1598 		   &qnm_snoc_sf, &qns_gem_noc_cnoc,
1599 		   &qns_pcie },
1600 };
1601 
1602 static struct qcom_icc_bcm bcm_sn0 = {
1603 	.name = "SN0",
1604 	.keepalive = true,
1605 	.num_nodes = 1,
1606 	.nodes = { &qns_gemnoc_sf },
1607 };
1608 
1609 static struct qcom_icc_bcm bcm_sn1 = {
1610 	.name = "SN1",
1611 	.num_nodes = 3,
1612 	.nodes = { &qhm_gic, &xm_gic,
1613 		   &qns_gemnoc_gc },
1614 };
1615 
1616 static struct qcom_icc_bcm bcm_sn2 = {
1617 	.name = "SN2",
1618 	.num_nodes = 1,
1619 	.nodes = { &qnm_aggre1_noc },
1620 };
1621 
1622 static struct qcom_icc_bcm bcm_sn3 = {
1623 	.name = "SN3",
1624 	.num_nodes = 1,
1625 	.nodes = { &qnm_aggre2_noc },
1626 };
1627 
1628 static struct qcom_icc_bcm bcm_sn7 = {
1629 	.name = "SN7",
1630 	.num_nodes = 1,
1631 	.nodes = { &qns_pcie_mem_noc },
1632 };
1633 
1634 static struct qcom_icc_bcm bcm_acv_disp = {
1635 	.name = "ACV",
1636 	.num_nodes = 1,
1637 	.nodes = { &ebi_disp },
1638 };
1639 
1640 static struct qcom_icc_bcm bcm_mc0_disp = {
1641 	.name = "MC0",
1642 	.num_nodes = 1,
1643 	.nodes = { &ebi_disp },
1644 };
1645 
1646 static struct qcom_icc_bcm bcm_mm0_disp = {
1647 	.name = "MM0",
1648 	.num_nodes = 1,
1649 	.nodes = { &qns_mem_noc_hf_disp },
1650 };
1651 
1652 static struct qcom_icc_bcm bcm_sh0_disp = {
1653 	.name = "SH0",
1654 	.num_nodes = 1,
1655 	.nodes = { &qns_llcc_disp },
1656 };
1657 
1658 static struct qcom_icc_bcm bcm_sh1_disp = {
1659 	.name = "SH1",
1660 	.num_nodes = 2,
1661 	.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
1662 };
1663 
1664 static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
1665 	.name = "ACV",
1666 	.num_nodes = 1,
1667 	.nodes = { &ebi_cam_ife_0 },
1668 };
1669 
1670 static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = {
1671 	.name = "MC0",
1672 	.num_nodes = 1,
1673 	.nodes = { &ebi_cam_ife_0 },
1674 };
1675 
1676 static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
1677 	.name = "MM0",
1678 	.num_nodes = 1,
1679 	.nodes = { &qns_mem_noc_hf_cam_ife_0 },
1680 };
1681 
1682 static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
1683 	.name = "MM1",
1684 	.num_nodes = 4,
1685 	.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
1686 		   &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
1687 };
1688 
1689 static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
1690 	.name = "SH0",
1691 	.num_nodes = 1,
1692 	.nodes = { &qns_llcc_cam_ife_0 },
1693 };
1694 
1695 static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
1696 	.name = "SH1",
1697 	.num_nodes = 3,
1698 	.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
1699 		   &qnm_pcie_cam_ife_0 },
1700 };
1701 
1702 static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
1703 	.name = "ACV",
1704 	.num_nodes = 1,
1705 	.nodes = { &ebi_cam_ife_1 },
1706 };
1707 
1708 static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = {
1709 	.name = "MC0",
1710 	.num_nodes = 1,
1711 	.nodes = { &ebi_cam_ife_1 },
1712 };
1713 
1714 static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
1715 	.name = "MM0",
1716 	.num_nodes = 1,
1717 	.nodes = { &qns_mem_noc_hf_cam_ife_1 },
1718 };
1719 
1720 static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
1721 	.name = "MM1",
1722 	.num_nodes = 4,
1723 	.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
1724 		   &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
1725 };
1726 
1727 static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
1728 	.name = "SH0",
1729 	.num_nodes = 1,
1730 	.nodes = { &qns_llcc_cam_ife_1 },
1731 };
1732 
1733 static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
1734 	.name = "SH1",
1735 	.num_nodes = 3,
1736 	.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
1737 		   &qnm_pcie_cam_ife_1 },
1738 };
1739 
1740 static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
1741 	.name = "ACV",
1742 	.num_nodes = 1,
1743 	.nodes = { &ebi_cam_ife_2 },
1744 };
1745 
1746 static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = {
1747 	.name = "MC0",
1748 	.num_nodes = 1,
1749 	.nodes = { &ebi_cam_ife_2 },
1750 };
1751 
1752 static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
1753 	.name = "MM0",
1754 	.num_nodes = 1,
1755 	.nodes = { &qns_mem_noc_hf_cam_ife_2 },
1756 };
1757 
1758 static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
1759 	.name = "MM1",
1760 	.num_nodes = 4,
1761 	.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
1762 		   &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
1763 };
1764 
1765 static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
1766 	.name = "SH0",
1767 	.num_nodes = 1,
1768 	.nodes = { &qns_llcc_cam_ife_2 },
1769 };
1770 
1771 static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
1772 	.name = "SH1",
1773 	.num_nodes = 3,
1774 	.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
1775 		   &qnm_pcie_cam_ife_2 },
1776 };
1777 
1778 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1779 };
1780 
1781 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1782 	[MASTER_QSPI_0] = &qhm_qspi,
1783 	[MASTER_QUP_1] = &qhm_qup1,
1784 	[MASTER_SDCC_4] = &xm_sdc4,
1785 	[MASTER_UFS_MEM] = &xm_ufs_mem,
1786 	[MASTER_USB3_0] = &xm_usb3_0,
1787 	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1788 };
1789 
1790 static const struct qcom_icc_desc sm8550_aggre1_noc = {
1791 	.nodes = aggre1_noc_nodes,
1792 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1793 	.bcms = aggre1_noc_bcms,
1794 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1795 };
1796 
1797 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1798 	&bcm_ce0,
1799 };
1800 
1801 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1802 	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1803 	[MASTER_QUP_2] = &qhm_qup2,
1804 	[MASTER_CRYPTO] = &qxm_crypto,
1805 	[MASTER_IPA] = &qxm_ipa,
1806 	[MASTER_SP] = &qxm_sp,
1807 	[MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1808 	[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1809 	[MASTER_SDCC_2] = &xm_sdc2,
1810 	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1811 };
1812 
1813 static const struct qcom_icc_desc sm8550_aggre2_noc = {
1814 	.nodes = aggre2_noc_nodes,
1815 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1816 	.bcms = aggre2_noc_bcms,
1817 	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1818 };
1819 
1820 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1821 	&bcm_qup0,
1822 	&bcm_qup1,
1823 	&bcm_qup2,
1824 };
1825 
1826 static struct qcom_icc_node * const clk_virt_nodes[] = {
1827 	[MASTER_QUP_CORE_0] = &qup0_core_master,
1828 	[MASTER_QUP_CORE_1] = &qup1_core_master,
1829 	[MASTER_QUP_CORE_2] = &qup2_core_master,
1830 	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1831 	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1832 	[SLAVE_QUP_CORE_2] = &qup2_core_slave,
1833 };
1834 
1835 static const struct qcom_icc_desc sm8550_clk_virt = {
1836 	.nodes = clk_virt_nodes,
1837 	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1838 	.bcms = clk_virt_bcms,
1839 	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1840 };
1841 
1842 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1843 	&bcm_cn0,
1844 	&bcm_cn1,
1845 };
1846 
1847 static struct qcom_icc_node * const config_noc_nodes[] = {
1848 	[MASTER_CNOC_CFG] = &qsm_cfg,
1849 	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1850 	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1851 	[SLAVE_APPSS] = &qhs_apss,
1852 	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1853 	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1854 	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1855 	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1856 	[SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1857 	[SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1858 	[SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1859 	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1860 	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1861 	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1862 	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1863 	[SLAVE_I2C] = &qhs_i2c,
1864 	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1865 	[SLAVE_IPA_CFG] = &qhs_ipa,
1866 	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1867 	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1868 	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1869 	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1870 	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1871 	[SLAVE_PDM] = &qhs_pdm,
1872 	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1873 	[SLAVE_PRNG] = &qhs_prng,
1874 	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1875 	[SLAVE_QSPI_0] = &qhs_qspi,
1876 	[SLAVE_QUP_1] = &qhs_qup1,
1877 	[SLAVE_QUP_2] = &qhs_qup2,
1878 	[SLAVE_SDCC_2] = &qhs_sdc2,
1879 	[SLAVE_SDCC_4] = &qhs_sdc4,
1880 	[SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1881 	[SLAVE_TCSR] = &qhs_tcsr,
1882 	[SLAVE_TLMM] = &qhs_tlmm,
1883 	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1884 	[SLAVE_USB3_0] = &qhs_usb3_0,
1885 	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1886 	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1887 	[SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
1888 	[SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1889 	[SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
1890 	[SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1891 	[SLAVE_QDSS_STM] = &xs_qdss_stm,
1892 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
1893 };
1894 
1895 static const struct qcom_icc_desc sm8550_config_noc = {
1896 	.nodes = config_noc_nodes,
1897 	.num_nodes = ARRAY_SIZE(config_noc_nodes),
1898 	.bcms = config_noc_bcms,
1899 	.num_bcms = ARRAY_SIZE(config_noc_bcms),
1900 };
1901 
1902 static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1903 	&bcm_cn0,
1904 };
1905 
1906 static struct qcom_icc_node * const cnoc_main_nodes[] = {
1907 	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1908 	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1909 	[SLAVE_AOSS] = &qhs_aoss,
1910 	[SLAVE_TME_CFG] = &qhs_tme_cfg,
1911 	[SLAVE_CNOC_CFG] = &qss_cfg,
1912 	[SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1913 	[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1914 	[SLAVE_IMEM] = &qxs_imem,
1915 	[SLAVE_PCIE_0] = &xs_pcie_0,
1916 	[SLAVE_PCIE_1] = &xs_pcie_1,
1917 };
1918 
1919 static const struct qcom_icc_desc sm8550_cnoc_main = {
1920 	.nodes = cnoc_main_nodes,
1921 	.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1922 	.bcms = cnoc_main_bcms,
1923 	.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1924 };
1925 
1926 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1927 	&bcm_sh0,
1928 	&bcm_sh1,
1929 	&bcm_sh0_disp,
1930 	&bcm_sh1_disp,
1931 	&bcm_sh0_cam_ife_0,
1932 	&bcm_sh1_cam_ife_0,
1933 	&bcm_sh0_cam_ife_1,
1934 	&bcm_sh1_cam_ife_1,
1935 	&bcm_sh0_cam_ife_2,
1936 	&bcm_sh1_cam_ife_2,
1937 };
1938 
1939 static struct qcom_icc_node * const gem_noc_nodes[] = {
1940 	[MASTER_GPU_TCU] = &alm_gpu_tcu,
1941 	[MASTER_SYS_TCU] = &alm_sys_tcu,
1942 	[MASTER_APPSS_PROC] = &chm_apps,
1943 	[MASTER_GFX3D] = &qnm_gpu,
1944 	[MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1945 	[MASTER_MSS_PROC] = &qnm_mdsp,
1946 	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1947 	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1948 	[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1949 	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1950 	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1951 	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1952 	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1953 	[SLAVE_LLCC] = &qns_llcc,
1954 	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1955 	[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1956 	[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1957 	[SLAVE_LLCC_DISP] = &qns_llcc_disp,
1958 	[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_hf_cam_ife_0,
1959 	[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_sf_cam_ife_0,
1960 	[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0] = &qnm_pcie_cam_ife_0,
1961 	[SLAVE_LLCC_CAM_IFE_0] = &qns_llcc_cam_ife_0,
1962 	[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_hf_cam_ife_1,
1963 	[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_sf_cam_ife_1,
1964 	[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1] = &qnm_pcie_cam_ife_1,
1965 	[SLAVE_LLCC_CAM_IFE_1] = &qns_llcc_cam_ife_1,
1966 	[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_hf_cam_ife_2,
1967 	[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_sf_cam_ife_2,
1968 	[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2] = &qnm_pcie_cam_ife_2,
1969 	[SLAVE_LLCC_CAM_IFE_2] = &qns_llcc_cam_ife_2,
1970 };
1971 
1972 static const struct qcom_icc_desc sm8550_gem_noc = {
1973 	.nodes = gem_noc_nodes,
1974 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1975 	.bcms = gem_noc_bcms,
1976 	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1977 };
1978 
1979 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1980 };
1981 
1982 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1983 	[MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1984 	[SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1985 };
1986 
1987 static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
1988 	.nodes = lpass_ag_noc_nodes,
1989 	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1990 	.bcms = lpass_ag_noc_bcms,
1991 	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1992 };
1993 
1994 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1995 	&bcm_lp0,
1996 };
1997 
1998 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1999 	[MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
2000 	[SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
2001 };
2002 
2003 static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
2004 	.nodes = lpass_lpiaon_noc_nodes,
2005 	.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
2006 	.bcms = lpass_lpiaon_noc_bcms,
2007 	.num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
2008 };
2009 
2010 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = {
2011 };
2012 
2013 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
2014 	[MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim,
2015 	[SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
2016 };
2017 
2018 static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
2019 	.nodes = lpass_lpicx_noc_nodes,
2020 	.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
2021 	.bcms = lpass_lpicx_noc_bcms,
2022 	.num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms),
2023 };
2024 
2025 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2026 	&bcm_acv,
2027 	&bcm_mc0,
2028 	&bcm_acv_disp,
2029 	&bcm_mc0_disp,
2030 	&bcm_acv_cam_ife_0,
2031 	&bcm_mc0_cam_ife_0,
2032 	&bcm_acv_cam_ife_1,
2033 	&bcm_mc0_cam_ife_1,
2034 	&bcm_acv_cam_ife_2,
2035 	&bcm_mc0_cam_ife_2,
2036 };
2037 
2038 static struct qcom_icc_node * const mc_virt_nodes[] = {
2039 	[MASTER_LLCC] = &llcc_mc,
2040 	[SLAVE_EBI1] = &ebi,
2041 	[MASTER_LLCC_DISP] = &llcc_mc_disp,
2042 	[SLAVE_EBI1_DISP] = &ebi_disp,
2043 	[MASTER_LLCC_CAM_IFE_0] = &llcc_mc_cam_ife_0,
2044 	[SLAVE_EBI1_CAM_IFE_0] = &ebi_cam_ife_0,
2045 	[MASTER_LLCC_CAM_IFE_1] = &llcc_mc_cam_ife_1,
2046 	[SLAVE_EBI1_CAM_IFE_1] = &ebi_cam_ife_1,
2047 	[MASTER_LLCC_CAM_IFE_2] = &llcc_mc_cam_ife_2,
2048 	[SLAVE_EBI1_CAM_IFE_2] = &ebi_cam_ife_2,
2049 };
2050 
2051 static const struct qcom_icc_desc sm8550_mc_virt = {
2052 	.nodes = mc_virt_nodes,
2053 	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
2054 	.bcms = mc_virt_bcms,
2055 	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
2056 };
2057 
2058 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2059 	&bcm_mm0,
2060 	&bcm_mm1,
2061 	&bcm_mm0_disp,
2062 	&bcm_mm0_cam_ife_0,
2063 	&bcm_mm1_cam_ife_0,
2064 	&bcm_mm0_cam_ife_1,
2065 	&bcm_mm1_cam_ife_1,
2066 	&bcm_mm0_cam_ife_2,
2067 	&bcm_mm1_cam_ife_2,
2068 };
2069 
2070 static struct qcom_icc_node * const mmss_noc_nodes[] = {
2071 	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2072 	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2073 	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
2074 	[MASTER_MDP] = &qnm_mdp,
2075 	[MASTER_CDSP_HCP] = &qnm_vapss_hcp,
2076 	[MASTER_VIDEO] = &qnm_video,
2077 	[MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
2078 	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
2079 	[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
2080 	[MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
2081 	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2082 	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2083 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
2084 	[MASTER_MDP_DISP] = &qnm_mdp_disp,
2085 	[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
2086 	[MASTER_CAMNOC_HF_CAM_IFE_0] = &qnm_camnoc_hf_cam_ife_0,
2087 	[MASTER_CAMNOC_ICP_CAM_IFE_0] = &qnm_camnoc_icp_cam_ife_0,
2088 	[MASTER_CAMNOC_SF_CAM_IFE_0] = &qnm_camnoc_sf_cam_ife_0,
2089 	[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_hf_cam_ife_0,
2090 	[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_sf_cam_ife_0,
2091 	[MASTER_CAMNOC_HF_CAM_IFE_1] = &qnm_camnoc_hf_cam_ife_1,
2092 	[MASTER_CAMNOC_ICP_CAM_IFE_1] = &qnm_camnoc_icp_cam_ife_1,
2093 	[MASTER_CAMNOC_SF_CAM_IFE_1] = &qnm_camnoc_sf_cam_ife_1,
2094 	[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_hf_cam_ife_1,
2095 	[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_sf_cam_ife_1,
2096 	[MASTER_CAMNOC_HF_CAM_IFE_2] = &qnm_camnoc_hf_cam_ife_2,
2097 	[MASTER_CAMNOC_ICP_CAM_IFE_2] = &qnm_camnoc_icp_cam_ife_2,
2098 	[MASTER_CAMNOC_SF_CAM_IFE_2] = &qnm_camnoc_sf_cam_ife_2,
2099 	[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_hf_cam_ife_2,
2100 	[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_sf_cam_ife_2,
2101 };
2102 
2103 static const struct qcom_icc_desc sm8550_mmss_noc = {
2104 	.nodes = mmss_noc_nodes,
2105 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2106 	.bcms = mmss_noc_bcms,
2107 	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2108 };
2109 
2110 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
2111 	&bcm_co0,
2112 };
2113 
2114 static struct qcom_icc_node * const nsp_noc_nodes[] = {
2115 	[MASTER_CDSP_PROC] = &qxm_nsp,
2116 	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2117 };
2118 
2119 static const struct qcom_icc_desc sm8550_nsp_noc = {
2120 	.nodes = nsp_noc_nodes,
2121 	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
2122 	.bcms = nsp_noc_bcms,
2123 	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
2124 };
2125 
2126 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
2127 	&bcm_sn7,
2128 };
2129 
2130 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
2131 	[MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
2132 	[MASTER_PCIE_0] = &xm_pcie3_0,
2133 	[MASTER_PCIE_1] = &xm_pcie3_1,
2134 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
2135 	[SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
2136 };
2137 
2138 static const struct qcom_icc_desc sm8550_pcie_anoc = {
2139 	.nodes = pcie_anoc_nodes,
2140 	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2141 	.bcms = pcie_anoc_bcms,
2142 	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2143 };
2144 
2145 static struct qcom_icc_bcm * const system_noc_bcms[] = {
2146 	&bcm_sn0,
2147 	&bcm_sn1,
2148 	&bcm_sn2,
2149 	&bcm_sn3,
2150 };
2151 
2152 static struct qcom_icc_node * const system_noc_nodes[] = {
2153 	[MASTER_GIC_AHB] = &qhm_gic,
2154 	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2155 	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2156 	[MASTER_GIC] = &xm_gic,
2157 	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2158 	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2159 };
2160 
2161 static const struct qcom_icc_desc sm8550_system_noc = {
2162 	.nodes = system_noc_nodes,
2163 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
2164 	.bcms = system_noc_bcms,
2165 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
2166 };
2167 
2168 static int qnoc_probe(struct platform_device *pdev)
2169 {
2170 	const struct qcom_icc_desc *desc;
2171 	struct icc_onecell_data *data;
2172 	struct icc_provider *provider;
2173 	struct qcom_icc_node * const *qnodes;
2174 	struct qcom_icc_provider *qp;
2175 	struct icc_node *node;
2176 	size_t num_nodes, i;
2177 	int ret;
2178 
2179 	desc = device_get_match_data(&pdev->dev);
2180 	if (!desc)
2181 		return -EINVAL;
2182 
2183 	qnodes = desc->nodes;
2184 	num_nodes = desc->num_nodes;
2185 
2186 	qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
2187 	if (!qp)
2188 		return -ENOMEM;
2189 
2190 	data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
2191 	if (!data)
2192 		return -ENOMEM;
2193 
2194 	provider = &qp->provider;
2195 	provider->dev = &pdev->dev;
2196 	provider->set = qcom_icc_set;
2197 	provider->pre_aggregate = qcom_icc_pre_aggregate;
2198 	provider->aggregate = qcom_icc_aggregate;
2199 	provider->xlate_extended = qcom_icc_xlate_extended;
2200 	INIT_LIST_HEAD(&provider->nodes);
2201 	provider->data = data;
2202 
2203 	qp->dev = &pdev->dev;
2204 	qp->bcms = desc->bcms;
2205 	qp->num_bcms = desc->num_bcms;
2206 
2207 	qp->voter = of_bcm_voter_get(qp->dev, NULL);
2208 	if (IS_ERR(qp->voter))
2209 		return PTR_ERR(qp->voter);
2210 
2211 	ret = icc_provider_add(provider);
2212 	if (ret) {
2213 		dev_err_probe(&pdev->dev, ret,
2214 			      "error adding interconnect provider\n");
2215 		return ret;
2216 	}
2217 
2218 	for (i = 0; i < qp->num_bcms; i++)
2219 		qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
2220 
2221 	for (i = 0; i < num_nodes; i++) {
2222 		size_t j;
2223 
2224 		if (!qnodes[i])
2225 			continue;
2226 
2227 		node = icc_node_create(qnodes[i]->id);
2228 		if (IS_ERR(node)) {
2229 			ret = PTR_ERR(node);
2230 			goto err;
2231 		}
2232 
2233 		node->name = qnodes[i]->name;
2234 		node->data = qnodes[i];
2235 		icc_node_add(node, provider);
2236 
2237 		for (j = 0; j < qnodes[i]->num_links; j++)
2238 			icc_link_create(node, qnodes[i]->links[j]);
2239 
2240 		data->nodes[i] = node;
2241 	}
2242 	data->num_nodes = num_nodes;
2243 
2244 	platform_set_drvdata(pdev, qp);
2245 
2246 	return 0;
2247 err:
2248 	icc_nodes_remove(provider);
2249 	icc_provider_del(provider);
2250 	return ret;
2251 }
2252 
2253 static int qnoc_remove(struct platform_device *pdev)
2254 {
2255 	struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
2256 
2257 	icc_nodes_remove(&qp->provider);
2258 	icc_provider_del(&qp->provider);
2259 
2260 	return 0;
2261 }
2262 
2263 static const struct of_device_id qnoc_of_match[] = {
2264 	{ .compatible = "qcom,sm8550-aggre1-noc",
2265 	  .data = &sm8550_aggre1_noc},
2266 	{ .compatible = "qcom,sm8550-aggre2-noc",
2267 	  .data = &sm8550_aggre2_noc},
2268 	{ .compatible = "qcom,sm8550-clk-virt",
2269 	  .data = &sm8550_clk_virt},
2270 	{ .compatible = "qcom,sm8550-config-noc",
2271 	  .data = &sm8550_config_noc},
2272 	{ .compatible = "qcom,sm8550-cnoc-main",
2273 	  .data = &sm8550_cnoc_main},
2274 	{ .compatible = "qcom,sm8550-gem-noc",
2275 	  .data = &sm8550_gem_noc},
2276 	{ .compatible = "qcom,sm8550-lpass-ag-noc",
2277 	  .data = &sm8550_lpass_ag_noc},
2278 	{ .compatible = "qcom,sm8550-lpass-lpiaon-noc",
2279 	  .data = &sm8550_lpass_lpiaon_noc},
2280 	{ .compatible = "qcom,sm8550-lpass-lpicx-noc",
2281 	  .data = &sm8550_lpass_lpicx_noc},
2282 	{ .compatible = "qcom,sm8550-mc-virt",
2283 	  .data = &sm8550_mc_virt},
2284 	{ .compatible = "qcom,sm8550-mmss-noc",
2285 	  .data = &sm8550_mmss_noc},
2286 	{ .compatible = "qcom,sm8550-nsp-noc",
2287 	  .data = &sm8550_nsp_noc},
2288 	{ .compatible = "qcom,sm8550-pcie-anoc",
2289 	  .data = &sm8550_pcie_anoc},
2290 	{ .compatible = "qcom,sm8550-system-noc",
2291 	  .data = &sm8550_system_noc},
2292 	{ }
2293 };
2294 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2295 
2296 static struct platform_driver qnoc_driver = {
2297 	.probe = qnoc_probe,
2298 	.remove = qnoc_remove,
2299 	.driver = {
2300 		.name = "qnoc-sm8550",
2301 		.of_match_table = qnoc_of_match,
2302 	},
2303 };
2304 
2305 static int __init qnoc_driver_init(void)
2306 {
2307 	return platform_driver_register(&qnoc_driver);
2308 }
2309 core_initcall(qnoc_driver_init);
2310 
2311 static void __exit qnoc_driver_exit(void)
2312 {
2313 	platform_driver_unregister(&qnoc_driver);
2314 }
2315 module_exit(qnoc_driver_exit);
2316 
2317 MODULE_DESCRIPTION("sm8550 NoC driver");
2318 MODULE_LICENSE("GPL");
2319