1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021, Linaro Limited
5  */
6 
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <dt-bindings/interconnect/qcom,sm8450.h>
13 
14 #include "bcm-voter.h"
15 #include "icc-rpmh.h"
16 #include "sm8450.h"
17 
18 static struct qcom_icc_node qhm_qspi = {
19 	.name = "qhm_qspi",
20 	.id = SM8450_MASTER_QSPI_0,
21 	.channels = 1,
22 	.buswidth = 4,
23 	.num_links = 1,
24 	.links = { SM8450_SLAVE_A1NOC_SNOC },
25 };
26 
27 static struct qcom_icc_node qhm_qup1 = {
28 	.name = "qhm_qup1",
29 	.id = SM8450_MASTER_QUP_1,
30 	.channels = 1,
31 	.buswidth = 4,
32 	.num_links = 1,
33 	.links = { SM8450_SLAVE_A1NOC_SNOC },
34 };
35 
36 static struct qcom_icc_node qnm_a1noc_cfg = {
37 	.name = "qnm_a1noc_cfg",
38 	.id = SM8450_MASTER_A1NOC_CFG,
39 	.channels = 1,
40 	.buswidth = 4,
41 	.num_links = 1,
42 	.links = { SM8450_SLAVE_SERVICE_A1NOC },
43 };
44 
45 static struct qcom_icc_node xm_sdc4 = {
46 	.name = "xm_sdc4",
47 	.id = SM8450_MASTER_SDCC_4,
48 	.channels = 1,
49 	.buswidth = 8,
50 	.num_links = 1,
51 	.links = { SM8450_SLAVE_A1NOC_SNOC },
52 };
53 
54 static struct qcom_icc_node xm_ufs_mem = {
55 	.name = "xm_ufs_mem",
56 	.id = SM8450_MASTER_UFS_MEM,
57 	.channels = 1,
58 	.buswidth = 8,
59 	.num_links = 1,
60 	.links = { SM8450_SLAVE_A1NOC_SNOC },
61 };
62 
63 static struct qcom_icc_node xm_usb3_0 = {
64 	.name = "xm_usb3_0",
65 	.id = SM8450_MASTER_USB3_0,
66 	.channels = 1,
67 	.buswidth = 8,
68 	.num_links = 1,
69 	.links = { SM8450_SLAVE_A1NOC_SNOC },
70 };
71 
72 static struct qcom_icc_node qhm_qdss_bam = {
73 	.name = "qhm_qdss_bam",
74 	.id = SM8450_MASTER_QDSS_BAM,
75 	.channels = 1,
76 	.buswidth = 4,
77 	.num_links = 1,
78 	.links = { SM8450_SLAVE_A2NOC_SNOC },
79 };
80 
81 static struct qcom_icc_node qhm_qup0 = {
82 	.name = "qhm_qup0",
83 	.id = SM8450_MASTER_QUP_0,
84 	.channels = 1,
85 	.buswidth = 4,
86 	.num_links = 1,
87 	.links = { SM8450_SLAVE_A2NOC_SNOC },
88 };
89 
90 static struct qcom_icc_node qhm_qup2 = {
91 	.name = "qhm_qup2",
92 	.id = SM8450_MASTER_QUP_2,
93 	.channels = 1,
94 	.buswidth = 4,
95 	.num_links = 1,
96 	.links = { SM8450_SLAVE_A2NOC_SNOC },
97 };
98 
99 static struct qcom_icc_node qnm_a2noc_cfg = {
100 	.name = "qnm_a2noc_cfg",
101 	.id = SM8450_MASTER_A2NOC_CFG,
102 	.channels = 1,
103 	.buswidth = 4,
104 	.num_links = 1,
105 	.links = { SM8450_SLAVE_SERVICE_A2NOC },
106 };
107 
108 static struct qcom_icc_node qxm_crypto = {
109 	.name = "qxm_crypto",
110 	.id = SM8450_MASTER_CRYPTO,
111 	.channels = 1,
112 	.buswidth = 8,
113 	.num_links = 1,
114 	.links = { SM8450_SLAVE_A2NOC_SNOC },
115 };
116 
117 static struct qcom_icc_node qxm_ipa = {
118 	.name = "qxm_ipa",
119 	.id = SM8450_MASTER_IPA,
120 	.channels = 1,
121 	.buswidth = 8,
122 	.num_links = 1,
123 	.links = { SM8450_SLAVE_A2NOC_SNOC },
124 };
125 
126 static struct qcom_icc_node qxm_sensorss_q6 = {
127 	.name = "qxm_sensorss_q6",
128 	.id = SM8450_MASTER_SENSORS_PROC,
129 	.channels = 1,
130 	.buswidth = 8,
131 	.num_links = 1,
132 	.links = { SM8450_SLAVE_A2NOC_SNOC },
133 };
134 
135 static struct qcom_icc_node qxm_sp = {
136 	.name = "qxm_sp",
137 	.id = SM8450_MASTER_SP,
138 	.channels = 1,
139 	.buswidth = 8,
140 	.num_links = 1,
141 	.links = { SM8450_SLAVE_A2NOC_SNOC },
142 };
143 
144 static struct qcom_icc_node xm_qdss_etr_0 = {
145 	.name = "xm_qdss_etr_0",
146 	.id = SM8450_MASTER_QDSS_ETR,
147 	.channels = 1,
148 	.buswidth = 8,
149 	.num_links = 1,
150 	.links = { SM8450_SLAVE_A2NOC_SNOC },
151 };
152 
153 static struct qcom_icc_node xm_qdss_etr_1 = {
154 	.name = "xm_qdss_etr_1",
155 	.id = SM8450_MASTER_QDSS_ETR_1,
156 	.channels = 1,
157 	.buswidth = 8,
158 	.num_links = 1,
159 	.links = { SM8450_SLAVE_A2NOC_SNOC },
160 };
161 
162 static struct qcom_icc_node xm_sdc2 = {
163 	.name = "xm_sdc2",
164 	.id = SM8450_MASTER_SDCC_2,
165 	.channels = 1,
166 	.buswidth = 8,
167 	.num_links = 1,
168 	.links = { SM8450_SLAVE_A2NOC_SNOC },
169 };
170 
171 static struct qcom_icc_node qup0_core_master = {
172 	.name = "qup0_core_master",
173 	.id = SM8450_MASTER_QUP_CORE_0,
174 	.channels = 1,
175 	.buswidth = 4,
176 	.num_links = 1,
177 	.links = { SM8450_SLAVE_QUP_CORE_0 },
178 };
179 
180 static struct qcom_icc_node qup1_core_master = {
181 	.name = "qup1_core_master",
182 	.id = SM8450_MASTER_QUP_CORE_1,
183 	.channels = 1,
184 	.buswidth = 4,
185 	.num_links = 1,
186 	.links = { SM8450_SLAVE_QUP_CORE_1 },
187 };
188 
189 static struct qcom_icc_node qup2_core_master = {
190 	.name = "qup2_core_master",
191 	.id = SM8450_MASTER_QUP_CORE_2,
192 	.channels = 1,
193 	.buswidth = 4,
194 	.num_links = 1,
195 	.links = { SM8450_SLAVE_QUP_CORE_2 },
196 };
197 
198 static struct qcom_icc_node qnm_gemnoc_cnoc = {
199 	.name = "qnm_gemnoc_cnoc",
200 	.id = SM8450_MASTER_GEM_NOC_CNOC,
201 	.channels = 1,
202 	.buswidth = 16,
203 	.num_links = 51,
204 	.links = { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH,
205 		   SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG,
206 		   SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG,
207 		   SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG,
208 		   SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG,
209 		   SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM,
210 		   SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG,
211 		   SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG,
212 		   SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS,
213 		   SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM,
214 		   SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG,
215 		   SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG,
216 		   SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG,
217 		   SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0,
218 		   SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2,
219 		   SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4,
220 		   SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR,
221 		   SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG,
222 		   SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0,
223 		   SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG,
224 		   SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG,
225 		   SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG,
226 		   SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG,
227 		   SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM,
228 		   SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM,
229 		   SM8450_SLAVE_TCU },
230 };
231 
232 static struct qcom_icc_node qnm_gemnoc_pcie = {
233 	.name = "qnm_gemnoc_pcie",
234 	.id = SM8450_MASTER_GEM_NOC_PCIE_SNOC,
235 	.channels = 1,
236 	.buswidth = 8,
237 	.num_links = 2,
238 	.links = { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 },
239 };
240 
241 static struct qcom_icc_node alm_gpu_tcu = {
242 	.name = "alm_gpu_tcu",
243 	.id = SM8450_MASTER_GPU_TCU,
244 	.channels = 1,
245 	.buswidth = 8,
246 	.num_links = 2,
247 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
248 };
249 
250 static struct qcom_icc_node alm_sys_tcu = {
251 	.name = "alm_sys_tcu",
252 	.id = SM8450_MASTER_SYS_TCU,
253 	.channels = 1,
254 	.buswidth = 8,
255 	.num_links = 2,
256 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
257 };
258 
259 static struct qcom_icc_node chm_apps = {
260 	.name = "chm_apps",
261 	.id = SM8450_MASTER_APPSS_PROC,
262 	.channels = 3,
263 	.buswidth = 32,
264 	.num_links = 3,
265 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
266 		   SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
267 };
268 
269 static struct qcom_icc_node qnm_gpu = {
270 	.name = "qnm_gpu",
271 	.id = SM8450_MASTER_GFX3D,
272 	.channels = 2,
273 	.buswidth = 32,
274 	.num_links = 2,
275 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
276 };
277 
278 static struct qcom_icc_node qnm_mdsp = {
279 	.name = "qnm_mdsp",
280 	.id = SM8450_MASTER_MSS_PROC,
281 	.channels = 1,
282 	.buswidth = 16,
283 	.num_links = 3,
284 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
285 		   SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
286 };
287 
288 static struct qcom_icc_node qnm_mnoc_hf = {
289 	.name = "qnm_mnoc_hf",
290 	.id = SM8450_MASTER_MNOC_HF_MEM_NOC,
291 	.channels = 2,
292 	.buswidth = 32,
293 	.num_links = 1,
294 	.links = { SM8450_SLAVE_LLCC },
295 };
296 
297 static struct qcom_icc_node qnm_mnoc_sf = {
298 	.name = "qnm_mnoc_sf",
299 	.id = SM8450_MASTER_MNOC_SF_MEM_NOC,
300 	.channels = 2,
301 	.buswidth = 32,
302 	.num_links = 2,
303 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
304 };
305 
306 static struct qcom_icc_node qnm_nsp_gemnoc = {
307 	.name = "qnm_nsp_gemnoc",
308 	.id = SM8450_MASTER_COMPUTE_NOC,
309 	.channels = 2,
310 	.buswidth = 32,
311 	.num_links = 2,
312 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
313 };
314 
315 static struct qcom_icc_node qnm_pcie = {
316 	.name = "qnm_pcie",
317 	.id = SM8450_MASTER_ANOC_PCIE_GEM_NOC,
318 	.channels = 1,
319 	.buswidth = 16,
320 	.num_links = 2,
321 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
322 };
323 
324 static struct qcom_icc_node qnm_snoc_gc = {
325 	.name = "qnm_snoc_gc",
326 	.id = SM8450_MASTER_SNOC_GC_MEM_NOC,
327 	.channels = 1,
328 	.buswidth = 8,
329 	.num_links = 1,
330 	.links = { SM8450_SLAVE_LLCC },
331 };
332 
333 static struct qcom_icc_node qnm_snoc_sf = {
334 	.name = "qnm_snoc_sf",
335 	.id = SM8450_MASTER_SNOC_SF_MEM_NOC,
336 	.channels = 1,
337 	.buswidth = 16,
338 	.num_links = 3,
339 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
340 		   SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
341 };
342 
343 static struct qcom_icc_node qhm_config_noc = {
344 	.name = "qhm_config_noc",
345 	.id = SM8450_MASTER_CNOC_LPASS_AG_NOC,
346 	.channels = 1,
347 	.buswidth = 4,
348 	.num_links = 6,
349 	.links = { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG,
350 		   SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG,
351 		   SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC },
352 };
353 
354 static struct qcom_icc_node qxm_lpass_dsp = {
355 	.name = "qxm_lpass_dsp",
356 	.id = SM8450_MASTER_LPASS_PROC,
357 	.channels = 1,
358 	.buswidth = 8,
359 	.num_links = 4,
360 	.links = { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC,
361 		   SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC },
362 };
363 
364 static struct qcom_icc_node llcc_mc = {
365 	.name = "llcc_mc",
366 	.id = SM8450_MASTER_LLCC,
367 	.channels = 4,
368 	.buswidth = 4,
369 	.num_links = 1,
370 	.links = { SM8450_SLAVE_EBI1 },
371 };
372 
373 static struct qcom_icc_node qnm_camnoc_hf = {
374 	.name = "qnm_camnoc_hf",
375 	.id = SM8450_MASTER_CAMNOC_HF,
376 	.channels = 2,
377 	.buswidth = 32,
378 	.num_links = 1,
379 	.links = { SM8450_SLAVE_MNOC_HF_MEM_NOC },
380 };
381 
382 static struct qcom_icc_node qnm_camnoc_icp = {
383 	.name = "qnm_camnoc_icp",
384 	.id = SM8450_MASTER_CAMNOC_ICP,
385 	.channels = 1,
386 	.buswidth = 8,
387 	.num_links = 1,
388 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
389 };
390 
391 static struct qcom_icc_node qnm_camnoc_sf = {
392 	.name = "qnm_camnoc_sf",
393 	.id = SM8450_MASTER_CAMNOC_SF,
394 	.channels = 2,
395 	.buswidth = 32,
396 	.num_links = 1,
397 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
398 };
399 
400 static struct qcom_icc_node qnm_mdp = {
401 	.name = "qnm_mdp",
402 	.id = SM8450_MASTER_MDP,
403 	.channels = 2,
404 	.buswidth = 32,
405 	.num_links = 1,
406 	.links = { SM8450_SLAVE_MNOC_HF_MEM_NOC },
407 };
408 
409 static struct qcom_icc_node qnm_mnoc_cfg = {
410 	.name = "qnm_mnoc_cfg",
411 	.id = SM8450_MASTER_CNOC_MNOC_CFG,
412 	.channels = 1,
413 	.buswidth = 4,
414 	.num_links = 1,
415 	.links = { SM8450_SLAVE_SERVICE_MNOC },
416 };
417 
418 static struct qcom_icc_node qnm_rot = {
419 	.name = "qnm_rot",
420 	.id = SM8450_MASTER_ROTATOR,
421 	.channels = 1,
422 	.buswidth = 32,
423 	.num_links = 1,
424 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
425 };
426 
427 static struct qcom_icc_node qnm_vapss_hcp = {
428 	.name = "qnm_vapss_hcp",
429 	.id = SM8450_MASTER_CDSP_HCP,
430 	.channels = 1,
431 	.buswidth = 32,
432 	.num_links = 1,
433 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
434 };
435 
436 static struct qcom_icc_node qnm_video = {
437 	.name = "qnm_video",
438 	.id = SM8450_MASTER_VIDEO,
439 	.channels = 2,
440 	.buswidth = 32,
441 	.num_links = 1,
442 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
443 };
444 
445 static struct qcom_icc_node qnm_video_cv_cpu = {
446 	.name = "qnm_video_cv_cpu",
447 	.id = SM8450_MASTER_VIDEO_CV_PROC,
448 	.channels = 1,
449 	.buswidth = 8,
450 	.num_links = 1,
451 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
452 };
453 
454 static struct qcom_icc_node qnm_video_cvp = {
455 	.name = "qnm_video_cvp",
456 	.id = SM8450_MASTER_VIDEO_PROC,
457 	.channels = 1,
458 	.buswidth = 32,
459 	.num_links = 1,
460 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
461 };
462 
463 static struct qcom_icc_node qnm_video_v_cpu = {
464 	.name = "qnm_video_v_cpu",
465 	.id = SM8450_MASTER_VIDEO_V_PROC,
466 	.channels = 1,
467 	.buswidth = 8,
468 	.num_links = 1,
469 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
470 };
471 
472 static struct qcom_icc_node qhm_nsp_noc_config = {
473 	.name = "qhm_nsp_noc_config",
474 	.id = SM8450_MASTER_CDSP_NOC_CFG,
475 	.channels = 1,
476 	.buswidth = 4,
477 	.num_links = 1,
478 	.links = { SM8450_SLAVE_SERVICE_NSP_NOC },
479 };
480 
481 static struct qcom_icc_node qxm_nsp = {
482 	.name = "qxm_nsp",
483 	.id = SM8450_MASTER_CDSP_PROC,
484 	.channels = 2,
485 	.buswidth = 32,
486 	.num_links = 1,
487 	.links = { SM8450_SLAVE_CDSP_MEM_NOC },
488 };
489 
490 static struct qcom_icc_node qnm_pcie_anoc_cfg = {
491 	.name = "qnm_pcie_anoc_cfg",
492 	.id = SM8450_MASTER_PCIE_ANOC_CFG,
493 	.channels = 1,
494 	.buswidth = 4,
495 	.num_links = 1,
496 	.links = { SM8450_SLAVE_SERVICE_PCIE_ANOC },
497 };
498 
499 static struct qcom_icc_node xm_pcie3_0 = {
500 	.name = "xm_pcie3_0",
501 	.id = SM8450_MASTER_PCIE_0,
502 	.channels = 1,
503 	.buswidth = 8,
504 	.num_links = 1,
505 	.links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC },
506 };
507 
508 static struct qcom_icc_node xm_pcie3_1 = {
509 	.name = "xm_pcie3_1",
510 	.id = SM8450_MASTER_PCIE_1,
511 	.channels = 1,
512 	.buswidth = 8,
513 	.num_links = 1,
514 	.links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC },
515 };
516 
517 static struct qcom_icc_node qhm_gic = {
518 	.name = "qhm_gic",
519 	.id = SM8450_MASTER_GIC_AHB,
520 	.channels = 1,
521 	.buswidth = 4,
522 	.num_links = 1,
523 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
524 };
525 
526 static struct qcom_icc_node qnm_aggre1_noc = {
527 	.name = "qnm_aggre1_noc",
528 	.id = SM8450_MASTER_A1NOC_SNOC,
529 	.channels = 1,
530 	.buswidth = 16,
531 	.num_links = 1,
532 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
533 };
534 
535 static struct qcom_icc_node qnm_aggre2_noc = {
536 	.name = "qnm_aggre2_noc",
537 	.id = SM8450_MASTER_A2NOC_SNOC,
538 	.channels = 1,
539 	.buswidth = 16,
540 	.num_links = 1,
541 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
542 };
543 
544 static struct qcom_icc_node qnm_lpass_noc = {
545 	.name = "qnm_lpass_noc",
546 	.id = SM8450_MASTER_LPASS_ANOC,
547 	.channels = 1,
548 	.buswidth = 16,
549 	.num_links = 1,
550 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
551 };
552 
553 static struct qcom_icc_node qnm_snoc_cfg = {
554 	.name = "qnm_snoc_cfg",
555 	.id = SM8450_MASTER_SNOC_CFG,
556 	.channels = 1,
557 	.buswidth = 4,
558 	.num_links = 1,
559 	.links = { SM8450_SLAVE_SERVICE_SNOC },
560 };
561 
562 static struct qcom_icc_node qxm_pimem = {
563 	.name = "qxm_pimem",
564 	.id = SM8450_MASTER_PIMEM,
565 	.channels = 1,
566 	.buswidth = 8,
567 	.num_links = 1,
568 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_GC },
569 };
570 
571 static struct qcom_icc_node xm_gic = {
572 	.name = "xm_gic",
573 	.id = SM8450_MASTER_GIC,
574 	.channels = 1,
575 	.buswidth = 8,
576 	.num_links = 1,
577 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_GC },
578 };
579 
580 static struct qcom_icc_node qnm_mnoc_hf_disp = {
581 	.name = "qnm_mnoc_hf_disp",
582 	.id = SM8450_MASTER_MNOC_HF_MEM_NOC_DISP,
583 	.channels = 2,
584 	.buswidth = 32,
585 	.num_links = 1,
586 	.links = { SM8450_SLAVE_LLCC_DISP },
587 };
588 
589 static struct qcom_icc_node qnm_mnoc_sf_disp = {
590 	.name = "qnm_mnoc_sf_disp",
591 	.id = SM8450_MASTER_MNOC_SF_MEM_NOC_DISP,
592 	.channels = 2,
593 	.buswidth = 32,
594 	.num_links = 1,
595 	.links = { SM8450_SLAVE_LLCC_DISP },
596 };
597 
598 static struct qcom_icc_node qnm_pcie_disp = {
599 	.name = "qnm_pcie_disp",
600 	.id = SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP,
601 	.channels = 1,
602 	.buswidth = 16,
603 	.num_links = 1,
604 	.links = { SM8450_SLAVE_LLCC_DISP },
605 };
606 
607 static struct qcom_icc_node llcc_mc_disp = {
608 	.name = "llcc_mc_disp",
609 	.id = SM8450_MASTER_LLCC_DISP,
610 	.channels = 4,
611 	.buswidth = 4,
612 	.num_links = 1,
613 	.links = { SM8450_SLAVE_EBI1_DISP },
614 };
615 
616 static struct qcom_icc_node qnm_mdp_disp = {
617 	.name = "qnm_mdp_disp",
618 	.id = SM8450_MASTER_MDP_DISP,
619 	.channels = 2,
620 	.buswidth = 32,
621 	.num_links = 1,
622 	.links = { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP },
623 };
624 
625 static struct qcom_icc_node qnm_rot_disp = {
626 	.name = "qnm_rot_disp",
627 	.id = SM8450_MASTER_ROTATOR_DISP,
628 	.channels = 1,
629 	.buswidth = 32,
630 	.num_links = 1,
631 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP },
632 };
633 
634 static struct qcom_icc_node qns_a1noc_snoc = {
635 	.name = "qns_a1noc_snoc",
636 	.id = SM8450_SLAVE_A1NOC_SNOC,
637 	.channels = 1,
638 	.buswidth = 16,
639 	.num_links = 1,
640 	.links = { SM8450_MASTER_A1NOC_SNOC },
641 };
642 
643 static struct qcom_icc_node srvc_aggre1_noc = {
644 	.name = "srvc_aggre1_noc",
645 	.id = SM8450_SLAVE_SERVICE_A1NOC,
646 	.channels = 1,
647 	.buswidth = 4,
648 	.num_links = 0,
649 };
650 
651 static struct qcom_icc_node qns_a2noc_snoc = {
652 	.name = "qns_a2noc_snoc",
653 	.id = SM8450_SLAVE_A2NOC_SNOC,
654 	.channels = 1,
655 	.buswidth = 16,
656 	.num_links = 1,
657 	.links = { SM8450_MASTER_A2NOC_SNOC },
658 };
659 
660 static struct qcom_icc_node srvc_aggre2_noc = {
661 	.name = "srvc_aggre2_noc",
662 	.id = SM8450_SLAVE_SERVICE_A2NOC,
663 	.channels = 1,
664 	.buswidth = 4,
665 	.num_links = 0,
666 };
667 
668 static struct qcom_icc_node qup0_core_slave = {
669 	.name = "qup0_core_slave",
670 	.id = SM8450_SLAVE_QUP_CORE_0,
671 	.channels = 1,
672 	.buswidth = 4,
673 	.num_links = 0,
674 };
675 
676 static struct qcom_icc_node qup1_core_slave = {
677 	.name = "qup1_core_slave",
678 	.id = SM8450_SLAVE_QUP_CORE_1,
679 	.channels = 1,
680 	.buswidth = 4,
681 	.num_links = 0,
682 };
683 
684 static struct qcom_icc_node qup2_core_slave = {
685 	.name = "qup2_core_slave",
686 	.id = SM8450_SLAVE_QUP_CORE_2,
687 	.channels = 1,
688 	.buswidth = 4,
689 	.num_links = 0,
690 };
691 
692 static struct qcom_icc_node qhs_ahb2phy0 = {
693 	.name = "qhs_ahb2phy0",
694 	.id = SM8450_SLAVE_AHB2PHY_SOUTH,
695 	.channels = 1,
696 	.buswidth = 4,
697 	.num_links = 0,
698 };
699 
700 static struct qcom_icc_node qhs_ahb2phy1 = {
701 	.name = "qhs_ahb2phy1",
702 	.id = SM8450_SLAVE_AHB2PHY_NORTH,
703 	.channels = 1,
704 	.buswidth = 4,
705 	.num_links = 0,
706 };
707 
708 static struct qcom_icc_node qhs_aoss = {
709 	.name = "qhs_aoss",
710 	.id = SM8450_SLAVE_AOSS,
711 	.channels = 1,
712 	.buswidth = 4,
713 	.num_links = 0,
714 };
715 
716 static struct qcom_icc_node qhs_camera_cfg = {
717 	.name = "qhs_camera_cfg",
718 	.id = SM8450_SLAVE_CAMERA_CFG,
719 	.channels = 1,
720 	.buswidth = 4,
721 	.num_links = 0,
722 };
723 
724 static struct qcom_icc_node qhs_clk_ctl = {
725 	.name = "qhs_clk_ctl",
726 	.id = SM8450_SLAVE_CLK_CTL,
727 	.channels = 1,
728 	.buswidth = 4,
729 	.num_links = 0,
730 };
731 
732 static struct qcom_icc_node qhs_compute_cfg = {
733 	.name = "qhs_compute_cfg",
734 	.id = SM8450_SLAVE_CDSP_CFG,
735 	.channels = 1,
736 	.buswidth = 4,
737 	.num_links = 1,
738 	.links = { MASTER_CDSP_NOC_CFG },
739 };
740 
741 static struct qcom_icc_node qhs_cpr_cx = {
742 	.name = "qhs_cpr_cx",
743 	.id = SM8450_SLAVE_RBCPR_CX_CFG,
744 	.channels = 1,
745 	.buswidth = 4,
746 	.num_links = 0,
747 };
748 
749 static struct qcom_icc_node qhs_cpr_mmcx = {
750 	.name = "qhs_cpr_mmcx",
751 	.id = SM8450_SLAVE_RBCPR_MMCX_CFG,
752 	.channels = 1,
753 	.buswidth = 4,
754 	.num_links = 0,
755 };
756 
757 static struct qcom_icc_node qhs_cpr_mxa = {
758 	.name = "qhs_cpr_mxa",
759 	.id = SM8450_SLAVE_RBCPR_MXA_CFG,
760 	.channels = 1,
761 	.buswidth = 4,
762 	.num_links = 0,
763 };
764 
765 static struct qcom_icc_node qhs_cpr_mxc = {
766 	.name = "qhs_cpr_mxc",
767 	.id = SM8450_SLAVE_RBCPR_MXC_CFG,
768 	.channels = 1,
769 	.buswidth = 4,
770 	.num_links = 0,
771 };
772 
773 static struct qcom_icc_node qhs_crypto0_cfg = {
774 	.name = "qhs_crypto0_cfg",
775 	.id = SM8450_SLAVE_CRYPTO_0_CFG,
776 	.channels = 1,
777 	.buswidth = 4,
778 	.num_links = 0,
779 };
780 
781 static struct qcom_icc_node qhs_cx_rdpm = {
782 	.name = "qhs_cx_rdpm",
783 	.id = SM8450_SLAVE_CX_RDPM,
784 	.channels = 1,
785 	.buswidth = 4,
786 	.num_links = 0,
787 };
788 
789 static struct qcom_icc_node qhs_display_cfg = {
790 	.name = "qhs_display_cfg",
791 	.id = SM8450_SLAVE_DISPLAY_CFG,
792 	.channels = 1,
793 	.buswidth = 4,
794 	.num_links = 0,
795 };
796 
797 static struct qcom_icc_node qhs_gpuss_cfg = {
798 	.name = "qhs_gpuss_cfg",
799 	.id = SM8450_SLAVE_GFX3D_CFG,
800 	.channels = 1,
801 	.buswidth = 8,
802 	.num_links = 0,
803 };
804 
805 static struct qcom_icc_node qhs_imem_cfg = {
806 	.name = "qhs_imem_cfg",
807 	.id = SM8450_SLAVE_IMEM_CFG,
808 	.channels = 1,
809 	.buswidth = 4,
810 	.num_links = 0,
811 };
812 
813 static struct qcom_icc_node qhs_ipa = {
814 	.name = "qhs_ipa",
815 	.id = SM8450_SLAVE_IPA_CFG,
816 	.channels = 1,
817 	.buswidth = 4,
818 	.num_links = 0,
819 };
820 
821 static struct qcom_icc_node qhs_ipc_router = {
822 	.name = "qhs_ipc_router",
823 	.id = SM8450_SLAVE_IPC_ROUTER_CFG,
824 	.channels = 1,
825 	.buswidth = 4,
826 	.num_links = 0,
827 };
828 
829 static struct qcom_icc_node qhs_lpass_cfg = {
830 	.name = "qhs_lpass_cfg",
831 	.id = SM8450_SLAVE_LPASS,
832 	.channels = 1,
833 	.buswidth = 4,
834 	.num_links = 1,
835 	.links = { MASTER_CNOC_LPASS_AG_NOC },
836 };
837 
838 static struct qcom_icc_node qhs_mss_cfg = {
839 	.name = "qhs_mss_cfg",
840 	.id = SM8450_SLAVE_CNOC_MSS,
841 	.channels = 1,
842 	.buswidth = 4,
843 	.num_links = 0,
844 };
845 
846 static struct qcom_icc_node qhs_mx_rdpm = {
847 	.name = "qhs_mx_rdpm",
848 	.id = SM8450_SLAVE_MX_RDPM,
849 	.channels = 1,
850 	.buswidth = 4,
851 	.num_links = 0,
852 };
853 
854 static struct qcom_icc_node qhs_pcie0_cfg = {
855 	.name = "qhs_pcie0_cfg",
856 	.id = SM8450_SLAVE_PCIE_0_CFG,
857 	.channels = 1,
858 	.buswidth = 4,
859 	.num_links = 0,
860 };
861 
862 static struct qcom_icc_node qhs_pcie1_cfg = {
863 	.name = "qhs_pcie1_cfg",
864 	.id = SM8450_SLAVE_PCIE_1_CFG,
865 	.channels = 1,
866 	.buswidth = 4,
867 	.num_links = 0,
868 };
869 
870 static struct qcom_icc_node qhs_pdm = {
871 	.name = "qhs_pdm",
872 	.id = SM8450_SLAVE_PDM,
873 	.channels = 1,
874 	.buswidth = 4,
875 	.num_links = 0,
876 };
877 
878 static struct qcom_icc_node qhs_pimem_cfg = {
879 	.name = "qhs_pimem_cfg",
880 	.id = SM8450_SLAVE_PIMEM_CFG,
881 	.channels = 1,
882 	.buswidth = 4,
883 	.num_links = 0,
884 };
885 
886 static struct qcom_icc_node qhs_prng = {
887 	.name = "qhs_prng",
888 	.id = SM8450_SLAVE_PRNG,
889 	.channels = 1,
890 	.buswidth = 4,
891 	.num_links = 0,
892 };
893 
894 static struct qcom_icc_node qhs_qdss_cfg = {
895 	.name = "qhs_qdss_cfg",
896 	.id = SM8450_SLAVE_QDSS_CFG,
897 	.channels = 1,
898 	.buswidth = 4,
899 	.num_links = 0,
900 };
901 
902 static struct qcom_icc_node qhs_qspi = {
903 	.name = "qhs_qspi",
904 	.id = SM8450_SLAVE_QSPI_0,
905 	.channels = 1,
906 	.buswidth = 4,
907 	.num_links = 0,
908 };
909 
910 static struct qcom_icc_node qhs_qup0 = {
911 	.name = "qhs_qup0",
912 	.id = SM8450_SLAVE_QUP_0,
913 	.channels = 1,
914 	.buswidth = 4,
915 	.num_links = 0,
916 };
917 
918 static struct qcom_icc_node qhs_qup1 = {
919 	.name = "qhs_qup1",
920 	.id = SM8450_SLAVE_QUP_1,
921 	.channels = 1,
922 	.buswidth = 4,
923 	.num_links = 0,
924 };
925 
926 static struct qcom_icc_node qhs_qup2 = {
927 	.name = "qhs_qup2",
928 	.id = SM8450_SLAVE_QUP_2,
929 	.channels = 1,
930 	.buswidth = 4,
931 	.num_links = 0,
932 };
933 
934 static struct qcom_icc_node qhs_sdc2 = {
935 	.name = "qhs_sdc2",
936 	.id = SM8450_SLAVE_SDCC_2,
937 	.channels = 1,
938 	.buswidth = 4,
939 	.num_links = 0,
940 };
941 
942 static struct qcom_icc_node qhs_sdc4 = {
943 	.name = "qhs_sdc4",
944 	.id = SM8450_SLAVE_SDCC_4,
945 	.channels = 1,
946 	.buswidth = 4,
947 	.num_links = 0,
948 };
949 
950 static struct qcom_icc_node qhs_spss_cfg = {
951 	.name = "qhs_spss_cfg",
952 	.id = SM8450_SLAVE_SPSS_CFG,
953 	.channels = 1,
954 	.buswidth = 4,
955 	.num_links = 0,
956 };
957 
958 static struct qcom_icc_node qhs_tcsr = {
959 	.name = "qhs_tcsr",
960 	.id = SM8450_SLAVE_TCSR,
961 	.channels = 1,
962 	.buswidth = 4,
963 	.num_links = 0,
964 };
965 
966 static struct qcom_icc_node qhs_tlmm = {
967 	.name = "qhs_tlmm",
968 	.id = SM8450_SLAVE_TLMM,
969 	.channels = 1,
970 	.buswidth = 4,
971 	.num_links = 0,
972 };
973 
974 static struct qcom_icc_node qhs_tme_cfg = {
975 	.name = "qhs_tme_cfg",
976 	.id = SM8450_SLAVE_TME_CFG,
977 	.channels = 1,
978 	.buswidth = 4,
979 	.num_links = 0,
980 };
981 
982 static struct qcom_icc_node qhs_ufs_mem_cfg = {
983 	.name = "qhs_ufs_mem_cfg",
984 	.id = SM8450_SLAVE_UFS_MEM_CFG,
985 	.channels = 1,
986 	.buswidth = 4,
987 	.num_links = 0,
988 };
989 
990 static struct qcom_icc_node qhs_usb3_0 = {
991 	.name = "qhs_usb3_0",
992 	.id = SM8450_SLAVE_USB3_0,
993 	.channels = 1,
994 	.buswidth = 4,
995 	.num_links = 0,
996 };
997 
998 static struct qcom_icc_node qhs_venus_cfg = {
999 	.name = "qhs_venus_cfg",
1000 	.id = SM8450_SLAVE_VENUS_CFG,
1001 	.channels = 1,
1002 	.buswidth = 4,
1003 	.num_links = 0,
1004 };
1005 
1006 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1007 	.name = "qhs_vsense_ctrl_cfg",
1008 	.id = SM8450_SLAVE_VSENSE_CTRL_CFG,
1009 	.channels = 1,
1010 	.buswidth = 4,
1011 	.num_links = 0,
1012 };
1013 
1014 static struct qcom_icc_node qns_a1_noc_cfg = {
1015 	.name = "qns_a1_noc_cfg",
1016 	.id = SM8450_SLAVE_A1NOC_CFG,
1017 	.channels = 1,
1018 	.buswidth = 4,
1019 	.num_links = 1,
1020 	.links = { SM8450_MASTER_A1NOC_CFG },
1021 };
1022 
1023 static struct qcom_icc_node qns_a2_noc_cfg = {
1024 	.name = "qns_a2_noc_cfg",
1025 	.id = SM8450_SLAVE_A2NOC_CFG,
1026 	.channels = 1,
1027 	.buswidth = 4,
1028 	.num_links = 1,
1029 	.links = { SM8450_MASTER_A2NOC_CFG },
1030 };
1031 
1032 static struct qcom_icc_node qns_ddrss_cfg = {
1033 	.name = "qns_ddrss_cfg",
1034 	.id = SM8450_SLAVE_DDRSS_CFG,
1035 	.channels = 1,
1036 	.buswidth = 4,
1037 	.num_links = 1,
1038 	//FIXME where is link
1039 };
1040 
1041 static struct qcom_icc_node qns_mnoc_cfg = {
1042 	.name = "qns_mnoc_cfg",
1043 	.id = SM8450_SLAVE_CNOC_MNOC_CFG,
1044 	.channels = 1,
1045 	.buswidth = 4,
1046 	.num_links = 1,
1047 	.links = { SM8450_MASTER_CNOC_MNOC_CFG },
1048 };
1049 
1050 static struct qcom_icc_node qns_pcie_anoc_cfg = {
1051 	.name = "qns_pcie_anoc_cfg",
1052 	.id = SM8450_SLAVE_PCIE_ANOC_CFG,
1053 	.channels = 1,
1054 	.buswidth = 4,
1055 	.num_links = 1,
1056 	.links = { SM8450_MASTER_PCIE_ANOC_CFG },
1057 };
1058 
1059 static struct qcom_icc_node qns_snoc_cfg = {
1060 	.name = "qns_snoc_cfg",
1061 	.id = SM8450_SLAVE_SNOC_CFG,
1062 	.channels = 1,
1063 	.buswidth = 4,
1064 	.num_links = 1,
1065 	.links = { SM8450_MASTER_SNOC_CFG },
1066 };
1067 
1068 static struct qcom_icc_node qxs_imem = {
1069 	.name = "qxs_imem",
1070 	.id = SM8450_SLAVE_IMEM,
1071 	.channels = 1,
1072 	.buswidth = 8,
1073 	.num_links = 0,
1074 };
1075 
1076 static struct qcom_icc_node qxs_pimem = {
1077 	.name = "qxs_pimem",
1078 	.id = SM8450_SLAVE_PIMEM,
1079 	.channels = 1,
1080 	.buswidth = 8,
1081 	.num_links = 0,
1082 };
1083 
1084 static struct qcom_icc_node srvc_cnoc = {
1085 	.name = "srvc_cnoc",
1086 	.id = SM8450_SLAVE_SERVICE_CNOC,
1087 	.channels = 1,
1088 	.buswidth = 4,
1089 	.num_links = 0,
1090 };
1091 
1092 static struct qcom_icc_node xs_pcie_0 = {
1093 	.name = "xs_pcie_0",
1094 	.id = SM8450_SLAVE_PCIE_0,
1095 	.channels = 1,
1096 	.buswidth = 8,
1097 	.num_links = 0,
1098 };
1099 
1100 static struct qcom_icc_node xs_pcie_1 = {
1101 	.name = "xs_pcie_1",
1102 	.id = SM8450_SLAVE_PCIE_1,
1103 	.channels = 1,
1104 	.buswidth = 8,
1105 	.num_links = 0,
1106 };
1107 
1108 static struct qcom_icc_node xs_qdss_stm = {
1109 	.name = "xs_qdss_stm",
1110 	.id = SM8450_SLAVE_QDSS_STM,
1111 	.channels = 1,
1112 	.buswidth = 4,
1113 	.num_links = 0,
1114 };
1115 
1116 static struct qcom_icc_node xs_sys_tcu_cfg = {
1117 	.name = "xs_sys_tcu_cfg",
1118 	.id = SM8450_SLAVE_TCU,
1119 	.channels = 1,
1120 	.buswidth = 8,
1121 	.num_links = 0,
1122 };
1123 
1124 static struct qcom_icc_node qns_gem_noc_cnoc = {
1125 	.name = "qns_gem_noc_cnoc",
1126 	.id = SM8450_SLAVE_GEM_NOC_CNOC,
1127 	.channels = 1,
1128 	.buswidth = 16,
1129 	.num_links = 1,
1130 	.links = { SM8450_MASTER_GEM_NOC_CNOC },
1131 };
1132 
1133 static struct qcom_icc_node qns_llcc = {
1134 	.name = "qns_llcc",
1135 	.id = SM8450_SLAVE_LLCC,
1136 	.channels = 4,
1137 	.buswidth = 16,
1138 	.num_links = 1,
1139 	.links = { SM8450_MASTER_LLCC },
1140 };
1141 
1142 static struct qcom_icc_node qns_pcie = {
1143 	.name = "qns_pcie",
1144 	.id = SM8450_SLAVE_MEM_NOC_PCIE_SNOC,
1145 	.channels = 1,
1146 	.buswidth = 8,
1147 	.num_links = 1,
1148 	.links = { SM8450_MASTER_GEM_NOC_PCIE_SNOC },
1149 };
1150 
1151 static struct qcom_icc_node qhs_lpass_core = {
1152 	.name = "qhs_lpass_core",
1153 	.id = SM8450_SLAVE_LPASS_CORE_CFG,
1154 	.channels = 1,
1155 	.buswidth = 4,
1156 	.num_links = 0,
1157 };
1158 
1159 static struct qcom_icc_node qhs_lpass_lpi = {
1160 	.name = "qhs_lpass_lpi",
1161 	.id = SM8450_SLAVE_LPASS_LPI_CFG,
1162 	.channels = 1,
1163 	.buswidth = 4,
1164 	.num_links = 0,
1165 };
1166 
1167 static struct qcom_icc_node qhs_lpass_mpu = {
1168 	.name = "qhs_lpass_mpu",
1169 	.id = SM8450_SLAVE_LPASS_MPU_CFG,
1170 	.channels = 1,
1171 	.buswidth = 4,
1172 	.num_links = 0,
1173 };
1174 
1175 static struct qcom_icc_node qhs_lpass_top = {
1176 	.name = "qhs_lpass_top",
1177 	.id = SM8450_SLAVE_LPASS_TOP_CFG,
1178 	.channels = 1,
1179 	.buswidth = 4,
1180 	.num_links = 0,
1181 };
1182 
1183 static struct qcom_icc_node qns_sysnoc = {
1184 	.name = "qns_sysnoc",
1185 	.id = SM8450_SLAVE_LPASS_SNOC,
1186 	.channels = 1,
1187 	.buswidth = 16,
1188 	.num_links = 1,
1189 	.links = { SM8450_MASTER_LPASS_ANOC },
1190 };
1191 
1192 static struct qcom_icc_node srvc_niu_aml_noc = {
1193 	.name = "srvc_niu_aml_noc",
1194 	.id = SM8450_SLAVE_SERVICES_LPASS_AML_NOC,
1195 	.channels = 1,
1196 	.buswidth = 4,
1197 	.num_links = 0,
1198 };
1199 
1200 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1201 	.name = "srvc_niu_lpass_agnoc",
1202 	.id = SM8450_SLAVE_SERVICE_LPASS_AG_NOC,
1203 	.channels = 1,
1204 	.buswidth = 4,
1205 	.num_links = 0,
1206 };
1207 
1208 static struct qcom_icc_node ebi = {
1209 	.name = "ebi",
1210 	.id = SM8450_SLAVE_EBI1,
1211 	.channels = 4,
1212 	.buswidth = 4,
1213 	.num_links = 0,
1214 };
1215 
1216 static struct qcom_icc_node qns_mem_noc_hf = {
1217 	.name = "qns_mem_noc_hf",
1218 	.id = SM8450_SLAVE_MNOC_HF_MEM_NOC,
1219 	.channels = 2,
1220 	.buswidth = 32,
1221 	.num_links = 1,
1222 	.links = { SM8450_MASTER_MNOC_HF_MEM_NOC },
1223 };
1224 
1225 static struct qcom_icc_node qns_mem_noc_sf = {
1226 	.name = "qns_mem_noc_sf",
1227 	.id = SM8450_SLAVE_MNOC_SF_MEM_NOC,
1228 	.channels = 2,
1229 	.buswidth = 32,
1230 	.num_links = 1,
1231 	.links = { SM8450_MASTER_MNOC_SF_MEM_NOC },
1232 };
1233 
1234 static struct qcom_icc_node srvc_mnoc = {
1235 	.name = "srvc_mnoc",
1236 	.id = SM8450_SLAVE_SERVICE_MNOC,
1237 	.channels = 1,
1238 	.buswidth = 4,
1239 	.num_links = 0,
1240 };
1241 
1242 static struct qcom_icc_node qns_nsp_gemnoc = {
1243 	.name = "qns_nsp_gemnoc",
1244 	.id = SM8450_SLAVE_CDSP_MEM_NOC,
1245 	.channels = 2,
1246 	.buswidth = 32,
1247 	.num_links = 1,
1248 	.links = { SM8450_MASTER_COMPUTE_NOC },
1249 };
1250 
1251 static struct qcom_icc_node service_nsp_noc = {
1252 	.name = "service_nsp_noc",
1253 	.id = SM8450_SLAVE_SERVICE_NSP_NOC,
1254 	.channels = 1,
1255 	.buswidth = 4,
1256 	.num_links = 0,
1257 };
1258 
1259 static struct qcom_icc_node qns_pcie_mem_noc = {
1260 	.name = "qns_pcie_mem_noc",
1261 	.id = SM8450_SLAVE_ANOC_PCIE_GEM_NOC,
1262 	.channels = 1,
1263 	.buswidth = 16,
1264 	.num_links = 1,
1265 	.links = { SM8450_MASTER_ANOC_PCIE_GEM_NOC },
1266 };
1267 
1268 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1269 	.name = "srvc_pcie_aggre_noc",
1270 	.id = SM8450_SLAVE_SERVICE_PCIE_ANOC,
1271 	.channels = 1,
1272 	.buswidth = 4,
1273 	.num_links = 0,
1274 };
1275 
1276 static struct qcom_icc_node qns_gemnoc_gc = {
1277 	.name = "qns_gemnoc_gc",
1278 	.id = SM8450_SLAVE_SNOC_GEM_NOC_GC,
1279 	.channels = 1,
1280 	.buswidth = 8,
1281 	.num_links = 1,
1282 	.links = { SM8450_MASTER_SNOC_GC_MEM_NOC },
1283 };
1284 
1285 static struct qcom_icc_node qns_gemnoc_sf = {
1286 	.name = "qns_gemnoc_sf",
1287 	.id = SM8450_SLAVE_SNOC_GEM_NOC_SF,
1288 	.channels = 1,
1289 	.buswidth = 16,
1290 	.num_links = 1,
1291 	.links = { SM8450_MASTER_SNOC_SF_MEM_NOC },
1292 };
1293 
1294 static struct qcom_icc_node srvc_snoc = {
1295 	.name = "srvc_snoc",
1296 	.id = SM8450_SLAVE_SERVICE_SNOC,
1297 	.channels = 1,
1298 	.buswidth = 4,
1299 	.num_links = 0,
1300 };
1301 
1302 static struct qcom_icc_node qns_llcc_disp = {
1303 	.name = "qns_llcc_disp",
1304 	.id = SM8450_SLAVE_LLCC_DISP,
1305 	.channels = 4,
1306 	.buswidth = 16,
1307 	.num_links = 1,
1308 	.links = { SM8450_MASTER_LLCC_DISP },
1309 };
1310 
1311 static struct qcom_icc_node ebi_disp = {
1312 	.name = "ebi_disp",
1313 	.id = SM8450_SLAVE_EBI1_DISP,
1314 	.channels = 4,
1315 	.buswidth = 4,
1316 	.num_links = 0,
1317 };
1318 
1319 static struct qcom_icc_node qns_mem_noc_hf_disp = {
1320 	.name = "qns_mem_noc_hf_disp",
1321 	.id = SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP,
1322 	.channels = 2,
1323 	.buswidth = 32,
1324 	.num_links = 1,
1325 	.links = { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP },
1326 };
1327 
1328 static struct qcom_icc_node qns_mem_noc_sf_disp = {
1329 	.name = "qns_mem_noc_sf_disp",
1330 	.id = SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP,
1331 	.channels = 2,
1332 	.buswidth = 32,
1333 	.num_links = 1,
1334 	.links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP },
1335 };
1336 
1337 static struct qcom_icc_bcm bcm_acv = {
1338 	.name = "ACV",
1339 	.num_nodes = 1,
1340 	.nodes = { &ebi },
1341 };
1342 
1343 static struct qcom_icc_bcm bcm_ce0 = {
1344 	.name = "CE0",
1345 	.num_nodes = 1,
1346 	.nodes = { &qxm_crypto },
1347 };
1348 
1349 static struct qcom_icc_bcm bcm_cn0 = {
1350 	.name = "CN0",
1351 	.keepalive = true,
1352 	.num_nodes = 55,
1353 	.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1354 		   &qhs_ahb2phy0, &qhs_ahb2phy1,
1355 		   &qhs_aoss, &qhs_camera_cfg,
1356 		   &qhs_clk_ctl, &qhs_compute_cfg,
1357 		   &qhs_cpr_cx, &qhs_cpr_mmcx,
1358 		   &qhs_cpr_mxa, &qhs_cpr_mxc,
1359 		   &qhs_crypto0_cfg, &qhs_cx_rdpm,
1360 		   &qhs_display_cfg, &qhs_gpuss_cfg,
1361 		   &qhs_imem_cfg, &qhs_ipa,
1362 		   &qhs_ipc_router, &qhs_lpass_cfg,
1363 		   &qhs_mss_cfg, &qhs_mx_rdpm,
1364 		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1365 		   &qhs_pdm, &qhs_pimem_cfg,
1366 		   &qhs_prng, &qhs_qdss_cfg,
1367 		   &qhs_qspi, &qhs_qup0,
1368 		   &qhs_qup1, &qhs_qup2,
1369 		   &qhs_sdc2, &qhs_sdc4,
1370 		   &qhs_spss_cfg, &qhs_tcsr,
1371 		   &qhs_tlmm, &qhs_tme_cfg,
1372 		   &qhs_ufs_mem_cfg, &qhs_usb3_0,
1373 		   &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1374 		   &qns_a1_noc_cfg, &qns_a2_noc_cfg,
1375 		   &qns_ddrss_cfg, &qns_mnoc_cfg,
1376 		   &qns_pcie_anoc_cfg, &qns_snoc_cfg,
1377 		   &qxs_imem, &qxs_pimem,
1378 		   &srvc_cnoc, &xs_pcie_0,
1379 		   &xs_pcie_1, &xs_qdss_stm,
1380 		   &xs_sys_tcu_cfg },
1381 };
1382 
1383 static struct qcom_icc_bcm bcm_co0 = {
1384 	.name = "CO0",
1385 	.num_nodes = 2,
1386 	.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1387 };
1388 
1389 static struct qcom_icc_bcm bcm_mc0 = {
1390 	.name = "MC0",
1391 	.keepalive = true,
1392 	.num_nodes = 1,
1393 	.nodes = { &ebi },
1394 };
1395 
1396 static struct qcom_icc_bcm bcm_mm0 = {
1397 	.name = "MM0",
1398 	.keepalive = true,
1399 	.num_nodes = 1,
1400 	.nodes = { &qns_mem_noc_hf },
1401 };
1402 
1403 static struct qcom_icc_bcm bcm_mm1 = {
1404 	.name = "MM1",
1405 	.num_nodes = 12,
1406 	.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1407 		   &qnm_camnoc_sf, &qnm_mdp,
1408 		   &qnm_mnoc_cfg, &qnm_rot,
1409 		   &qnm_vapss_hcp, &qnm_video,
1410 		   &qnm_video_cv_cpu, &qnm_video_cvp,
1411 		   &qnm_video_v_cpu, &qns_mem_noc_sf },
1412 };
1413 
1414 static struct qcom_icc_bcm bcm_qup0 = {
1415 	.name = "QUP0",
1416 	.keepalive = true,
1417 	.vote_scale = 1,
1418 	.num_nodes = 1,
1419 	.nodes = { &qup0_core_slave },
1420 };
1421 
1422 static struct qcom_icc_bcm bcm_qup1 = {
1423 	.name = "QUP1",
1424 	.keepalive = true,
1425 	.vote_scale = 1,
1426 	.num_nodes = 1,
1427 	.nodes = { &qup1_core_slave },
1428 };
1429 
1430 static struct qcom_icc_bcm bcm_qup2 = {
1431 	.name = "QUP2",
1432 	.keepalive = true,
1433 	.vote_scale = 1,
1434 	.num_nodes = 1,
1435 	.nodes = { &qup2_core_slave },
1436 };
1437 
1438 static struct qcom_icc_bcm bcm_sh0 = {
1439 	.name = "SH0",
1440 	.keepalive = true,
1441 	.num_nodes = 1,
1442 	.nodes = { &qns_llcc },
1443 };
1444 
1445 static struct qcom_icc_bcm bcm_sh1 = {
1446 	.name = "SH1",
1447 	.num_nodes = 7,
1448 	.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1449 		   &qnm_nsp_gemnoc, &qnm_pcie,
1450 		   &qnm_snoc_gc, &qns_gem_noc_cnoc,
1451 		   &qns_pcie },
1452 };
1453 
1454 static struct qcom_icc_bcm bcm_sn0 = {
1455 	.name = "SN0",
1456 	.keepalive = true,
1457 	.num_nodes = 1,
1458 	.nodes = { &qns_gemnoc_sf },
1459 };
1460 
1461 static struct qcom_icc_bcm bcm_sn1 = {
1462 	.name = "SN1",
1463 	.num_nodes = 4,
1464 	.nodes = { &qhm_gic, &qxm_pimem,
1465 		   &xm_gic, &qns_gemnoc_gc },
1466 };
1467 
1468 static struct qcom_icc_bcm bcm_sn2 = {
1469 	.name = "SN2",
1470 	.num_nodes = 1,
1471 	.nodes = { &qnm_aggre1_noc },
1472 };
1473 
1474 static struct qcom_icc_bcm bcm_sn3 = {
1475 	.name = "SN3",
1476 	.num_nodes = 1,
1477 	.nodes = { &qnm_aggre2_noc },
1478 };
1479 
1480 static struct qcom_icc_bcm bcm_sn4 = {
1481 	.name = "SN4",
1482 	.num_nodes = 1,
1483 	.nodes = { &qnm_lpass_noc },
1484 };
1485 
1486 static struct qcom_icc_bcm bcm_sn7 = {
1487 	.name = "SN7",
1488 	.num_nodes = 1,
1489 	.nodes = { &qns_pcie_mem_noc },
1490 };
1491 
1492 static struct qcom_icc_bcm bcm_acv_disp = {
1493 	.name = "ACV",
1494 	.num_nodes = 1,
1495 	.nodes = { &ebi_disp },
1496 };
1497 
1498 static struct qcom_icc_bcm bcm_mc0_disp = {
1499 	.name = "MC0",
1500 	.num_nodes = 1,
1501 	.nodes = { &ebi_disp },
1502 };
1503 
1504 static struct qcom_icc_bcm bcm_mm0_disp = {
1505 	.name = "MM0",
1506 	.num_nodes = 1,
1507 	.nodes = { &qns_mem_noc_hf_disp },
1508 };
1509 
1510 static struct qcom_icc_bcm bcm_mm1_disp = {
1511 	.name = "MM1",
1512 	.num_nodes = 3,
1513 	.nodes = { &qnm_mdp_disp, &qnm_rot_disp,
1514 		   &qns_mem_noc_sf_disp },
1515 };
1516 
1517 static struct qcom_icc_bcm bcm_sh0_disp = {
1518 	.name = "SH0",
1519 	.num_nodes = 1,
1520 	.nodes = { &qns_llcc_disp },
1521 };
1522 
1523 static struct qcom_icc_bcm bcm_sh1_disp = {
1524 	.name = "SH1",
1525 	.num_nodes = 1,
1526 	.nodes = { &qnm_pcie_disp },
1527 };
1528 
1529 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1530 };
1531 
1532 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1533 	[MASTER_QSPI_0] = &qhm_qspi,
1534 	[MASTER_QUP_1] = &qhm_qup1,
1535 	[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1536 	[MASTER_SDCC_4] = &xm_sdc4,
1537 	[MASTER_UFS_MEM] = &xm_ufs_mem,
1538 	[MASTER_USB3_0] = &xm_usb3_0,
1539 	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1540 	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1541 };
1542 
1543 static const struct qcom_icc_desc sm8450_aggre1_noc = {
1544 	.nodes = aggre1_noc_nodes,
1545 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1546 	.bcms = aggre1_noc_bcms,
1547 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1548 };
1549 
1550 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1551 	&bcm_ce0,
1552 };
1553 
1554 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1555 	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1556 	[MASTER_QUP_0] = &qhm_qup0,
1557 	[MASTER_QUP_2] = &qhm_qup2,
1558 	[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1559 	[MASTER_CRYPTO] = &qxm_crypto,
1560 	[MASTER_IPA] = &qxm_ipa,
1561 	[MASTER_SENSORS_PROC] = &qxm_sensorss_q6,
1562 	[MASTER_SP] = &qxm_sp,
1563 	[MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1564 	[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1565 	[MASTER_SDCC_2] = &xm_sdc2,
1566 	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1567 	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1568 };
1569 
1570 static const struct qcom_icc_desc sm8450_aggre2_noc = {
1571 	.nodes = aggre2_noc_nodes,
1572 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1573 	.bcms = aggre2_noc_bcms,
1574 	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1575 };
1576 
1577 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1578 	&bcm_qup0,
1579 	&bcm_qup1,
1580 	&bcm_qup2,
1581 };
1582 
1583 static struct qcom_icc_node * const clk_virt_nodes[] = {
1584 	[MASTER_QUP_CORE_0] = &qup0_core_master,
1585 	[MASTER_QUP_CORE_1] = &qup1_core_master,
1586 	[MASTER_QUP_CORE_2] = &qup2_core_master,
1587 	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1588 	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1589 	[SLAVE_QUP_CORE_2] = &qup2_core_slave,
1590 };
1591 
1592 static const struct qcom_icc_desc sm8450_clk_virt = {
1593 	.nodes = clk_virt_nodes,
1594 	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1595 	.bcms = clk_virt_bcms,
1596 	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1597 };
1598 
1599 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1600 	&bcm_cn0,
1601 };
1602 
1603 static struct qcom_icc_node * const config_noc_nodes[] = {
1604 	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1605 	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1606 	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1607 	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1608 	[SLAVE_AOSS] = &qhs_aoss,
1609 	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1610 	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1611 	[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1612 	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1613 	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1614 	[SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1615 	[SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1616 	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1617 	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1618 	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1619 	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1620 	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1621 	[SLAVE_IPA_CFG] = &qhs_ipa,
1622 	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1623 	[SLAVE_LPASS] = &qhs_lpass_cfg,
1624 	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1625 	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1626 	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1627 	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1628 	[SLAVE_PDM] = &qhs_pdm,
1629 	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1630 	[SLAVE_PRNG] = &qhs_prng,
1631 	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1632 	[SLAVE_QSPI_0] = &qhs_qspi,
1633 	[SLAVE_QUP_0] = &qhs_qup0,
1634 	[SLAVE_QUP_1] = &qhs_qup1,
1635 	[SLAVE_QUP_2] = &qhs_qup2,
1636 	[SLAVE_SDCC_2] = &qhs_sdc2,
1637 	[SLAVE_SDCC_4] = &qhs_sdc4,
1638 	[SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1639 	[SLAVE_TCSR] = &qhs_tcsr,
1640 	[SLAVE_TLMM] = &qhs_tlmm,
1641 	[SLAVE_TME_CFG] = &qhs_tme_cfg,
1642 	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1643 	[SLAVE_USB3_0] = &qhs_usb3_0,
1644 	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1645 	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1646 	[SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1647 	[SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1648 	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1649 	[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1650 	[SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
1651 	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1652 	[SLAVE_IMEM] = &qxs_imem,
1653 	[SLAVE_PIMEM] = &qxs_pimem,
1654 	[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1655 	[SLAVE_PCIE_0] = &xs_pcie_0,
1656 	[SLAVE_PCIE_1] = &xs_pcie_1,
1657 	[SLAVE_QDSS_STM] = &xs_qdss_stm,
1658 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
1659 };
1660 
1661 static const struct qcom_icc_desc sm8450_config_noc = {
1662 	.nodes = config_noc_nodes,
1663 	.num_nodes = ARRAY_SIZE(config_noc_nodes),
1664 	.bcms = config_noc_bcms,
1665 	.num_bcms = ARRAY_SIZE(config_noc_bcms),
1666 };
1667 
1668 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1669 	&bcm_sh0,
1670 	&bcm_sh1,
1671 	&bcm_sh0_disp,
1672 	&bcm_sh1_disp,
1673 };
1674 
1675 static struct qcom_icc_node * const gem_noc_nodes[] = {
1676 	[MASTER_GPU_TCU] = &alm_gpu_tcu,
1677 	[MASTER_SYS_TCU] = &alm_sys_tcu,
1678 	[MASTER_APPSS_PROC] = &chm_apps,
1679 	[MASTER_GFX3D] = &qnm_gpu,
1680 	[MASTER_MSS_PROC] = &qnm_mdsp,
1681 	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1682 	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1683 	[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1684 	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1685 	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1686 	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1687 	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1688 	[SLAVE_LLCC] = &qns_llcc,
1689 	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1690 	[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1691 	[MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
1692 	[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1693 	[SLAVE_LLCC_DISP] = &qns_llcc_disp,
1694 };
1695 
1696 static const struct qcom_icc_desc sm8450_gem_noc = {
1697 	.nodes = gem_noc_nodes,
1698 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1699 	.bcms = gem_noc_bcms,
1700 	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1701 };
1702 
1703 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1704 };
1705 
1706 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1707 	[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1708 	[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
1709 	[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1710 	[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1711 	[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1712 	[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1713 	[SLAVE_LPASS_SNOC] = &qns_sysnoc,
1714 	[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1715 	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1716 };
1717 
1718 static const struct qcom_icc_desc sm8450_lpass_ag_noc = {
1719 	.nodes = lpass_ag_noc_nodes,
1720 	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1721 	.bcms = lpass_ag_noc_bcms,
1722 	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1723 };
1724 
1725 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1726 	&bcm_acv,
1727 	&bcm_mc0,
1728 	&bcm_acv_disp,
1729 	&bcm_mc0_disp,
1730 };
1731 
1732 static struct qcom_icc_node * const mc_virt_nodes[] = {
1733 	[MASTER_LLCC] = &llcc_mc,
1734 	[SLAVE_EBI1] = &ebi,
1735 	[MASTER_LLCC_DISP] = &llcc_mc_disp,
1736 	[SLAVE_EBI1_DISP] = &ebi_disp,
1737 };
1738 
1739 static const struct qcom_icc_desc sm8450_mc_virt = {
1740 	.nodes = mc_virt_nodes,
1741 	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1742 	.bcms = mc_virt_bcms,
1743 	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1744 };
1745 
1746 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1747 	&bcm_mm0,
1748 	&bcm_mm1,
1749 	&bcm_mm0_disp,
1750 	&bcm_mm1_disp,
1751 };
1752 
1753 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1754 	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1755 	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1756 	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1757 	[MASTER_MDP] = &qnm_mdp,
1758 	[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1759 	[MASTER_ROTATOR] = &qnm_rot,
1760 	[MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1761 	[MASTER_VIDEO] = &qnm_video,
1762 	[MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1763 	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
1764 	[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1765 	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1766 	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1767 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1768 	[MASTER_MDP_DISP] = &qnm_mdp_disp,
1769 	[MASTER_ROTATOR_DISP] = &qnm_rot_disp,
1770 	[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1771 	[SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
1772 };
1773 
1774 static const struct qcom_icc_desc sm8450_mmss_noc = {
1775 	.nodes = mmss_noc_nodes,
1776 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1777 	.bcms = mmss_noc_bcms,
1778 	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1779 };
1780 
1781 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1782 	&bcm_co0,
1783 };
1784 
1785 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1786 	[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1787 	[MASTER_CDSP_PROC] = &qxm_nsp,
1788 	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1789 	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1790 };
1791 
1792 static const struct qcom_icc_desc sm8450_nsp_noc = {
1793 	.nodes = nsp_noc_nodes,
1794 	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1795 	.bcms = nsp_noc_bcms,
1796 	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1797 };
1798 
1799 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1800 	&bcm_sn7,
1801 };
1802 
1803 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1804 	[MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg,
1805 	[MASTER_PCIE_0] = &xm_pcie3_0,
1806 	[MASTER_PCIE_1] = &xm_pcie3_1,
1807 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1808 	[SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1809 };
1810 
1811 static const struct qcom_icc_desc sm8450_pcie_anoc = {
1812 	.nodes = pcie_anoc_nodes,
1813 	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1814 	.bcms = pcie_anoc_bcms,
1815 	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1816 };
1817 
1818 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1819 	&bcm_sn0,
1820 	&bcm_sn1,
1821 	&bcm_sn2,
1822 	&bcm_sn3,
1823 	&bcm_sn4,
1824 };
1825 
1826 static struct qcom_icc_node * const system_noc_nodes[] = {
1827 	[MASTER_GIC_AHB] = &qhm_gic,
1828 	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1829 	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1830 	[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
1831 	[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1832 	[MASTER_PIMEM] = &qxm_pimem,
1833 	[MASTER_GIC] = &xm_gic,
1834 	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1835 	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1836 	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1837 };
1838 
1839 static const struct qcom_icc_desc sm8450_system_noc = {
1840 	.nodes = system_noc_nodes,
1841 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
1842 	.bcms = system_noc_bcms,
1843 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
1844 };
1845 
1846 static int qnoc_probe(struct platform_device *pdev)
1847 {
1848 	const struct qcom_icc_desc *desc;
1849 	struct icc_onecell_data *data;
1850 	struct icc_provider *provider;
1851 	struct qcom_icc_node * const *qnodes;
1852 	struct qcom_icc_provider *qp;
1853 	struct icc_node *node;
1854 	size_t num_nodes, i;
1855 	int ret;
1856 
1857 	desc = device_get_match_data(&pdev->dev);
1858 	if (!desc)
1859 		return -EINVAL;
1860 
1861 	qnodes = desc->nodes;
1862 	num_nodes = desc->num_nodes;
1863 
1864 	qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
1865 	if (!qp)
1866 		return -ENOMEM;
1867 
1868 	data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
1869 	if (!data)
1870 		return -ENOMEM;
1871 
1872 	provider = &qp->provider;
1873 	provider->dev = &pdev->dev;
1874 	provider->set = qcom_icc_set;
1875 	provider->pre_aggregate = qcom_icc_pre_aggregate;
1876 	provider->aggregate = qcom_icc_aggregate;
1877 	provider->xlate_extended = qcom_icc_xlate_extended;
1878 	INIT_LIST_HEAD(&provider->nodes);
1879 	provider->data = data;
1880 
1881 	qp->dev = &pdev->dev;
1882 	qp->bcms = desc->bcms;
1883 	qp->num_bcms = desc->num_bcms;
1884 
1885 	qp->voter = of_bcm_voter_get(qp->dev, NULL);
1886 	if (IS_ERR(qp->voter))
1887 		return PTR_ERR(qp->voter);
1888 
1889 	ret = icc_provider_add(provider);
1890 	if (ret) {
1891 		dev_err(&pdev->dev, "error adding interconnect provider\n");
1892 		return ret;
1893 	}
1894 
1895 	for (i = 0; i < qp->num_bcms; i++)
1896 		qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
1897 
1898 	for (i = 0; i < num_nodes; i++) {
1899 		size_t j;
1900 
1901 		if (!qnodes[i])
1902 			continue;
1903 
1904 		node = icc_node_create(qnodes[i]->id);
1905 		if (IS_ERR(node)) {
1906 			ret = PTR_ERR(node);
1907 			goto err;
1908 		}
1909 
1910 		node->name = qnodes[i]->name;
1911 		node->data = qnodes[i];
1912 		icc_node_add(node, provider);
1913 
1914 		for (j = 0; j < qnodes[i]->num_links; j++)
1915 			icc_link_create(node, qnodes[i]->links[j]);
1916 
1917 		data->nodes[i] = node;
1918 	}
1919 	data->num_nodes = num_nodes;
1920 
1921 	platform_set_drvdata(pdev, qp);
1922 
1923 	return 0;
1924 err:
1925 	icc_nodes_remove(provider);
1926 	icc_provider_del(provider);
1927 	return ret;
1928 }
1929 
1930 static int qnoc_remove(struct platform_device *pdev)
1931 {
1932 	struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
1933 
1934 	icc_nodes_remove(&qp->provider);
1935 	return icc_provider_del(&qp->provider);
1936 }
1937 
1938 static const struct of_device_id qnoc_of_match[] = {
1939 	{ .compatible = "qcom,sm8450-aggre1-noc",
1940 	  .data = &sm8450_aggre1_noc},
1941 	{ .compatible = "qcom,sm8450-aggre2-noc",
1942 	  .data = &sm8450_aggre2_noc},
1943 	{ .compatible = "qcom,sm8450-clk-virt",
1944 	  .data = &sm8450_clk_virt},
1945 	{ .compatible = "qcom,sm8450-config-noc",
1946 	  .data = &sm8450_config_noc},
1947 	{ .compatible = "qcom,sm8450-gem-noc",
1948 	  .data = &sm8450_gem_noc},
1949 	{ .compatible = "qcom,sm8450-lpass-ag-noc",
1950 	  .data = &sm8450_lpass_ag_noc},
1951 	{ .compatible = "qcom,sm8450-mc-virt",
1952 	  .data = &sm8450_mc_virt},
1953 	{ .compatible = "qcom,sm8450-mmss-noc",
1954 	  .data = &sm8450_mmss_noc},
1955 	{ .compatible = "qcom,sm8450-nsp-noc",
1956 	  .data = &sm8450_nsp_noc},
1957 	{ .compatible = "qcom,sm8450-pcie-anoc",
1958 	  .data = &sm8450_pcie_anoc},
1959 	{ .compatible = "qcom,sm8450-system-noc",
1960 	  .data = &sm8450_system_noc},
1961 	{ }
1962 };
1963 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1964 
1965 static struct platform_driver qnoc_driver = {
1966 	.probe = qnoc_probe,
1967 	.remove = qnoc_remove,
1968 	.driver = {
1969 		.name = "qnoc-sm8450",
1970 		.of_match_table = qnoc_of_match,
1971 	},
1972 };
1973 
1974 static int __init qnoc_driver_init(void)
1975 {
1976 	return platform_driver_register(&qnoc_driver);
1977 }
1978 core_initcall(qnoc_driver_init);
1979 
1980 static void __exit qnoc_driver_exit(void)
1981 {
1982 	platform_driver_unregister(&qnoc_driver);
1983 }
1984 module_exit(qnoc_driver_exit);
1985 
1986 MODULE_DESCRIPTION("sm8450 NoC driver");
1987 MODULE_LICENSE("GPL v2");
1988