1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021, Linaro Limited
5  */
6 
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <dt-bindings/interconnect/qcom,sm8450.h>
13 
14 #include "bcm-voter.h"
15 #include "icc-common.h"
16 #include "icc-rpmh.h"
17 #include "sm8450.h"
18 
19 static struct qcom_icc_node qhm_qspi = {
20 	.name = "qhm_qspi",
21 	.id = SM8450_MASTER_QSPI_0,
22 	.channels = 1,
23 	.buswidth = 4,
24 	.num_links = 1,
25 	.links = { SM8450_SLAVE_A1NOC_SNOC },
26 };
27 
28 static struct qcom_icc_node qhm_qup1 = {
29 	.name = "qhm_qup1",
30 	.id = SM8450_MASTER_QUP_1,
31 	.channels = 1,
32 	.buswidth = 4,
33 	.num_links = 1,
34 	.links = { SM8450_SLAVE_A1NOC_SNOC },
35 };
36 
37 static struct qcom_icc_node qnm_a1noc_cfg = {
38 	.name = "qnm_a1noc_cfg",
39 	.id = SM8450_MASTER_A1NOC_CFG,
40 	.channels = 1,
41 	.buswidth = 4,
42 	.num_links = 1,
43 	.links = { SM8450_SLAVE_SERVICE_A1NOC },
44 };
45 
46 static struct qcom_icc_node xm_sdc4 = {
47 	.name = "xm_sdc4",
48 	.id = SM8450_MASTER_SDCC_4,
49 	.channels = 1,
50 	.buswidth = 8,
51 	.num_links = 1,
52 	.links = { SM8450_SLAVE_A1NOC_SNOC },
53 };
54 
55 static struct qcom_icc_node xm_ufs_mem = {
56 	.name = "xm_ufs_mem",
57 	.id = SM8450_MASTER_UFS_MEM,
58 	.channels = 1,
59 	.buswidth = 8,
60 	.num_links = 1,
61 	.links = { SM8450_SLAVE_A1NOC_SNOC },
62 };
63 
64 static struct qcom_icc_node xm_usb3_0 = {
65 	.name = "xm_usb3_0",
66 	.id = SM8450_MASTER_USB3_0,
67 	.channels = 1,
68 	.buswidth = 8,
69 	.num_links = 1,
70 	.links = { SM8450_SLAVE_A1NOC_SNOC },
71 };
72 
73 static struct qcom_icc_node qhm_qdss_bam = {
74 	.name = "qhm_qdss_bam",
75 	.id = SM8450_MASTER_QDSS_BAM,
76 	.channels = 1,
77 	.buswidth = 4,
78 	.num_links = 1,
79 	.links = { SM8450_SLAVE_A2NOC_SNOC },
80 };
81 
82 static struct qcom_icc_node qhm_qup0 = {
83 	.name = "qhm_qup0",
84 	.id = SM8450_MASTER_QUP_0,
85 	.channels = 1,
86 	.buswidth = 4,
87 	.num_links = 1,
88 	.links = { SM8450_SLAVE_A2NOC_SNOC },
89 };
90 
91 static struct qcom_icc_node qhm_qup2 = {
92 	.name = "qhm_qup2",
93 	.id = SM8450_MASTER_QUP_2,
94 	.channels = 1,
95 	.buswidth = 4,
96 	.num_links = 1,
97 	.links = { SM8450_SLAVE_A2NOC_SNOC },
98 };
99 
100 static struct qcom_icc_node qnm_a2noc_cfg = {
101 	.name = "qnm_a2noc_cfg",
102 	.id = SM8450_MASTER_A2NOC_CFG,
103 	.channels = 1,
104 	.buswidth = 4,
105 	.num_links = 1,
106 	.links = { SM8450_SLAVE_SERVICE_A2NOC },
107 };
108 
109 static struct qcom_icc_node qxm_crypto = {
110 	.name = "qxm_crypto",
111 	.id = SM8450_MASTER_CRYPTO,
112 	.channels = 1,
113 	.buswidth = 8,
114 	.num_links = 1,
115 	.links = { SM8450_SLAVE_A2NOC_SNOC },
116 };
117 
118 static struct qcom_icc_node qxm_ipa = {
119 	.name = "qxm_ipa",
120 	.id = SM8450_MASTER_IPA,
121 	.channels = 1,
122 	.buswidth = 8,
123 	.num_links = 1,
124 	.links = { SM8450_SLAVE_A2NOC_SNOC },
125 };
126 
127 static struct qcom_icc_node qxm_sensorss_q6 = {
128 	.name = "qxm_sensorss_q6",
129 	.id = SM8450_MASTER_SENSORS_PROC,
130 	.channels = 1,
131 	.buswidth = 8,
132 	.num_links = 1,
133 	.links = { SM8450_SLAVE_A2NOC_SNOC },
134 };
135 
136 static struct qcom_icc_node qxm_sp = {
137 	.name = "qxm_sp",
138 	.id = SM8450_MASTER_SP,
139 	.channels = 1,
140 	.buswidth = 8,
141 	.num_links = 1,
142 	.links = { SM8450_SLAVE_A2NOC_SNOC },
143 };
144 
145 static struct qcom_icc_node xm_qdss_etr_0 = {
146 	.name = "xm_qdss_etr_0",
147 	.id = SM8450_MASTER_QDSS_ETR,
148 	.channels = 1,
149 	.buswidth = 8,
150 	.num_links = 1,
151 	.links = { SM8450_SLAVE_A2NOC_SNOC },
152 };
153 
154 static struct qcom_icc_node xm_qdss_etr_1 = {
155 	.name = "xm_qdss_etr_1",
156 	.id = SM8450_MASTER_QDSS_ETR_1,
157 	.channels = 1,
158 	.buswidth = 8,
159 	.num_links = 1,
160 	.links = { SM8450_SLAVE_A2NOC_SNOC },
161 };
162 
163 static struct qcom_icc_node xm_sdc2 = {
164 	.name = "xm_sdc2",
165 	.id = SM8450_MASTER_SDCC_2,
166 	.channels = 1,
167 	.buswidth = 8,
168 	.num_links = 1,
169 	.links = { SM8450_SLAVE_A2NOC_SNOC },
170 };
171 
172 static struct qcom_icc_node qup0_core_master = {
173 	.name = "qup0_core_master",
174 	.id = SM8450_MASTER_QUP_CORE_0,
175 	.channels = 1,
176 	.buswidth = 4,
177 	.num_links = 1,
178 	.links = { SM8450_SLAVE_QUP_CORE_0 },
179 };
180 
181 static struct qcom_icc_node qup1_core_master = {
182 	.name = "qup1_core_master",
183 	.id = SM8450_MASTER_QUP_CORE_1,
184 	.channels = 1,
185 	.buswidth = 4,
186 	.num_links = 1,
187 	.links = { SM8450_SLAVE_QUP_CORE_1 },
188 };
189 
190 static struct qcom_icc_node qup2_core_master = {
191 	.name = "qup2_core_master",
192 	.id = SM8450_MASTER_QUP_CORE_2,
193 	.channels = 1,
194 	.buswidth = 4,
195 	.num_links = 1,
196 	.links = { SM8450_SLAVE_QUP_CORE_2 },
197 };
198 
199 static struct qcom_icc_node qnm_gemnoc_cnoc = {
200 	.name = "qnm_gemnoc_cnoc",
201 	.id = SM8450_MASTER_GEM_NOC_CNOC,
202 	.channels = 1,
203 	.buswidth = 16,
204 	.num_links = 51,
205 	.links = { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH,
206 		   SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG,
207 		   SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG,
208 		   SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG,
209 		   SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG,
210 		   SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM,
211 		   SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG,
212 		   SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG,
213 		   SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS,
214 		   SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM,
215 		   SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG,
216 		   SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG,
217 		   SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG,
218 		   SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0,
219 		   SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2,
220 		   SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4,
221 		   SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR,
222 		   SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG,
223 		   SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0,
224 		   SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG,
225 		   SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG,
226 		   SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG,
227 		   SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG,
228 		   SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM,
229 		   SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM,
230 		   SM8450_SLAVE_TCU },
231 };
232 
233 static struct qcom_icc_node qnm_gemnoc_pcie = {
234 	.name = "qnm_gemnoc_pcie",
235 	.id = SM8450_MASTER_GEM_NOC_PCIE_SNOC,
236 	.channels = 1,
237 	.buswidth = 8,
238 	.num_links = 2,
239 	.links = { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 },
240 };
241 
242 static struct qcom_icc_node alm_gpu_tcu = {
243 	.name = "alm_gpu_tcu",
244 	.id = SM8450_MASTER_GPU_TCU,
245 	.channels = 1,
246 	.buswidth = 8,
247 	.num_links = 2,
248 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
249 };
250 
251 static struct qcom_icc_node alm_sys_tcu = {
252 	.name = "alm_sys_tcu",
253 	.id = SM8450_MASTER_SYS_TCU,
254 	.channels = 1,
255 	.buswidth = 8,
256 	.num_links = 2,
257 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
258 };
259 
260 static struct qcom_icc_node chm_apps = {
261 	.name = "chm_apps",
262 	.id = SM8450_MASTER_APPSS_PROC,
263 	.channels = 3,
264 	.buswidth = 32,
265 	.num_links = 3,
266 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
267 		   SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
268 };
269 
270 static struct qcom_icc_node qnm_gpu = {
271 	.name = "qnm_gpu",
272 	.id = SM8450_MASTER_GFX3D,
273 	.channels = 2,
274 	.buswidth = 32,
275 	.num_links = 2,
276 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
277 };
278 
279 static struct qcom_icc_node qnm_mdsp = {
280 	.name = "qnm_mdsp",
281 	.id = SM8450_MASTER_MSS_PROC,
282 	.channels = 1,
283 	.buswidth = 16,
284 	.num_links = 3,
285 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
286 		   SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
287 };
288 
289 static struct qcom_icc_node qnm_mnoc_hf = {
290 	.name = "qnm_mnoc_hf",
291 	.id = SM8450_MASTER_MNOC_HF_MEM_NOC,
292 	.channels = 2,
293 	.buswidth = 32,
294 	.num_links = 1,
295 	.links = { SM8450_SLAVE_LLCC },
296 };
297 
298 static struct qcom_icc_node qnm_mnoc_sf = {
299 	.name = "qnm_mnoc_sf",
300 	.id = SM8450_MASTER_MNOC_SF_MEM_NOC,
301 	.channels = 2,
302 	.buswidth = 32,
303 	.num_links = 2,
304 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
305 };
306 
307 static struct qcom_icc_node qnm_nsp_gemnoc = {
308 	.name = "qnm_nsp_gemnoc",
309 	.id = SM8450_MASTER_COMPUTE_NOC,
310 	.channels = 2,
311 	.buswidth = 32,
312 	.num_links = 2,
313 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
314 };
315 
316 static struct qcom_icc_node qnm_pcie = {
317 	.name = "qnm_pcie",
318 	.id = SM8450_MASTER_ANOC_PCIE_GEM_NOC,
319 	.channels = 1,
320 	.buswidth = 16,
321 	.num_links = 2,
322 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC },
323 };
324 
325 static struct qcom_icc_node qnm_snoc_gc = {
326 	.name = "qnm_snoc_gc",
327 	.id = SM8450_MASTER_SNOC_GC_MEM_NOC,
328 	.channels = 1,
329 	.buswidth = 8,
330 	.num_links = 1,
331 	.links = { SM8450_SLAVE_LLCC },
332 };
333 
334 static struct qcom_icc_node qnm_snoc_sf = {
335 	.name = "qnm_snoc_sf",
336 	.id = SM8450_MASTER_SNOC_SF_MEM_NOC,
337 	.channels = 1,
338 	.buswidth = 16,
339 	.num_links = 3,
340 	.links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC,
341 		   SM8450_SLAVE_MEM_NOC_PCIE_SNOC },
342 };
343 
344 static struct qcom_icc_node qhm_config_noc = {
345 	.name = "qhm_config_noc",
346 	.id = SM8450_MASTER_CNOC_LPASS_AG_NOC,
347 	.channels = 1,
348 	.buswidth = 4,
349 	.num_links = 6,
350 	.links = { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG,
351 		   SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG,
352 		   SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC },
353 };
354 
355 static struct qcom_icc_node qxm_lpass_dsp = {
356 	.name = "qxm_lpass_dsp",
357 	.id = SM8450_MASTER_LPASS_PROC,
358 	.channels = 1,
359 	.buswidth = 8,
360 	.num_links = 4,
361 	.links = { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC,
362 		   SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC },
363 };
364 
365 static struct qcom_icc_node llcc_mc = {
366 	.name = "llcc_mc",
367 	.id = SM8450_MASTER_LLCC,
368 	.channels = 4,
369 	.buswidth = 4,
370 	.num_links = 1,
371 	.links = { SM8450_SLAVE_EBI1 },
372 };
373 
374 static struct qcom_icc_node qnm_camnoc_hf = {
375 	.name = "qnm_camnoc_hf",
376 	.id = SM8450_MASTER_CAMNOC_HF,
377 	.channels = 2,
378 	.buswidth = 32,
379 	.num_links = 1,
380 	.links = { SM8450_SLAVE_MNOC_HF_MEM_NOC },
381 };
382 
383 static struct qcom_icc_node qnm_camnoc_icp = {
384 	.name = "qnm_camnoc_icp",
385 	.id = SM8450_MASTER_CAMNOC_ICP,
386 	.channels = 1,
387 	.buswidth = 8,
388 	.num_links = 1,
389 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
390 };
391 
392 static struct qcom_icc_node qnm_camnoc_sf = {
393 	.name = "qnm_camnoc_sf",
394 	.id = SM8450_MASTER_CAMNOC_SF,
395 	.channels = 2,
396 	.buswidth = 32,
397 	.num_links = 1,
398 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
399 };
400 
401 static struct qcom_icc_node qnm_mdp = {
402 	.name = "qnm_mdp",
403 	.id = SM8450_MASTER_MDP,
404 	.channels = 2,
405 	.buswidth = 32,
406 	.num_links = 1,
407 	.links = { SM8450_SLAVE_MNOC_HF_MEM_NOC },
408 };
409 
410 static struct qcom_icc_node qnm_mnoc_cfg = {
411 	.name = "qnm_mnoc_cfg",
412 	.id = SM8450_MASTER_CNOC_MNOC_CFG,
413 	.channels = 1,
414 	.buswidth = 4,
415 	.num_links = 1,
416 	.links = { SM8450_SLAVE_SERVICE_MNOC },
417 };
418 
419 static struct qcom_icc_node qnm_rot = {
420 	.name = "qnm_rot",
421 	.id = SM8450_MASTER_ROTATOR,
422 	.channels = 1,
423 	.buswidth = 32,
424 	.num_links = 1,
425 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
426 };
427 
428 static struct qcom_icc_node qnm_vapss_hcp = {
429 	.name = "qnm_vapss_hcp",
430 	.id = SM8450_MASTER_CDSP_HCP,
431 	.channels = 1,
432 	.buswidth = 32,
433 	.num_links = 1,
434 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
435 };
436 
437 static struct qcom_icc_node qnm_video = {
438 	.name = "qnm_video",
439 	.id = SM8450_MASTER_VIDEO,
440 	.channels = 2,
441 	.buswidth = 32,
442 	.num_links = 1,
443 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
444 };
445 
446 static struct qcom_icc_node qnm_video_cv_cpu = {
447 	.name = "qnm_video_cv_cpu",
448 	.id = SM8450_MASTER_VIDEO_CV_PROC,
449 	.channels = 1,
450 	.buswidth = 8,
451 	.num_links = 1,
452 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
453 };
454 
455 static struct qcom_icc_node qnm_video_cvp = {
456 	.name = "qnm_video_cvp",
457 	.id = SM8450_MASTER_VIDEO_PROC,
458 	.channels = 1,
459 	.buswidth = 32,
460 	.num_links = 1,
461 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
462 };
463 
464 static struct qcom_icc_node qnm_video_v_cpu = {
465 	.name = "qnm_video_v_cpu",
466 	.id = SM8450_MASTER_VIDEO_V_PROC,
467 	.channels = 1,
468 	.buswidth = 8,
469 	.num_links = 1,
470 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC },
471 };
472 
473 static struct qcom_icc_node qhm_nsp_noc_config = {
474 	.name = "qhm_nsp_noc_config",
475 	.id = SM8450_MASTER_CDSP_NOC_CFG,
476 	.channels = 1,
477 	.buswidth = 4,
478 	.num_links = 1,
479 	.links = { SM8450_SLAVE_SERVICE_NSP_NOC },
480 };
481 
482 static struct qcom_icc_node qxm_nsp = {
483 	.name = "qxm_nsp",
484 	.id = SM8450_MASTER_CDSP_PROC,
485 	.channels = 2,
486 	.buswidth = 32,
487 	.num_links = 1,
488 	.links = { SM8450_SLAVE_CDSP_MEM_NOC },
489 };
490 
491 static struct qcom_icc_node qnm_pcie_anoc_cfg = {
492 	.name = "qnm_pcie_anoc_cfg",
493 	.id = SM8450_MASTER_PCIE_ANOC_CFG,
494 	.channels = 1,
495 	.buswidth = 4,
496 	.num_links = 1,
497 	.links = { SM8450_SLAVE_SERVICE_PCIE_ANOC },
498 };
499 
500 static struct qcom_icc_node xm_pcie3_0 = {
501 	.name = "xm_pcie3_0",
502 	.id = SM8450_MASTER_PCIE_0,
503 	.channels = 1,
504 	.buswidth = 8,
505 	.num_links = 1,
506 	.links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC },
507 };
508 
509 static struct qcom_icc_node xm_pcie3_1 = {
510 	.name = "xm_pcie3_1",
511 	.id = SM8450_MASTER_PCIE_1,
512 	.channels = 1,
513 	.buswidth = 8,
514 	.num_links = 1,
515 	.links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC },
516 };
517 
518 static struct qcom_icc_node qhm_gic = {
519 	.name = "qhm_gic",
520 	.id = SM8450_MASTER_GIC_AHB,
521 	.channels = 1,
522 	.buswidth = 4,
523 	.num_links = 1,
524 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
525 };
526 
527 static struct qcom_icc_node qnm_aggre1_noc = {
528 	.name = "qnm_aggre1_noc",
529 	.id = SM8450_MASTER_A1NOC_SNOC,
530 	.channels = 1,
531 	.buswidth = 16,
532 	.num_links = 1,
533 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
534 };
535 
536 static struct qcom_icc_node qnm_aggre2_noc = {
537 	.name = "qnm_aggre2_noc",
538 	.id = SM8450_MASTER_A2NOC_SNOC,
539 	.channels = 1,
540 	.buswidth = 16,
541 	.num_links = 1,
542 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
543 };
544 
545 static struct qcom_icc_node qnm_lpass_noc = {
546 	.name = "qnm_lpass_noc",
547 	.id = SM8450_MASTER_LPASS_ANOC,
548 	.channels = 1,
549 	.buswidth = 16,
550 	.num_links = 1,
551 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_SF },
552 };
553 
554 static struct qcom_icc_node qnm_snoc_cfg = {
555 	.name = "qnm_snoc_cfg",
556 	.id = SM8450_MASTER_SNOC_CFG,
557 	.channels = 1,
558 	.buswidth = 4,
559 	.num_links = 1,
560 	.links = { SM8450_SLAVE_SERVICE_SNOC },
561 };
562 
563 static struct qcom_icc_node qxm_pimem = {
564 	.name = "qxm_pimem",
565 	.id = SM8450_MASTER_PIMEM,
566 	.channels = 1,
567 	.buswidth = 8,
568 	.num_links = 1,
569 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_GC },
570 };
571 
572 static struct qcom_icc_node xm_gic = {
573 	.name = "xm_gic",
574 	.id = SM8450_MASTER_GIC,
575 	.channels = 1,
576 	.buswidth = 8,
577 	.num_links = 1,
578 	.links = { SM8450_SLAVE_SNOC_GEM_NOC_GC },
579 };
580 
581 static struct qcom_icc_node qnm_mnoc_hf_disp = {
582 	.name = "qnm_mnoc_hf_disp",
583 	.id = SM8450_MASTER_MNOC_HF_MEM_NOC_DISP,
584 	.channels = 2,
585 	.buswidth = 32,
586 	.num_links = 1,
587 	.links = { SM8450_SLAVE_LLCC_DISP },
588 };
589 
590 static struct qcom_icc_node qnm_mnoc_sf_disp = {
591 	.name = "qnm_mnoc_sf_disp",
592 	.id = SM8450_MASTER_MNOC_SF_MEM_NOC_DISP,
593 	.channels = 2,
594 	.buswidth = 32,
595 	.num_links = 1,
596 	.links = { SM8450_SLAVE_LLCC_DISP },
597 };
598 
599 static struct qcom_icc_node qnm_pcie_disp = {
600 	.name = "qnm_pcie_disp",
601 	.id = SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP,
602 	.channels = 1,
603 	.buswidth = 16,
604 	.num_links = 1,
605 	.links = { SM8450_SLAVE_LLCC_DISP },
606 };
607 
608 static struct qcom_icc_node llcc_mc_disp = {
609 	.name = "llcc_mc_disp",
610 	.id = SM8450_MASTER_LLCC_DISP,
611 	.channels = 4,
612 	.buswidth = 4,
613 	.num_links = 1,
614 	.links = { SM8450_SLAVE_EBI1_DISP },
615 };
616 
617 static struct qcom_icc_node qnm_mdp_disp = {
618 	.name = "qnm_mdp_disp",
619 	.id = SM8450_MASTER_MDP_DISP,
620 	.channels = 2,
621 	.buswidth = 32,
622 	.num_links = 1,
623 	.links = { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP },
624 };
625 
626 static struct qcom_icc_node qnm_rot_disp = {
627 	.name = "qnm_rot_disp",
628 	.id = SM8450_MASTER_ROTATOR_DISP,
629 	.channels = 1,
630 	.buswidth = 32,
631 	.num_links = 1,
632 	.links = { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP },
633 };
634 
635 static struct qcom_icc_node qns_a1noc_snoc = {
636 	.name = "qns_a1noc_snoc",
637 	.id = SM8450_SLAVE_A1NOC_SNOC,
638 	.channels = 1,
639 	.buswidth = 16,
640 	.num_links = 1,
641 	.links = { SM8450_MASTER_A1NOC_SNOC },
642 };
643 
644 static struct qcom_icc_node srvc_aggre1_noc = {
645 	.name = "srvc_aggre1_noc",
646 	.id = SM8450_SLAVE_SERVICE_A1NOC,
647 	.channels = 1,
648 	.buswidth = 4,
649 	.num_links = 0,
650 };
651 
652 static struct qcom_icc_node qns_a2noc_snoc = {
653 	.name = "qns_a2noc_snoc",
654 	.id = SM8450_SLAVE_A2NOC_SNOC,
655 	.channels = 1,
656 	.buswidth = 16,
657 	.num_links = 1,
658 	.links = { SM8450_MASTER_A2NOC_SNOC },
659 };
660 
661 static struct qcom_icc_node srvc_aggre2_noc = {
662 	.name = "srvc_aggre2_noc",
663 	.id = SM8450_SLAVE_SERVICE_A2NOC,
664 	.channels = 1,
665 	.buswidth = 4,
666 	.num_links = 0,
667 };
668 
669 static struct qcom_icc_node qup0_core_slave = {
670 	.name = "qup0_core_slave",
671 	.id = SM8450_SLAVE_QUP_CORE_0,
672 	.channels = 1,
673 	.buswidth = 4,
674 	.num_links = 0,
675 };
676 
677 static struct qcom_icc_node qup1_core_slave = {
678 	.name = "qup1_core_slave",
679 	.id = SM8450_SLAVE_QUP_CORE_1,
680 	.channels = 1,
681 	.buswidth = 4,
682 	.num_links = 0,
683 };
684 
685 static struct qcom_icc_node qup2_core_slave = {
686 	.name = "qup2_core_slave",
687 	.id = SM8450_SLAVE_QUP_CORE_2,
688 	.channels = 1,
689 	.buswidth = 4,
690 	.num_links = 0,
691 };
692 
693 static struct qcom_icc_node qhs_ahb2phy0 = {
694 	.name = "qhs_ahb2phy0",
695 	.id = SM8450_SLAVE_AHB2PHY_SOUTH,
696 	.channels = 1,
697 	.buswidth = 4,
698 	.num_links = 0,
699 };
700 
701 static struct qcom_icc_node qhs_ahb2phy1 = {
702 	.name = "qhs_ahb2phy1",
703 	.id = SM8450_SLAVE_AHB2PHY_NORTH,
704 	.channels = 1,
705 	.buswidth = 4,
706 	.num_links = 0,
707 };
708 
709 static struct qcom_icc_node qhs_aoss = {
710 	.name = "qhs_aoss",
711 	.id = SM8450_SLAVE_AOSS,
712 	.channels = 1,
713 	.buswidth = 4,
714 	.num_links = 0,
715 };
716 
717 static struct qcom_icc_node qhs_camera_cfg = {
718 	.name = "qhs_camera_cfg",
719 	.id = SM8450_SLAVE_CAMERA_CFG,
720 	.channels = 1,
721 	.buswidth = 4,
722 	.num_links = 0,
723 };
724 
725 static struct qcom_icc_node qhs_clk_ctl = {
726 	.name = "qhs_clk_ctl",
727 	.id = SM8450_SLAVE_CLK_CTL,
728 	.channels = 1,
729 	.buswidth = 4,
730 	.num_links = 0,
731 };
732 
733 static struct qcom_icc_node qhs_compute_cfg = {
734 	.name = "qhs_compute_cfg",
735 	.id = SM8450_SLAVE_CDSP_CFG,
736 	.channels = 1,
737 	.buswidth = 4,
738 	.num_links = 1,
739 	.links = { MASTER_CDSP_NOC_CFG },
740 };
741 
742 static struct qcom_icc_node qhs_cpr_cx = {
743 	.name = "qhs_cpr_cx",
744 	.id = SM8450_SLAVE_RBCPR_CX_CFG,
745 	.channels = 1,
746 	.buswidth = 4,
747 	.num_links = 0,
748 };
749 
750 static struct qcom_icc_node qhs_cpr_mmcx = {
751 	.name = "qhs_cpr_mmcx",
752 	.id = SM8450_SLAVE_RBCPR_MMCX_CFG,
753 	.channels = 1,
754 	.buswidth = 4,
755 	.num_links = 0,
756 };
757 
758 static struct qcom_icc_node qhs_cpr_mxa = {
759 	.name = "qhs_cpr_mxa",
760 	.id = SM8450_SLAVE_RBCPR_MXA_CFG,
761 	.channels = 1,
762 	.buswidth = 4,
763 	.num_links = 0,
764 };
765 
766 static struct qcom_icc_node qhs_cpr_mxc = {
767 	.name = "qhs_cpr_mxc",
768 	.id = SM8450_SLAVE_RBCPR_MXC_CFG,
769 	.channels = 1,
770 	.buswidth = 4,
771 	.num_links = 0,
772 };
773 
774 static struct qcom_icc_node qhs_crypto0_cfg = {
775 	.name = "qhs_crypto0_cfg",
776 	.id = SM8450_SLAVE_CRYPTO_0_CFG,
777 	.channels = 1,
778 	.buswidth = 4,
779 	.num_links = 0,
780 };
781 
782 static struct qcom_icc_node qhs_cx_rdpm = {
783 	.name = "qhs_cx_rdpm",
784 	.id = SM8450_SLAVE_CX_RDPM,
785 	.channels = 1,
786 	.buswidth = 4,
787 	.num_links = 0,
788 };
789 
790 static struct qcom_icc_node qhs_display_cfg = {
791 	.name = "qhs_display_cfg",
792 	.id = SM8450_SLAVE_DISPLAY_CFG,
793 	.channels = 1,
794 	.buswidth = 4,
795 	.num_links = 0,
796 };
797 
798 static struct qcom_icc_node qhs_gpuss_cfg = {
799 	.name = "qhs_gpuss_cfg",
800 	.id = SM8450_SLAVE_GFX3D_CFG,
801 	.channels = 1,
802 	.buswidth = 8,
803 	.num_links = 0,
804 };
805 
806 static struct qcom_icc_node qhs_imem_cfg = {
807 	.name = "qhs_imem_cfg",
808 	.id = SM8450_SLAVE_IMEM_CFG,
809 	.channels = 1,
810 	.buswidth = 4,
811 	.num_links = 0,
812 };
813 
814 static struct qcom_icc_node qhs_ipa = {
815 	.name = "qhs_ipa",
816 	.id = SM8450_SLAVE_IPA_CFG,
817 	.channels = 1,
818 	.buswidth = 4,
819 	.num_links = 0,
820 };
821 
822 static struct qcom_icc_node qhs_ipc_router = {
823 	.name = "qhs_ipc_router",
824 	.id = SM8450_SLAVE_IPC_ROUTER_CFG,
825 	.channels = 1,
826 	.buswidth = 4,
827 	.num_links = 0,
828 };
829 
830 static struct qcom_icc_node qhs_lpass_cfg = {
831 	.name = "qhs_lpass_cfg",
832 	.id = SM8450_SLAVE_LPASS,
833 	.channels = 1,
834 	.buswidth = 4,
835 	.num_links = 1,
836 	.links = { MASTER_CNOC_LPASS_AG_NOC },
837 };
838 
839 static struct qcom_icc_node qhs_mss_cfg = {
840 	.name = "qhs_mss_cfg",
841 	.id = SM8450_SLAVE_CNOC_MSS,
842 	.channels = 1,
843 	.buswidth = 4,
844 	.num_links = 0,
845 };
846 
847 static struct qcom_icc_node qhs_mx_rdpm = {
848 	.name = "qhs_mx_rdpm",
849 	.id = SM8450_SLAVE_MX_RDPM,
850 	.channels = 1,
851 	.buswidth = 4,
852 	.num_links = 0,
853 };
854 
855 static struct qcom_icc_node qhs_pcie0_cfg = {
856 	.name = "qhs_pcie0_cfg",
857 	.id = SM8450_SLAVE_PCIE_0_CFG,
858 	.channels = 1,
859 	.buswidth = 4,
860 	.num_links = 0,
861 };
862 
863 static struct qcom_icc_node qhs_pcie1_cfg = {
864 	.name = "qhs_pcie1_cfg",
865 	.id = SM8450_SLAVE_PCIE_1_CFG,
866 	.channels = 1,
867 	.buswidth = 4,
868 	.num_links = 0,
869 };
870 
871 static struct qcom_icc_node qhs_pdm = {
872 	.name = "qhs_pdm",
873 	.id = SM8450_SLAVE_PDM,
874 	.channels = 1,
875 	.buswidth = 4,
876 	.num_links = 0,
877 };
878 
879 static struct qcom_icc_node qhs_pimem_cfg = {
880 	.name = "qhs_pimem_cfg",
881 	.id = SM8450_SLAVE_PIMEM_CFG,
882 	.channels = 1,
883 	.buswidth = 4,
884 	.num_links = 0,
885 };
886 
887 static struct qcom_icc_node qhs_prng = {
888 	.name = "qhs_prng",
889 	.id = SM8450_SLAVE_PRNG,
890 	.channels = 1,
891 	.buswidth = 4,
892 	.num_links = 0,
893 };
894 
895 static struct qcom_icc_node qhs_qdss_cfg = {
896 	.name = "qhs_qdss_cfg",
897 	.id = SM8450_SLAVE_QDSS_CFG,
898 	.channels = 1,
899 	.buswidth = 4,
900 	.num_links = 0,
901 };
902 
903 static struct qcom_icc_node qhs_qspi = {
904 	.name = "qhs_qspi",
905 	.id = SM8450_SLAVE_QSPI_0,
906 	.channels = 1,
907 	.buswidth = 4,
908 	.num_links = 0,
909 };
910 
911 static struct qcom_icc_node qhs_qup0 = {
912 	.name = "qhs_qup0",
913 	.id = SM8450_SLAVE_QUP_0,
914 	.channels = 1,
915 	.buswidth = 4,
916 	.num_links = 0,
917 };
918 
919 static struct qcom_icc_node qhs_qup1 = {
920 	.name = "qhs_qup1",
921 	.id = SM8450_SLAVE_QUP_1,
922 	.channels = 1,
923 	.buswidth = 4,
924 	.num_links = 0,
925 };
926 
927 static struct qcom_icc_node qhs_qup2 = {
928 	.name = "qhs_qup2",
929 	.id = SM8450_SLAVE_QUP_2,
930 	.channels = 1,
931 	.buswidth = 4,
932 	.num_links = 0,
933 };
934 
935 static struct qcom_icc_node qhs_sdc2 = {
936 	.name = "qhs_sdc2",
937 	.id = SM8450_SLAVE_SDCC_2,
938 	.channels = 1,
939 	.buswidth = 4,
940 	.num_links = 0,
941 };
942 
943 static struct qcom_icc_node qhs_sdc4 = {
944 	.name = "qhs_sdc4",
945 	.id = SM8450_SLAVE_SDCC_4,
946 	.channels = 1,
947 	.buswidth = 4,
948 	.num_links = 0,
949 };
950 
951 static struct qcom_icc_node qhs_spss_cfg = {
952 	.name = "qhs_spss_cfg",
953 	.id = SM8450_SLAVE_SPSS_CFG,
954 	.channels = 1,
955 	.buswidth = 4,
956 	.num_links = 0,
957 };
958 
959 static struct qcom_icc_node qhs_tcsr = {
960 	.name = "qhs_tcsr",
961 	.id = SM8450_SLAVE_TCSR,
962 	.channels = 1,
963 	.buswidth = 4,
964 	.num_links = 0,
965 };
966 
967 static struct qcom_icc_node qhs_tlmm = {
968 	.name = "qhs_tlmm",
969 	.id = SM8450_SLAVE_TLMM,
970 	.channels = 1,
971 	.buswidth = 4,
972 	.num_links = 0,
973 };
974 
975 static struct qcom_icc_node qhs_tme_cfg = {
976 	.name = "qhs_tme_cfg",
977 	.id = SM8450_SLAVE_TME_CFG,
978 	.channels = 1,
979 	.buswidth = 4,
980 	.num_links = 0,
981 };
982 
983 static struct qcom_icc_node qhs_ufs_mem_cfg = {
984 	.name = "qhs_ufs_mem_cfg",
985 	.id = SM8450_SLAVE_UFS_MEM_CFG,
986 	.channels = 1,
987 	.buswidth = 4,
988 	.num_links = 0,
989 };
990 
991 static struct qcom_icc_node qhs_usb3_0 = {
992 	.name = "qhs_usb3_0",
993 	.id = SM8450_SLAVE_USB3_0,
994 	.channels = 1,
995 	.buswidth = 4,
996 	.num_links = 0,
997 };
998 
999 static struct qcom_icc_node qhs_venus_cfg = {
1000 	.name = "qhs_venus_cfg",
1001 	.id = SM8450_SLAVE_VENUS_CFG,
1002 	.channels = 1,
1003 	.buswidth = 4,
1004 	.num_links = 0,
1005 };
1006 
1007 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1008 	.name = "qhs_vsense_ctrl_cfg",
1009 	.id = SM8450_SLAVE_VSENSE_CTRL_CFG,
1010 	.channels = 1,
1011 	.buswidth = 4,
1012 	.num_links = 0,
1013 };
1014 
1015 static struct qcom_icc_node qns_a1_noc_cfg = {
1016 	.name = "qns_a1_noc_cfg",
1017 	.id = SM8450_SLAVE_A1NOC_CFG,
1018 	.channels = 1,
1019 	.buswidth = 4,
1020 	.num_links = 1,
1021 	.links = { SM8450_MASTER_A1NOC_CFG },
1022 };
1023 
1024 static struct qcom_icc_node qns_a2_noc_cfg = {
1025 	.name = "qns_a2_noc_cfg",
1026 	.id = SM8450_SLAVE_A2NOC_CFG,
1027 	.channels = 1,
1028 	.buswidth = 4,
1029 	.num_links = 1,
1030 	.links = { SM8450_MASTER_A2NOC_CFG },
1031 };
1032 
1033 static struct qcom_icc_node qns_ddrss_cfg = {
1034 	.name = "qns_ddrss_cfg",
1035 	.id = SM8450_SLAVE_DDRSS_CFG,
1036 	.channels = 1,
1037 	.buswidth = 4,
1038 	.num_links = 1,
1039 	//FIXME where is link
1040 };
1041 
1042 static struct qcom_icc_node qns_mnoc_cfg = {
1043 	.name = "qns_mnoc_cfg",
1044 	.id = SM8450_SLAVE_CNOC_MNOC_CFG,
1045 	.channels = 1,
1046 	.buswidth = 4,
1047 	.num_links = 1,
1048 	.links = { SM8450_MASTER_CNOC_MNOC_CFG },
1049 };
1050 
1051 static struct qcom_icc_node qns_pcie_anoc_cfg = {
1052 	.name = "qns_pcie_anoc_cfg",
1053 	.id = SM8450_SLAVE_PCIE_ANOC_CFG,
1054 	.channels = 1,
1055 	.buswidth = 4,
1056 	.num_links = 1,
1057 	.links = { SM8450_MASTER_PCIE_ANOC_CFG },
1058 };
1059 
1060 static struct qcom_icc_node qns_snoc_cfg = {
1061 	.name = "qns_snoc_cfg",
1062 	.id = SM8450_SLAVE_SNOC_CFG,
1063 	.channels = 1,
1064 	.buswidth = 4,
1065 	.num_links = 1,
1066 	.links = { SM8450_MASTER_SNOC_CFG },
1067 };
1068 
1069 static struct qcom_icc_node qxs_imem = {
1070 	.name = "qxs_imem",
1071 	.id = SM8450_SLAVE_IMEM,
1072 	.channels = 1,
1073 	.buswidth = 8,
1074 	.num_links = 0,
1075 };
1076 
1077 static struct qcom_icc_node qxs_pimem = {
1078 	.name = "qxs_pimem",
1079 	.id = SM8450_SLAVE_PIMEM,
1080 	.channels = 1,
1081 	.buswidth = 8,
1082 	.num_links = 0,
1083 };
1084 
1085 static struct qcom_icc_node srvc_cnoc = {
1086 	.name = "srvc_cnoc",
1087 	.id = SM8450_SLAVE_SERVICE_CNOC,
1088 	.channels = 1,
1089 	.buswidth = 4,
1090 	.num_links = 0,
1091 };
1092 
1093 static struct qcom_icc_node xs_pcie_0 = {
1094 	.name = "xs_pcie_0",
1095 	.id = SM8450_SLAVE_PCIE_0,
1096 	.channels = 1,
1097 	.buswidth = 8,
1098 	.num_links = 0,
1099 };
1100 
1101 static struct qcom_icc_node xs_pcie_1 = {
1102 	.name = "xs_pcie_1",
1103 	.id = SM8450_SLAVE_PCIE_1,
1104 	.channels = 1,
1105 	.buswidth = 8,
1106 	.num_links = 0,
1107 };
1108 
1109 static struct qcom_icc_node xs_qdss_stm = {
1110 	.name = "xs_qdss_stm",
1111 	.id = SM8450_SLAVE_QDSS_STM,
1112 	.channels = 1,
1113 	.buswidth = 4,
1114 	.num_links = 0,
1115 };
1116 
1117 static struct qcom_icc_node xs_sys_tcu_cfg = {
1118 	.name = "xs_sys_tcu_cfg",
1119 	.id = SM8450_SLAVE_TCU,
1120 	.channels = 1,
1121 	.buswidth = 8,
1122 	.num_links = 0,
1123 };
1124 
1125 static struct qcom_icc_node qns_gem_noc_cnoc = {
1126 	.name = "qns_gem_noc_cnoc",
1127 	.id = SM8450_SLAVE_GEM_NOC_CNOC,
1128 	.channels = 1,
1129 	.buswidth = 16,
1130 	.num_links = 1,
1131 	.links = { SM8450_MASTER_GEM_NOC_CNOC },
1132 };
1133 
1134 static struct qcom_icc_node qns_llcc = {
1135 	.name = "qns_llcc",
1136 	.id = SM8450_SLAVE_LLCC,
1137 	.channels = 4,
1138 	.buswidth = 16,
1139 	.num_links = 1,
1140 	.links = { SM8450_MASTER_LLCC },
1141 };
1142 
1143 static struct qcom_icc_node qns_pcie = {
1144 	.name = "qns_pcie",
1145 	.id = SM8450_SLAVE_MEM_NOC_PCIE_SNOC,
1146 	.channels = 1,
1147 	.buswidth = 8,
1148 	.num_links = 1,
1149 	.links = { SM8450_MASTER_GEM_NOC_PCIE_SNOC },
1150 };
1151 
1152 static struct qcom_icc_node qhs_lpass_core = {
1153 	.name = "qhs_lpass_core",
1154 	.id = SM8450_SLAVE_LPASS_CORE_CFG,
1155 	.channels = 1,
1156 	.buswidth = 4,
1157 	.num_links = 0,
1158 };
1159 
1160 static struct qcom_icc_node qhs_lpass_lpi = {
1161 	.name = "qhs_lpass_lpi",
1162 	.id = SM8450_SLAVE_LPASS_LPI_CFG,
1163 	.channels = 1,
1164 	.buswidth = 4,
1165 	.num_links = 0,
1166 };
1167 
1168 static struct qcom_icc_node qhs_lpass_mpu = {
1169 	.name = "qhs_lpass_mpu",
1170 	.id = SM8450_SLAVE_LPASS_MPU_CFG,
1171 	.channels = 1,
1172 	.buswidth = 4,
1173 	.num_links = 0,
1174 };
1175 
1176 static struct qcom_icc_node qhs_lpass_top = {
1177 	.name = "qhs_lpass_top",
1178 	.id = SM8450_SLAVE_LPASS_TOP_CFG,
1179 	.channels = 1,
1180 	.buswidth = 4,
1181 	.num_links = 0,
1182 };
1183 
1184 static struct qcom_icc_node qns_sysnoc = {
1185 	.name = "qns_sysnoc",
1186 	.id = SM8450_SLAVE_LPASS_SNOC,
1187 	.channels = 1,
1188 	.buswidth = 16,
1189 	.num_links = 1,
1190 	.links = { SM8450_MASTER_LPASS_ANOC },
1191 };
1192 
1193 static struct qcom_icc_node srvc_niu_aml_noc = {
1194 	.name = "srvc_niu_aml_noc",
1195 	.id = SM8450_SLAVE_SERVICES_LPASS_AML_NOC,
1196 	.channels = 1,
1197 	.buswidth = 4,
1198 	.num_links = 0,
1199 };
1200 
1201 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1202 	.name = "srvc_niu_lpass_agnoc",
1203 	.id = SM8450_SLAVE_SERVICE_LPASS_AG_NOC,
1204 	.channels = 1,
1205 	.buswidth = 4,
1206 	.num_links = 0,
1207 };
1208 
1209 static struct qcom_icc_node ebi = {
1210 	.name = "ebi",
1211 	.id = SM8450_SLAVE_EBI1,
1212 	.channels = 4,
1213 	.buswidth = 4,
1214 	.num_links = 0,
1215 };
1216 
1217 static struct qcom_icc_node qns_mem_noc_hf = {
1218 	.name = "qns_mem_noc_hf",
1219 	.id = SM8450_SLAVE_MNOC_HF_MEM_NOC,
1220 	.channels = 2,
1221 	.buswidth = 32,
1222 	.num_links = 1,
1223 	.links = { SM8450_MASTER_MNOC_HF_MEM_NOC },
1224 };
1225 
1226 static struct qcom_icc_node qns_mem_noc_sf = {
1227 	.name = "qns_mem_noc_sf",
1228 	.id = SM8450_SLAVE_MNOC_SF_MEM_NOC,
1229 	.channels = 2,
1230 	.buswidth = 32,
1231 	.num_links = 1,
1232 	.links = { SM8450_MASTER_MNOC_SF_MEM_NOC },
1233 };
1234 
1235 static struct qcom_icc_node srvc_mnoc = {
1236 	.name = "srvc_mnoc",
1237 	.id = SM8450_SLAVE_SERVICE_MNOC,
1238 	.channels = 1,
1239 	.buswidth = 4,
1240 	.num_links = 0,
1241 };
1242 
1243 static struct qcom_icc_node qns_nsp_gemnoc = {
1244 	.name = "qns_nsp_gemnoc",
1245 	.id = SM8450_SLAVE_CDSP_MEM_NOC,
1246 	.channels = 2,
1247 	.buswidth = 32,
1248 	.num_links = 1,
1249 	.links = { SM8450_MASTER_COMPUTE_NOC },
1250 };
1251 
1252 static struct qcom_icc_node service_nsp_noc = {
1253 	.name = "service_nsp_noc",
1254 	.id = SM8450_SLAVE_SERVICE_NSP_NOC,
1255 	.channels = 1,
1256 	.buswidth = 4,
1257 	.num_links = 0,
1258 };
1259 
1260 static struct qcom_icc_node qns_pcie_mem_noc = {
1261 	.name = "qns_pcie_mem_noc",
1262 	.id = SM8450_SLAVE_ANOC_PCIE_GEM_NOC,
1263 	.channels = 1,
1264 	.buswidth = 16,
1265 	.num_links = 1,
1266 	.links = { SM8450_MASTER_ANOC_PCIE_GEM_NOC },
1267 };
1268 
1269 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1270 	.name = "srvc_pcie_aggre_noc",
1271 	.id = SM8450_SLAVE_SERVICE_PCIE_ANOC,
1272 	.channels = 1,
1273 	.buswidth = 4,
1274 	.num_links = 0,
1275 };
1276 
1277 static struct qcom_icc_node qns_gemnoc_gc = {
1278 	.name = "qns_gemnoc_gc",
1279 	.id = SM8450_SLAVE_SNOC_GEM_NOC_GC,
1280 	.channels = 1,
1281 	.buswidth = 8,
1282 	.num_links = 1,
1283 	.links = { SM8450_MASTER_SNOC_GC_MEM_NOC },
1284 };
1285 
1286 static struct qcom_icc_node qns_gemnoc_sf = {
1287 	.name = "qns_gemnoc_sf",
1288 	.id = SM8450_SLAVE_SNOC_GEM_NOC_SF,
1289 	.channels = 1,
1290 	.buswidth = 16,
1291 	.num_links = 1,
1292 	.links = { SM8450_MASTER_SNOC_SF_MEM_NOC },
1293 };
1294 
1295 static struct qcom_icc_node srvc_snoc = {
1296 	.name = "srvc_snoc",
1297 	.id = SM8450_SLAVE_SERVICE_SNOC,
1298 	.channels = 1,
1299 	.buswidth = 4,
1300 	.num_links = 0,
1301 };
1302 
1303 static struct qcom_icc_node qns_llcc_disp = {
1304 	.name = "qns_llcc_disp",
1305 	.id = SM8450_SLAVE_LLCC_DISP,
1306 	.channels = 4,
1307 	.buswidth = 16,
1308 	.num_links = 1,
1309 	.links = { SM8450_MASTER_LLCC_DISP },
1310 };
1311 
1312 static struct qcom_icc_node ebi_disp = {
1313 	.name = "ebi_disp",
1314 	.id = SM8450_SLAVE_EBI1_DISP,
1315 	.channels = 4,
1316 	.buswidth = 4,
1317 	.num_links = 0,
1318 };
1319 
1320 static struct qcom_icc_node qns_mem_noc_hf_disp = {
1321 	.name = "qns_mem_noc_hf_disp",
1322 	.id = SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP,
1323 	.channels = 2,
1324 	.buswidth = 32,
1325 	.num_links = 1,
1326 	.links = { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP },
1327 };
1328 
1329 static struct qcom_icc_node qns_mem_noc_sf_disp = {
1330 	.name = "qns_mem_noc_sf_disp",
1331 	.id = SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP,
1332 	.channels = 2,
1333 	.buswidth = 32,
1334 	.num_links = 1,
1335 	.links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP },
1336 };
1337 
1338 static struct qcom_icc_bcm bcm_acv = {
1339 	.name = "ACV",
1340 	.num_nodes = 1,
1341 	.nodes = { &ebi },
1342 };
1343 
1344 static struct qcom_icc_bcm bcm_ce0 = {
1345 	.name = "CE0",
1346 	.num_nodes = 1,
1347 	.nodes = { &qxm_crypto },
1348 };
1349 
1350 static struct qcom_icc_bcm bcm_cn0 = {
1351 	.name = "CN0",
1352 	.keepalive = true,
1353 	.num_nodes = 55,
1354 	.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1355 		   &qhs_ahb2phy0, &qhs_ahb2phy1,
1356 		   &qhs_aoss, &qhs_camera_cfg,
1357 		   &qhs_clk_ctl, &qhs_compute_cfg,
1358 		   &qhs_cpr_cx, &qhs_cpr_mmcx,
1359 		   &qhs_cpr_mxa, &qhs_cpr_mxc,
1360 		   &qhs_crypto0_cfg, &qhs_cx_rdpm,
1361 		   &qhs_display_cfg, &qhs_gpuss_cfg,
1362 		   &qhs_imem_cfg, &qhs_ipa,
1363 		   &qhs_ipc_router, &qhs_lpass_cfg,
1364 		   &qhs_mss_cfg, &qhs_mx_rdpm,
1365 		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1366 		   &qhs_pdm, &qhs_pimem_cfg,
1367 		   &qhs_prng, &qhs_qdss_cfg,
1368 		   &qhs_qspi, &qhs_qup0,
1369 		   &qhs_qup1, &qhs_qup2,
1370 		   &qhs_sdc2, &qhs_sdc4,
1371 		   &qhs_spss_cfg, &qhs_tcsr,
1372 		   &qhs_tlmm, &qhs_tme_cfg,
1373 		   &qhs_ufs_mem_cfg, &qhs_usb3_0,
1374 		   &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1375 		   &qns_a1_noc_cfg, &qns_a2_noc_cfg,
1376 		   &qns_ddrss_cfg, &qns_mnoc_cfg,
1377 		   &qns_pcie_anoc_cfg, &qns_snoc_cfg,
1378 		   &qxs_imem, &qxs_pimem,
1379 		   &srvc_cnoc, &xs_pcie_0,
1380 		   &xs_pcie_1, &xs_qdss_stm,
1381 		   &xs_sys_tcu_cfg },
1382 };
1383 
1384 static struct qcom_icc_bcm bcm_co0 = {
1385 	.name = "CO0",
1386 	.num_nodes = 2,
1387 	.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1388 };
1389 
1390 static struct qcom_icc_bcm bcm_mc0 = {
1391 	.name = "MC0",
1392 	.keepalive = true,
1393 	.num_nodes = 1,
1394 	.nodes = { &ebi },
1395 };
1396 
1397 static struct qcom_icc_bcm bcm_mm0 = {
1398 	.name = "MM0",
1399 	.keepalive = true,
1400 	.num_nodes = 1,
1401 	.nodes = { &qns_mem_noc_hf },
1402 };
1403 
1404 static struct qcom_icc_bcm bcm_mm1 = {
1405 	.name = "MM1",
1406 	.num_nodes = 12,
1407 	.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1408 		   &qnm_camnoc_sf, &qnm_mdp,
1409 		   &qnm_mnoc_cfg, &qnm_rot,
1410 		   &qnm_vapss_hcp, &qnm_video,
1411 		   &qnm_video_cv_cpu, &qnm_video_cvp,
1412 		   &qnm_video_v_cpu, &qns_mem_noc_sf },
1413 };
1414 
1415 static struct qcom_icc_bcm bcm_qup0 = {
1416 	.name = "QUP0",
1417 	.keepalive = true,
1418 	.vote_scale = 1,
1419 	.num_nodes = 1,
1420 	.nodes = { &qup0_core_slave },
1421 };
1422 
1423 static struct qcom_icc_bcm bcm_qup1 = {
1424 	.name = "QUP1",
1425 	.keepalive = true,
1426 	.vote_scale = 1,
1427 	.num_nodes = 1,
1428 	.nodes = { &qup1_core_slave },
1429 };
1430 
1431 static struct qcom_icc_bcm bcm_qup2 = {
1432 	.name = "QUP2",
1433 	.keepalive = true,
1434 	.vote_scale = 1,
1435 	.num_nodes = 1,
1436 	.nodes = { &qup2_core_slave },
1437 };
1438 
1439 static struct qcom_icc_bcm bcm_sh0 = {
1440 	.name = "SH0",
1441 	.keepalive = true,
1442 	.num_nodes = 1,
1443 	.nodes = { &qns_llcc },
1444 };
1445 
1446 static struct qcom_icc_bcm bcm_sh1 = {
1447 	.name = "SH1",
1448 	.num_nodes = 7,
1449 	.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1450 		   &qnm_nsp_gemnoc, &qnm_pcie,
1451 		   &qnm_snoc_gc, &qns_gem_noc_cnoc,
1452 		   &qns_pcie },
1453 };
1454 
1455 static struct qcom_icc_bcm bcm_sn0 = {
1456 	.name = "SN0",
1457 	.keepalive = true,
1458 	.num_nodes = 1,
1459 	.nodes = { &qns_gemnoc_sf },
1460 };
1461 
1462 static struct qcom_icc_bcm bcm_sn1 = {
1463 	.name = "SN1",
1464 	.num_nodes = 4,
1465 	.nodes = { &qhm_gic, &qxm_pimem,
1466 		   &xm_gic, &qns_gemnoc_gc },
1467 };
1468 
1469 static struct qcom_icc_bcm bcm_sn2 = {
1470 	.name = "SN2",
1471 	.num_nodes = 1,
1472 	.nodes = { &qnm_aggre1_noc },
1473 };
1474 
1475 static struct qcom_icc_bcm bcm_sn3 = {
1476 	.name = "SN3",
1477 	.num_nodes = 1,
1478 	.nodes = { &qnm_aggre2_noc },
1479 };
1480 
1481 static struct qcom_icc_bcm bcm_sn4 = {
1482 	.name = "SN4",
1483 	.num_nodes = 1,
1484 	.nodes = { &qnm_lpass_noc },
1485 };
1486 
1487 static struct qcom_icc_bcm bcm_sn7 = {
1488 	.name = "SN7",
1489 	.num_nodes = 1,
1490 	.nodes = { &qns_pcie_mem_noc },
1491 };
1492 
1493 static struct qcom_icc_bcm bcm_acv_disp = {
1494 	.name = "ACV",
1495 	.num_nodes = 1,
1496 	.nodes = { &ebi_disp },
1497 };
1498 
1499 static struct qcom_icc_bcm bcm_mc0_disp = {
1500 	.name = "MC0",
1501 	.num_nodes = 1,
1502 	.nodes = { &ebi_disp },
1503 };
1504 
1505 static struct qcom_icc_bcm bcm_mm0_disp = {
1506 	.name = "MM0",
1507 	.num_nodes = 1,
1508 	.nodes = { &qns_mem_noc_hf_disp },
1509 };
1510 
1511 static struct qcom_icc_bcm bcm_mm1_disp = {
1512 	.name = "MM1",
1513 	.num_nodes = 3,
1514 	.nodes = { &qnm_mdp_disp, &qnm_rot_disp,
1515 		   &qns_mem_noc_sf_disp },
1516 };
1517 
1518 static struct qcom_icc_bcm bcm_sh0_disp = {
1519 	.name = "SH0",
1520 	.num_nodes = 1,
1521 	.nodes = { &qns_llcc_disp },
1522 };
1523 
1524 static struct qcom_icc_bcm bcm_sh1_disp = {
1525 	.name = "SH1",
1526 	.num_nodes = 1,
1527 	.nodes = { &qnm_pcie_disp },
1528 };
1529 
1530 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1531 };
1532 
1533 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1534 	[MASTER_QSPI_0] = &qhm_qspi,
1535 	[MASTER_QUP_1] = &qhm_qup1,
1536 	[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1537 	[MASTER_SDCC_4] = &xm_sdc4,
1538 	[MASTER_UFS_MEM] = &xm_ufs_mem,
1539 	[MASTER_USB3_0] = &xm_usb3_0,
1540 	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1541 	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1542 };
1543 
1544 static const struct qcom_icc_desc sm8450_aggre1_noc = {
1545 	.nodes = aggre1_noc_nodes,
1546 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1547 	.bcms = aggre1_noc_bcms,
1548 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1549 };
1550 
1551 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1552 	&bcm_ce0,
1553 };
1554 
1555 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1556 	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1557 	[MASTER_QUP_0] = &qhm_qup0,
1558 	[MASTER_QUP_2] = &qhm_qup2,
1559 	[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1560 	[MASTER_CRYPTO] = &qxm_crypto,
1561 	[MASTER_IPA] = &qxm_ipa,
1562 	[MASTER_SENSORS_PROC] = &qxm_sensorss_q6,
1563 	[MASTER_SP] = &qxm_sp,
1564 	[MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1565 	[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1566 	[MASTER_SDCC_2] = &xm_sdc2,
1567 	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1568 	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1569 };
1570 
1571 static const struct qcom_icc_desc sm8450_aggre2_noc = {
1572 	.nodes = aggre2_noc_nodes,
1573 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1574 	.bcms = aggre2_noc_bcms,
1575 	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1576 };
1577 
1578 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1579 	&bcm_qup0,
1580 	&bcm_qup1,
1581 	&bcm_qup2,
1582 };
1583 
1584 static struct qcom_icc_node * const clk_virt_nodes[] = {
1585 	[MASTER_QUP_CORE_0] = &qup0_core_master,
1586 	[MASTER_QUP_CORE_1] = &qup1_core_master,
1587 	[MASTER_QUP_CORE_2] = &qup2_core_master,
1588 	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1589 	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1590 	[SLAVE_QUP_CORE_2] = &qup2_core_slave,
1591 };
1592 
1593 static const struct qcom_icc_desc sm8450_clk_virt = {
1594 	.nodes = clk_virt_nodes,
1595 	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1596 	.bcms = clk_virt_bcms,
1597 	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1598 };
1599 
1600 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1601 	&bcm_cn0,
1602 };
1603 
1604 static struct qcom_icc_node * const config_noc_nodes[] = {
1605 	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1606 	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1607 	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1608 	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1609 	[SLAVE_AOSS] = &qhs_aoss,
1610 	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1611 	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1612 	[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1613 	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1614 	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1615 	[SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1616 	[SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1617 	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1618 	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1619 	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1620 	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1621 	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1622 	[SLAVE_IPA_CFG] = &qhs_ipa,
1623 	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1624 	[SLAVE_LPASS] = &qhs_lpass_cfg,
1625 	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1626 	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1627 	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1628 	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1629 	[SLAVE_PDM] = &qhs_pdm,
1630 	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1631 	[SLAVE_PRNG] = &qhs_prng,
1632 	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1633 	[SLAVE_QSPI_0] = &qhs_qspi,
1634 	[SLAVE_QUP_0] = &qhs_qup0,
1635 	[SLAVE_QUP_1] = &qhs_qup1,
1636 	[SLAVE_QUP_2] = &qhs_qup2,
1637 	[SLAVE_SDCC_2] = &qhs_sdc2,
1638 	[SLAVE_SDCC_4] = &qhs_sdc4,
1639 	[SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1640 	[SLAVE_TCSR] = &qhs_tcsr,
1641 	[SLAVE_TLMM] = &qhs_tlmm,
1642 	[SLAVE_TME_CFG] = &qhs_tme_cfg,
1643 	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1644 	[SLAVE_USB3_0] = &qhs_usb3_0,
1645 	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1646 	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1647 	[SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1648 	[SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1649 	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1650 	[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1651 	[SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
1652 	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1653 	[SLAVE_IMEM] = &qxs_imem,
1654 	[SLAVE_PIMEM] = &qxs_pimem,
1655 	[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1656 	[SLAVE_PCIE_0] = &xs_pcie_0,
1657 	[SLAVE_PCIE_1] = &xs_pcie_1,
1658 	[SLAVE_QDSS_STM] = &xs_qdss_stm,
1659 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
1660 };
1661 
1662 static const struct qcom_icc_desc sm8450_config_noc = {
1663 	.nodes = config_noc_nodes,
1664 	.num_nodes = ARRAY_SIZE(config_noc_nodes),
1665 	.bcms = config_noc_bcms,
1666 	.num_bcms = ARRAY_SIZE(config_noc_bcms),
1667 };
1668 
1669 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1670 	&bcm_sh0,
1671 	&bcm_sh1,
1672 	&bcm_sh0_disp,
1673 	&bcm_sh1_disp,
1674 };
1675 
1676 static struct qcom_icc_node * const gem_noc_nodes[] = {
1677 	[MASTER_GPU_TCU] = &alm_gpu_tcu,
1678 	[MASTER_SYS_TCU] = &alm_sys_tcu,
1679 	[MASTER_APPSS_PROC] = &chm_apps,
1680 	[MASTER_GFX3D] = &qnm_gpu,
1681 	[MASTER_MSS_PROC] = &qnm_mdsp,
1682 	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1683 	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1684 	[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1685 	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1686 	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1687 	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1688 	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1689 	[SLAVE_LLCC] = &qns_llcc,
1690 	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1691 	[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1692 	[MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
1693 	[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1694 	[SLAVE_LLCC_DISP] = &qns_llcc_disp,
1695 };
1696 
1697 static const struct qcom_icc_desc sm8450_gem_noc = {
1698 	.nodes = gem_noc_nodes,
1699 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1700 	.bcms = gem_noc_bcms,
1701 	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1702 };
1703 
1704 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1705 };
1706 
1707 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1708 	[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1709 	[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
1710 	[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1711 	[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1712 	[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1713 	[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1714 	[SLAVE_LPASS_SNOC] = &qns_sysnoc,
1715 	[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1716 	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1717 };
1718 
1719 static const struct qcom_icc_desc sm8450_lpass_ag_noc = {
1720 	.nodes = lpass_ag_noc_nodes,
1721 	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1722 	.bcms = lpass_ag_noc_bcms,
1723 	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1724 };
1725 
1726 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1727 	&bcm_acv,
1728 	&bcm_mc0,
1729 	&bcm_acv_disp,
1730 	&bcm_mc0_disp,
1731 };
1732 
1733 static struct qcom_icc_node * const mc_virt_nodes[] = {
1734 	[MASTER_LLCC] = &llcc_mc,
1735 	[SLAVE_EBI1] = &ebi,
1736 	[MASTER_LLCC_DISP] = &llcc_mc_disp,
1737 	[SLAVE_EBI1_DISP] = &ebi_disp,
1738 };
1739 
1740 static const struct qcom_icc_desc sm8450_mc_virt = {
1741 	.nodes = mc_virt_nodes,
1742 	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1743 	.bcms = mc_virt_bcms,
1744 	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1745 };
1746 
1747 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1748 	&bcm_mm0,
1749 	&bcm_mm1,
1750 	&bcm_mm0_disp,
1751 	&bcm_mm1_disp,
1752 };
1753 
1754 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1755 	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1756 	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1757 	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1758 	[MASTER_MDP] = &qnm_mdp,
1759 	[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1760 	[MASTER_ROTATOR] = &qnm_rot,
1761 	[MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1762 	[MASTER_VIDEO] = &qnm_video,
1763 	[MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1764 	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
1765 	[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1766 	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1767 	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1768 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1769 	[MASTER_MDP_DISP] = &qnm_mdp_disp,
1770 	[MASTER_ROTATOR_DISP] = &qnm_rot_disp,
1771 	[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1772 	[SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
1773 };
1774 
1775 static const struct qcom_icc_desc sm8450_mmss_noc = {
1776 	.nodes = mmss_noc_nodes,
1777 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1778 	.bcms = mmss_noc_bcms,
1779 	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1780 };
1781 
1782 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1783 	&bcm_co0,
1784 };
1785 
1786 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1787 	[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1788 	[MASTER_CDSP_PROC] = &qxm_nsp,
1789 	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1790 	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1791 };
1792 
1793 static const struct qcom_icc_desc sm8450_nsp_noc = {
1794 	.nodes = nsp_noc_nodes,
1795 	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1796 	.bcms = nsp_noc_bcms,
1797 	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1798 };
1799 
1800 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1801 	&bcm_sn7,
1802 };
1803 
1804 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1805 	[MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg,
1806 	[MASTER_PCIE_0] = &xm_pcie3_0,
1807 	[MASTER_PCIE_1] = &xm_pcie3_1,
1808 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1809 	[SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1810 };
1811 
1812 static const struct qcom_icc_desc sm8450_pcie_anoc = {
1813 	.nodes = pcie_anoc_nodes,
1814 	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1815 	.bcms = pcie_anoc_bcms,
1816 	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1817 };
1818 
1819 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1820 	&bcm_sn0,
1821 	&bcm_sn1,
1822 	&bcm_sn2,
1823 	&bcm_sn3,
1824 	&bcm_sn4,
1825 };
1826 
1827 static struct qcom_icc_node * const system_noc_nodes[] = {
1828 	[MASTER_GIC_AHB] = &qhm_gic,
1829 	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1830 	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1831 	[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
1832 	[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1833 	[MASTER_PIMEM] = &qxm_pimem,
1834 	[MASTER_GIC] = &xm_gic,
1835 	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1836 	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1837 	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1838 };
1839 
1840 static const struct qcom_icc_desc sm8450_system_noc = {
1841 	.nodes = system_noc_nodes,
1842 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
1843 	.bcms = system_noc_bcms,
1844 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
1845 };
1846 
1847 static const struct of_device_id qnoc_of_match[] = {
1848 	{ .compatible = "qcom,sm8450-aggre1-noc",
1849 	  .data = &sm8450_aggre1_noc},
1850 	{ .compatible = "qcom,sm8450-aggre2-noc",
1851 	  .data = &sm8450_aggre2_noc},
1852 	{ .compatible = "qcom,sm8450-clk-virt",
1853 	  .data = &sm8450_clk_virt},
1854 	{ .compatible = "qcom,sm8450-config-noc",
1855 	  .data = &sm8450_config_noc},
1856 	{ .compatible = "qcom,sm8450-gem-noc",
1857 	  .data = &sm8450_gem_noc},
1858 	{ .compatible = "qcom,sm8450-lpass-ag-noc",
1859 	  .data = &sm8450_lpass_ag_noc},
1860 	{ .compatible = "qcom,sm8450-mc-virt",
1861 	  .data = &sm8450_mc_virt},
1862 	{ .compatible = "qcom,sm8450-mmss-noc",
1863 	  .data = &sm8450_mmss_noc},
1864 	{ .compatible = "qcom,sm8450-nsp-noc",
1865 	  .data = &sm8450_nsp_noc},
1866 	{ .compatible = "qcom,sm8450-pcie-anoc",
1867 	  .data = &sm8450_pcie_anoc},
1868 	{ .compatible = "qcom,sm8450-system-noc",
1869 	  .data = &sm8450_system_noc},
1870 	{ }
1871 };
1872 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1873 
1874 static struct platform_driver qnoc_driver = {
1875 	.probe = qcom_icc_rpmh_probe,
1876 	.remove = qcom_icc_rpmh_remove,
1877 	.driver = {
1878 		.name = "qnoc-sm8450",
1879 		.of_match_table = qnoc_of_match,
1880 	},
1881 };
1882 
1883 static int __init qnoc_driver_init(void)
1884 {
1885 	return platform_driver_register(&qnoc_driver);
1886 }
1887 core_initcall(qnoc_driver_init);
1888 
1889 static void __exit qnoc_driver_exit(void)
1890 {
1891 	platform_driver_unregister(&qnoc_driver);
1892 }
1893 module_exit(qnoc_driver_exit);
1894 
1895 MODULE_DESCRIPTION("sm8450 NoC driver");
1896 MODULE_LICENSE("GPL v2");
1897