1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4  *
5  */
6 
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <dt-bindings/interconnect/qcom,sm8250.h>
13 
14 #include "bcm-voter.h"
15 #include "icc-rpmh.h"
16 #include "sm8250.h"
17 
18 DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
19 DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);
20 DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV);
21 DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV);
22 DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV);
23 DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1);
24 DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV);
25 DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV);
26 DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV);
27 DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV);
28 DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC);
29 DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV);
30 DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV);
31 DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV);
32 DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV);
33 DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV);
34 DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
35 DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
36 DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV);
37 DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV);
38 DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV);
39 DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC);
40 DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
41 DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
42 DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG);
43 DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
44 DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
45 DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
46 DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC);
47 DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
48 DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
49 DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC);
50 DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
51 DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
52 DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
53 DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
54 DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
55 DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
56 DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
57 DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC);
58 DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
59 DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
60 DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
61 DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
62 DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
63 DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
64 DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
65 DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC);
66 DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC);
67 DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM);
68 DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC);
69 DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
70 DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
71 DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM);
72 DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1);
73 DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
74 DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
75 DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS);
76 DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
77 DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4);
78 DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS);
79 DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
80 DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4);
81 DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC);
82 DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG);
83 DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG);
84 DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4);
85 DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4);
86 DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4);
87 DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4);
88 DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4);
89 DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4);
90 DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4);
91 DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4);
92 DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4);
93 DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4);
94 DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4);
95 DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4);
96 DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC);
97 DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4);
98 DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8);
99 DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4);
100 DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4);
101 DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4);
102 DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4);
103 DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG);
104 DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG);
105 DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4);
106 DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4);
107 DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4);
108 DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4);
109 DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4);
110 DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4);
111 DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4);
112 DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4);
113 DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4);
114 DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4);
115 DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4);
116 DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4);
117 DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4);
118 DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG);
119 DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4);
120 DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4);
121 DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4);
122 DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4);
123 DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4);
124 DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4);
125 DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4);
126 DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4);
127 DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4);
128 DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4);
129 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4);
130 DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC);
131 DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4);
132 DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4);
133 DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG);
134 DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC);
135 DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC);
136 DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC);
137 DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
138 DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
139 DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
140 DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
141 DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
142 DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
143 DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4);
144 DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4);
145 DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4);
146 DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4);
147 DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
148 DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4);
149 DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4);
150 DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4);
151 DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4);
152 DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32);
153 DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4);
154 DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8);
155 DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS);
156 DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC);
157 DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC);
158 DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8);
159 DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
160 DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
161 DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
162 DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
163 DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
164 DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
165 DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
166 
167 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
168 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
169 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
170 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
171 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
172 DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
173 DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
174 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
175 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
176 DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
177 DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
178 DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
179 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
180 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
181 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
182 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
183 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
184 DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
185 DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
186 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
187 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
188 DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
189 DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
190 DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
191 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
192 DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
193 DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
194 
195 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
196 	&bcm_qup0,
197 	&bcm_sn12,
198 };
199 
200 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
201 	[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
202 	[MASTER_QSPI_0] = &qhm_qspi,
203 	[MASTER_QUP_1] = &qhm_qup1,
204 	[MASTER_QUP_2] = &qhm_qup2,
205 	[MASTER_TSIF] = &qhm_tsif,
206 	[MASTER_PCIE_2] = &xm_pcie3_modem,
207 	[MASTER_SDCC_4] = &xm_sdc4,
208 	[MASTER_UFS_MEM] = &xm_ufs_mem,
209 	[MASTER_USB3] = &xm_usb3_0,
210 	[MASTER_USB3_1] = &xm_usb3_1,
211 	[A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
212 	[SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc,
213 	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
214 };
215 
216 static const struct qcom_icc_desc sm8250_aggre1_noc = {
217 	.nodes = aggre1_noc_nodes,
218 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
219 	.bcms = aggre1_noc_bcms,
220 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
221 };
222 
223 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
224 	&bcm_ce0,
225 	&bcm_qup0,
226 	&bcm_sn12,
227 };
228 
229 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
230 	[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
231 	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
232 	[MASTER_QUP_0] = &qhm_qup0,
233 	[MASTER_CNOC_A2NOC] = &qnm_cnoc,
234 	[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
235 	[MASTER_IPA] = &qxm_ipa,
236 	[MASTER_PCIE] = &xm_pcie3_0,
237 	[MASTER_PCIE_1] = &xm_pcie3_1,
238 	[MASTER_QDSS_ETR] = &xm_qdss_etr,
239 	[MASTER_SDCC_2] = &xm_sdc2,
240 	[MASTER_UFS_CARD] = &xm_ufs_card,
241 	[A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
242 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
243 	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
244 };
245 
246 static const struct qcom_icc_desc sm8250_aggre2_noc = {
247 	.nodes = aggre2_noc_nodes,
248 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
249 	.bcms = aggre2_noc_bcms,
250 	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
251 };
252 
253 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
254 	&bcm_co0,
255 	&bcm_co2,
256 };
257 
258 static struct qcom_icc_node * const compute_noc_nodes[] = {
259 	[MASTER_NPU] = &qnm_npu,
260 	[SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
261 };
262 
263 static const struct qcom_icc_desc sm8250_compute_noc = {
264 	.nodes = compute_noc_nodes,
265 	.num_nodes = ARRAY_SIZE(compute_noc_nodes),
266 	.bcms = compute_noc_bcms,
267 	.num_bcms = ARRAY_SIZE(compute_noc_bcms),
268 };
269 
270 static struct qcom_icc_bcm * const config_noc_bcms[] = {
271 	&bcm_cn0,
272 };
273 
274 static struct qcom_icc_node * const config_noc_nodes[] = {
275 	[SNOC_CNOC_MAS] = &qnm_snoc,
276 	[MASTER_QDSS_DAP] = &xm_qdss_dap,
277 	[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
278 	[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
279 	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
280 	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
281 	[SLAVE_AOSS] = &qhs_aoss,
282 	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
283 	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
284 	[SLAVE_CDSP_CFG] = &qhs_compute_dsp,
285 	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
286 	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
287 	[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
288 	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
289 	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
290 	[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
291 	[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
292 	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
293 	[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
294 	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
295 	[SLAVE_IPA_CFG] = &qhs_ipa,
296 	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
297 	[SLAVE_LPASS] = &qhs_lpass_cfg,
298 	[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
299 	[SLAVE_NPU_CFG] = &qhs_npu_cfg,
300 	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
301 	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
302 	[SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg,
303 	[SLAVE_PDM] = &qhs_pdm,
304 	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
305 	[SLAVE_PRNG] = &qhs_prng,
306 	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
307 	[SLAVE_QSPI_0] = &qhs_qspi,
308 	[SLAVE_QUP_0] = &qhs_qup0,
309 	[SLAVE_QUP_1] = &qhs_qup1,
310 	[SLAVE_QUP_2] = &qhs_qup2,
311 	[SLAVE_SDCC_2] = &qhs_sdc2,
312 	[SLAVE_SDCC_4] = &qhs_sdc4,
313 	[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
314 	[SLAVE_TCSR] = &qhs_tcsr,
315 	[SLAVE_TLMM_NORTH] = &qhs_tlmm0,
316 	[SLAVE_TLMM_SOUTH] = &qhs_tlmm1,
317 	[SLAVE_TLMM_WEST] = &qhs_tlmm2,
318 	[SLAVE_TSIF] = &qhs_tsif,
319 	[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
320 	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
321 	[SLAVE_USB3] = &qhs_usb3_0,
322 	[SLAVE_USB3_1] = &qhs_usb3_1,
323 	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
324 	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
325 	[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
326 	[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
327 };
328 
329 static const struct qcom_icc_desc sm8250_config_noc = {
330 	.nodes = config_noc_nodes,
331 	.num_nodes = ARRAY_SIZE(config_noc_nodes),
332 	.bcms = config_noc_bcms,
333 	.num_bcms = ARRAY_SIZE(config_noc_bcms),
334 };
335 
336 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
337 };
338 
339 static struct qcom_icc_node * const dc_noc_nodes[] = {
340 	[MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
341 	[SLAVE_LLCC_CFG] = &qhs_llcc,
342 	[SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
343 };
344 
345 static const struct qcom_icc_desc sm8250_dc_noc = {
346 	.nodes = dc_noc_nodes,
347 	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
348 	.bcms = dc_noc_bcms,
349 	.num_bcms = ARRAY_SIZE(dc_noc_bcms),
350 };
351 
352 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
353 	&bcm_sh0,
354 	&bcm_sh2,
355 	&bcm_sh3,
356 	&bcm_sh4,
357 };
358 
359 static struct qcom_icc_node * const gem_noc_nodes[] = {
360 	[MASTER_GPU_TCU] = &alm_gpu_tcu,
361 	[MASTER_SYS_TCU] = &alm_sys_tcu,
362 	[MASTER_AMPSS_M0] = &chm_apps,
363 	[MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
364 	[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
365 	[MASTER_GRAPHICS_3D] = &qnm_gpu,
366 	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
367 	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
368 	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
369 	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
370 	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
371 	[SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
372 	[SLAVE_LLCC] = &qns_llcc,
373 	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
374 	[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
375 	[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
376 	[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
377 };
378 
379 static const struct qcom_icc_desc sm8250_gem_noc = {
380 	.nodes = gem_noc_nodes,
381 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
382 	.bcms = gem_noc_bcms,
383 	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
384 };
385 
386 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
387 	&bcm_acv,
388 	&bcm_mc0,
389 };
390 
391 static struct qcom_icc_node * const mc_virt_nodes[] = {
392 	[MASTER_LLCC] = &llcc_mc,
393 	[SLAVE_EBI_CH0] = &ebi,
394 };
395 
396 static const struct qcom_icc_desc sm8250_mc_virt = {
397 	.nodes = mc_virt_nodes,
398 	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
399 	.bcms = mc_virt_bcms,
400 	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
401 };
402 
403 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
404 	&bcm_mm0,
405 	&bcm_mm1,
406 	&bcm_mm2,
407 	&bcm_mm3,
408 };
409 
410 static struct qcom_icc_node * const mmss_noc_nodes[] = {
411 	[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
412 	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
413 	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
414 	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
415 	[MASTER_VIDEO_P0] = &qnm_video0,
416 	[MASTER_VIDEO_P1] = &qnm_video1,
417 	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
418 	[MASTER_MDP_PORT0] = &qxm_mdp0,
419 	[MASTER_MDP_PORT1] = &qxm_mdp1,
420 	[MASTER_ROTATOR] = &qxm_rot,
421 	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
422 	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
423 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
424 };
425 
426 static const struct qcom_icc_desc sm8250_mmss_noc = {
427 	.nodes = mmss_noc_nodes,
428 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
429 	.bcms = mmss_noc_bcms,
430 	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
431 };
432 
433 static struct qcom_icc_bcm * const npu_noc_bcms[] = {
434 };
435 
436 static struct qcom_icc_node * const npu_noc_nodes[] = {
437 	[MASTER_NPU_SYS] = &amm_npu_sys,
438 	[MASTER_NPU_CDP] = &amm_npu_sys_cdp_w,
439 	[MASTER_NPU_NOC_CFG] = &qhm_cfg,
440 	[SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
441 	[SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1,
442 	[SLAVE_NPU_CP] = &qhs_cp,
443 	[SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
444 	[SLAVE_NPU_DPM] = &qhs_dpm,
445 	[SLAVE_ISENSE_CFG] = &qhs_isense,
446 	[SLAVE_NPU_LLM_CFG] = &qhs_llm,
447 	[SLAVE_NPU_TCM] = &qhs_tcm,
448 	[SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
449 	[SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
450 };
451 
452 static const struct qcom_icc_desc sm8250_npu_noc = {
453 	.nodes = npu_noc_nodes,
454 	.num_nodes = ARRAY_SIZE(npu_noc_nodes),
455 	.bcms = npu_noc_bcms,
456 	.num_bcms = ARRAY_SIZE(npu_noc_bcms),
457 };
458 
459 static struct qcom_icc_bcm * const system_noc_bcms[] = {
460 	&bcm_sn0,
461 	&bcm_sn1,
462 	&bcm_sn11,
463 	&bcm_sn2,
464 	&bcm_sn3,
465 	&bcm_sn4,
466 	&bcm_sn5,
467 	&bcm_sn6,
468 	&bcm_sn7,
469 	&bcm_sn8,
470 	&bcm_sn9,
471 };
472 
473 static struct qcom_icc_node * const system_noc_nodes[] = {
474 	[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
475 	[A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
476 	[A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
477 	[MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
478 	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
479 	[MASTER_PIMEM] = &qxm_pimem,
480 	[MASTER_GIC] = &xm_gic,
481 	[SLAVE_APPSS] = &qhs_apss,
482 	[SNOC_CNOC_SLV] = &qns_cnoc,
483 	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
484 	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
485 	[SLAVE_OCIMEM] = &qxs_imem,
486 	[SLAVE_PIMEM] = &qxs_pimem,
487 	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
488 	[SLAVE_PCIE_0] = &xs_pcie_0,
489 	[SLAVE_PCIE_1] = &xs_pcie_1,
490 	[SLAVE_PCIE_2] = &xs_pcie_modem,
491 	[SLAVE_QDSS_STM] = &xs_qdss_stm,
492 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
493 };
494 
495 static const struct qcom_icc_desc sm8250_system_noc = {
496 	.nodes = system_noc_nodes,
497 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
498 	.bcms = system_noc_bcms,
499 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
500 };
501 
502 static const struct of_device_id qnoc_of_match[] = {
503 	{ .compatible = "qcom,sm8250-aggre1-noc",
504 	  .data = &sm8250_aggre1_noc},
505 	{ .compatible = "qcom,sm8250-aggre2-noc",
506 	  .data = &sm8250_aggre2_noc},
507 	{ .compatible = "qcom,sm8250-compute-noc",
508 	  .data = &sm8250_compute_noc},
509 	{ .compatible = "qcom,sm8250-config-noc",
510 	  .data = &sm8250_config_noc},
511 	{ .compatible = "qcom,sm8250-dc-noc",
512 	  .data = &sm8250_dc_noc},
513 	{ .compatible = "qcom,sm8250-gem-noc",
514 	  .data = &sm8250_gem_noc},
515 	{ .compatible = "qcom,sm8250-mc-virt",
516 	  .data = &sm8250_mc_virt},
517 	{ .compatible = "qcom,sm8250-mmss-noc",
518 	  .data = &sm8250_mmss_noc},
519 	{ .compatible = "qcom,sm8250-npu-noc",
520 	  .data = &sm8250_npu_noc},
521 	{ .compatible = "qcom,sm8250-system-noc",
522 	  .data = &sm8250_system_noc},
523 	{ }
524 };
525 MODULE_DEVICE_TABLE(of, qnoc_of_match);
526 
527 static struct platform_driver qnoc_driver = {
528 	.probe = qcom_icc_rpmh_probe,
529 	.remove = qcom_icc_rpmh_remove,
530 	.driver = {
531 		.name = "qnoc-sm8250",
532 		.of_match_table = qnoc_of_match,
533 	},
534 };
535 module_platform_driver(qnoc_driver);
536 
537 MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
538 MODULE_LICENSE("GPL v2");
539